Here is the initial revision of the patch-set.
The first patch is quite simple;
it just adds attributes to layers.
The second makes use of them.
In layer context, PCB:Color attribute is recognized
as the layer color definition.
To switch between two versions of the PCB file format
(with layer
Boss just sent around something he got from a consultant on
doing proper EMI design (which I've been doing for years already,
I thought until consultant came up with this):
Eliminate separate Vcc planes.
This ancient practice is long overdue for an overhaul. Years ago, the
leaded capacitors were
On Thu, Oct 15, 2009 at 2:54 PM, Stephen Williams st...@icarus.com wrote:
I was thinking about multi-part symbols, actually. It would be
kool to draw a symbol for all the business pins and another symbol
for the power pins. Then I could have a sheet just for power/gnd.
This is what I would
So your consultant thinks it's a bad idea to have a Vcc plane because
it takes up space that you could use for additional ground planes and
that you might need to run traces ...
... and then urges you to run power traces where?
In the - now empty - Vcc plane layer?
Or in the same layer as your
On Monday 19 October 2009, Bob Paddock wrote:
Boss just sent around something he got from a consultant on
doing proper EMI design (which I've been doing for years already,
I thought until consultant came up with this):
Eliminate separate Vcc planes.
What's he/she smoking, it must be great stuff
Andy Fierman wrote:
So your consultant thinks it's a bad idea to have a Vcc plane because
it takes up space
.
.
.
Hopefully you can gently persuade your boss that this is not quite
what the very expensive consultant meant to say.
So, are there no conditions where leaving out a VCC plane
We want to do powered burn in of populated boards, to catch bad solders
and early component failures. I'm thinking 0-65C.
Chris.
Message: 5
Date: Thu, 15 Oct 2009 19:50:13 -0400
From: Bob Paddock bob.padd...@gmail.com
Subject: Re: gEDA-user: PCB burn in spec?
To: gEDA user mailing list
I can't suggest much that hasn't been already stated.
A good reference book Printed Circuit board design techniques for
EMC compliance (ISBN0-7803-5376-5) it has interesting advice about
different layre stackups and the effects on inductance and decoupling
(now 9 years old but still in print)
for clarification:
... you might imagine times when routing thick
tracks as differential pairs with the ground plane on signal layres [instead
of a Vcc plane].
would make the design less likely to have ground loops or mistakenly
mistakenly
violate moating.
We want to do powered burn in of populated boards, to catch bad solders
and early component failures. I'm thinking 0-65C.
You want to do so-called HALT/HASS testing. One usually does
temperature cycling of the board, maybe humidity, shock vibration,
and other environmental tests.
The testing
On Mon, Oct 19, 2009 at 08:35:33AM -0400, Bob Paddock wrote:
To me running Vcc traces all over the board is the surest way to raise
inductance etc., and seems wrong to me.
Plus in high current, low voltage designs (like FPGA core power) the tiny
series resistance of even a plane can be a
Hello all,
I'm just started using GL version of PCB and I can not find out how to return
to normal view. I open the board then use 3d trackball to change view and
then I want to return to normal 2d view as at the start. Is there any
keystroke or command for this? Trying to get back using
On Mon, 2009-10-19 at 20:28 +0200, michalwd1979 wrote:
Hello all,
I'm just started using GL version of PCB and I can not find out how to
return to normal view. I open the board then use 3d trackball to
change view and then I want to return to normal 2d view as at the
start. Is there any
On Mon, 2009-10-19 at 11:10 +, Ineiev wrote:
Here is the initial revision of the patch-set.
The first patch is quite simple;
it just adds attributes to layers.
The second makes use of them.
In layer context, PCB:Color attribute is recognized
as the layer color definition.
To
On Mon, 2009-10-19 at 20:28 +0200, michalwd1979 wrote:
Hello all,
I'm just started using GL version of PCB and I can not find out how to
return to normal view. I open the board then use 3d trackball to
change view and then I want to return to normal 2d view as at the
start. Is there
Hi all, an interesting discussion thanks for sharing it with the list.
I have done the star topology Vcc design as is described here with great
results, but only in the correct set of circumstances.
Most of the PCB design I do for work is RF related typically 900MHz to about
5GHz, for
On Mon, 2009-10-19 at 21:55 +0200, michalwd1979 wrote:
Thank You Peter, it works!
I know that this is very experimental branch, but let me suggest something.
It would be nice if holes pads and vias would have walls. Now it is
sometimes confusing to find out which pad is which if board is
Neil -
On Mon, Oct 19, 2009 at 01:20:23PM -0700, Neil Hendin wrote:
If you look at the RF S-Parameters of the capacitor at frequencies
above the self resonance, they look inductive, not capacitive.
I'm not sure what the precise definition is for the S-Parameters
of a two-terminal device, but
I second this request. All of the quantitative data that I have seen
basically says that for a given dielectric, the inductance is a
function of the package size and shape regardless of the capacitance.
And yet the rule of thumb continues to be mixing capacitor values to
handle a range of
Larry Doolittle wrote:
Good RF decoupling standard practice is to use a smaller cap
(e.g. 20pF in parallel with some larger ones such as 1000pF
_and_ 0.1uF or larger as needed) to get a good broad band
capacitive reactance across frequency).
I have yet to see a 20pF or 1000pF cap with less
On Mon, 19 Oct 2009 20:13:40 +0100, Peter Clifton wrote:
To switch between two versions of the PCB file format (with layer
attributes and without them), preserve_layer_attribute flag is added;
Does the presence of layer attributes break anything with non-patched pcb
versions? In other words,
On Mon, Oct 19, 2009 at 5:27 PM, Dan McMahill d...@mcmahill.net wrote:
my recent experiences are more in line with Larry's. Most C for a given
package and voltage seems to be the best meaning that above resonance it
is no worse than smaller capacitance value devices and below resonance
it is
On Monday 19 October 2009, Dan McMahill wrote:
Larry Doolittle wrote:
Good RF decoupling standard practice is to use a smaller cap
(e.g. 20pF in parallel with some larger ones such as 1000pF
_and_ 0.1uF or larger as needed) to get a good broad band
capacitive reactance across frequency).
I
On 10/19/09, Kai-Martin Knaak k...@familieknaak.de wrote:
On Mon, 19 Oct 2009 20:13:40 +0100, Peter Clifton wrote:
Why do we need a tick box to preserve layer attributes? IMO, layer
attributes should _always_ be preserved.
+1
(unless layers attributes have to be skipped for backward
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