Rubén Gómez Antolí l...@mucharuina.com writes:
Hi again:
El 08/04/11 01:30, Peter Clifton escribió:
On Thu, 2011-04-07 at 16:00 -0600, John Doty wrote:
On Apr 7, 2011, at 3:06 PM, Rubén Gómez Antolí wrote:
You are right but, what about the users?
I *am* a user.
I'm too.
Both of you
On Apr 8, 2011, at 1:13 AM, Stephan Boettcher boettc...@physik.uni-kiel.de
wrote:
rickman gnuarm.g...@arius.com writes:
I have to say I am philosophically opposed to any feature that allows
a design to pass DRC when the layout differs from the schematic.
Just to get the
On 4/7/2011 1:13 PM, Stephan Boettcher wrote:
rickmangnuarm.g...@arius.com writes:
I have to say I am philosophically opposed to any feature that allows
a design to pass DRC when the layout differs from the schematic.
Just to get the terminology right:
DRC has no business to care about the
On Fri, Apr 8, 2011 at 9:39 AM, rickman gnuarm.g...@arius.com wrote:
On 4/7/2011 1:13 PM, Stephan Boettcher wrote:
rickmangnuarm.g...@arius.com writes:
I have to say I am philosophically opposed to any feature that allows
a design to pass DRC when the layout differs from the schematic.
On Fri, Apr 8, 2011 at 11:39 AM, rickman gnuarm.g...@arius.com wrote:
On 4/7/2011 1:13 PM, Stephan Boettcher wrote:
rickmangnuarm.g...@arius.com writes:
I have to say I am philosophically opposed to any feature that allows
a design to pass DRC when the layout differs from the schematic.
On 4/8/2011 12:57 PM, Mark Rages wrote:
On Fri, Apr 8, 2011 at 11:39 AM, rickmangnuarm.g...@arius.com wrote:
On 4/7/2011 1:13 PM, Stephan Boettcher wrote:
rickmangnuarm.g...@arius.comwrites:
I have to say I am philosophically opposed to any feature that allows
a design to pass DRC when
On 04/08/2011 11:44 AM, Russell Dill wrote:
I'm not sure if it could be done simpler, but for a special copper
trace that connects two planes, you would do DRC twice, one time
ignoring between the trace and plane A, and another between the trace
and plane B.
That is a method consistent with
The gEDA mailing lists are archived off the gEDA web page:
http://geda.seul.org/wiki/geda:mailinglists
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On Apr 8, 2011, at 1:22 AM, Stephan Boettcher wrote:
I do not see a conflict between GUI and make, the first ist a good way
to make features of the second discoverable.
Only if each individual tool is *simple*. Complex menus make features *less*
discoverable. Besides, if your use case
Date: Fri, 8 Apr 2011 14:48:19 -0400
From: DJ Delorie d...@delorie.com
The gEDA mailing lists are archived off the gEDA web page:
http://geda.seul.org/wiki/geda:mailinglists
Thank you
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# From: Kai-Martin Knaak knaak@xxx
# Date: Thu, 07 Apr 2011 13:32:42 +0200
Vincent wrote:
How the inherited attributes are entered in components? I couldn't
find
any information. I modified some preexisting component and then
entered
new name, footprint etc. If check the box
Hello:
First of all, a aclaration for Stephan Boettcher: I'm not refering how
power users to a CLI users, power users is a user that have a great
knowledge of using the tools, all the tools including makefiles, bash,
gEDA... I'm a CLI users and, certainly, I'm not a power user.
El 08/04/11
John Griessen:
...
Do we have a way to make a zero Ohm two terminal footprint with some copper
inside,
or pad overlap, that connects the pads and fits with the pcb program?
I can't remember for sure, but think not...
Another way to say that is, can we have footprint
numbered pads of
# shorting trace
Pad [ -1.550mm 0.000mm1.550mm 0.000mm 0.5mm 0.5mm 0.700mm c c
square ]
Perhaps a new flag for pads that means non-net copper ? Then
square,nonnet (for example) tells 'o' to ignore that copper when
determining connectivity, but DRC would still check it for
On Fri, 2011-04-08 at 16:29 -0400, Vincent wrote:
Here are the 2 sym original and the modified respectively.
You have modified much...
This is the output of gsymcheck for the second symbol, please check.
stefan@AMD64X2 ~/ttt $ gsymcheck -vv s2.sym
Read garbage in [/home/stefan/ttt/s2.sym] :
On Fri, Apr 8, 2011 at 2:18 PM, DJ Delorie d...@delorie.com wrote:
# shorting trace
Pad [ -1.550mm 0.000mm 1.550mm 0.000mm 0.5mm 0.5mm 0.700mm c c
square ]
Perhaps a new flag for pads that means non-net copper ? Then
square,nonnet (for example) tells 'o' to ignore that copper
In theory, we could support that flag in *any* object, but I'm not
sure how to manage the relationship between, say, a non-net trace on
an inner plane and the schematic/netlist. I asked someone who used a
BigName EDA package how they did it, and they had a completely
different class of
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