d completely acceptable for this particular project. See the attached
> layout.
That's a neat layout. It will look even neater if you use the "Miter"
trace optimiser - it really helps to tidy up after the autorouter.
Make sure to uncheck the "Only autorouted nets" f
u'll no longer have to
deal with the bit rot by yourself.
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
$39 Spartan 6 board with 32MB DDR DRAM ?
http://www.sioi.com.au/shop/product_info.php/products_id/47
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s
> quite annoying for all of the layers to be re-enabled if you're in the
> middle of routing. I'll look into that later.
+1
Very annoying with multi layer boards and a work flow that involves
frequent changes to the PCB from gedit.
Stephen Ecob
Silicon On Inspiration
Sydney Austr
ut the very common case is just a single fault, very often
that via with extra thermals on a wrong layer.
If only I had time for more than pseudo code at the moment!
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
$39 Spartan 6 board with 32MB DDR DRAM ?
h
o luck.
> Is there a patch which improves the functionality and actually locates
> the position of this short, or do I have to rip up large areas of my
> board until I get to it?
The orange ring on the left pad of I2 looks suspicious - what happens
if you delete I2 ?
Stephen Eco
too many layers there than in
the GUI.
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
$39 Spartan 6 board with 32MB DDR DRAM ?
http://www.sioi.com.au/shop/product_info.php/products_id/47
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nge ring around it. This is how the UI shows where two nets are
shorted.
A common mistake I make is to add thermals to a via on the wrong layer
- this usually results in a short circuit but I can quickly spot it
because of the orange ring.
Stephen Ecob
Silicon On Inspiration
Sydney Australia
w
> Even conversion of old legacy Altium designs could be done given access
I expect there will be a growing demand for exit options for Altium
users once the full impact of their recent upheaval settles in. It
could benefit the gEDA community to adopt Altium refugees - they're
used to spending $4K
as well. Those
> might also be useful options for a layer to have.
Nice idea, I'd use those.
--
Stephen Ecob
Silicon On Inspiration
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A few hours in the future, Andrew Poelstra wrote:
> On Tue, Aug 23, 2011 at 09:52:19AM +1000, Stephen Ecob wrote:
>> A few hours in the future, Andrew Poelstra wrote:
>> * Hide all layers button
>>
>> * Show all layers button
>
> These would be easy enough t
boards.
* Store layer colours and visibility data in the .pcb file. I often
work with a flow where I make changes to a .pcb in a text editor and
then import them into PCB with the "revert" function. It's a real
nuisance to lose my layer visibility state every time I revert.
--
Step
> With this in mind, I have implemented the italicized/separated
> suggestion. You can see it here:
>
> http://www.wpsoftware.net/andrew/dump/mockup4.png
404 error - did you get the URL wrong ?
--
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www
;Layer "Vias" can be displayed or hidden, but cannot be selected as
the current editing layer'
Just my $0.02, don't know how much work it would be to code these.
Regards,
Stephen
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
_
they are as opposed to
> some conditions of use of the website, which they are not.
Thanks for those pointers, they are just the sort of thing I was looking for :-)
Best regards,
Stephen
Stephen Ecob
Silicon On Inspiration
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e current layer, as my
focus is usually close to the center of the screen.
Stephen Ecob
Silicon On Inspiration
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e visible (change of
> fill color and text color with inset or outset border). Maybe something
> better can be done.
Photoshop (and also GIMP) use a small on/off icon that looks like an
eye to control layer visibility. This may or may not be a good way to
do it, but it is certainly a familiar
ints.
It helps to have the "Message Log" window open (you'll find it in the
"Window" menu). IIRC missing footprints are listed in the message log
when you load the board.
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
Thanks to all who have replied, I've received some really useful feedback.
The most commonly repeated comment was that the animated price tags
are just plain irritating. I'll put their removal on the slate for the
first refresh of the web site ;-)
Thanks and best regards,
Stephen
__
7;s anything amiss - would you consider buying the
product, or is there something in the site that would deter you ?
TIA,
Stephen
Stephen Ecob
Silicon On Inspiration
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spond..time out error.
You can use a cached copy:
http://webcache.googleusercontent.com/search?q=cache:http://vivara.net/cgi-bin/djboxsym.cgi
Stephen Ecob
Silicon On Inspiration
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www.sioi.com.au
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gattrib program. I lay out my schematic without assigning
footprints, and then open the schematic in gattrib and assign them in
one go. gattrib has a spreadsheet style layout so I can quickly and
easily assign footprints, change values etc. gattrib is included in
most distributions of gED
Contribute you mods back to
the community when you're done, if you wish.
Stephen Ecob
Silicon On Inspiration
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www.sioi.com.au
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r making the symbols I need is DJboxsym:
http://vivara.net/cgi-bin/djboxsym.cgi
This tool is very convenient for my FPGA work, but when I'm working
with BJTs, FETs, diodes and triacs I use the graphical route.
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
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his type of thing:
http://www.avx.com/docs/catalogs/9158.pdf
Those Tag Connect parts look nicer though, Solo Stacker has optional
lugs for alignment but no mechanism for locking
What's the pricing like for the Tag Connect parts ?
Regards,
Stephen
Stephen Ecob
Silicon On Inspir
On Wed, Aug 10, 2011 at 4:25 PM, DJ Delorie wrote:
>
> That would be www.gpleda.org, our own home page ;-)
>
> Click on "Links" in the upper right.
Thanks DJ :)
I'm embarassed - I looked at www.gpleda.org but totally missed it!
Stephen
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possible.
TIA,
Stephen
--
Stephen Ecob
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On Thu, Jul 28, 2011 at 5:35 AM, yamazakir2 wrote:
> I sometimes get boards done at 4pcb, I didn't know they do assembly.
> How much to they charge? And how big of a reel do you have to send
> them? And you just cut tape the amount of parts you need to assemble
> the amount of boards you want to m
On Thu, Jul 14, 2011 at 1:18 AM, David C. Kerber
wrote:
> Hi, electronics gurus -
>
> We have an application where we need to passively monitor a digital current
> loop (no data sending by us), with a data rate of 9600 baud. We already have
> solutions for tapping into the circuit, but in some
On Thu, Jun 30, 2011 at 2:23 AM, George Boudreau
wrote:
> Hi.
> I am working on a micro-stripline layout and the presence of the
> soldermask on portions of the board will cause problems. With gEDA/pcb
> micro-stripline work is a drafting task consisting of numerous
> polygons. Is there
On Fri, Jun 24, 2011 at 9:43 AM, Ethan Swint wrote:
> On 06/23/2011 07:21 PM, Ethan Swint wrote:
>>
>> On 06/24/2011 03:45 AM, Andrew Poelstra wrote:
>>>
>>> On Wed, Jun 22, 2011 at 09:26:09PM -0700, Russell Dill wrote:
I was selecting a net when PCB crashed.
>>> Has anyone else see
On Wed, Jun 22, 2011 at 6:50 AM, Andrew Poelstra wrote:
> We are working on moving pcb toward metric base units -- then
> a mm would be 10^6 nm rather than "about 3937.00787 cmils"
> like we have now.
Thanks for your work on this Andrew, it is a much anticipated improvement :)
I see that you've
On Wed, Jun 1, 2011 at 6:59 AM, Thomas Oldbury wrote:
> Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like
> each jumper to have a refdes and BOM entry if possible.)
The hack I use for solder jumpers is to make a footprint that is open
circuit, and bridge where needed with
>> The trace optimizer only touches autorouted tracks by default - if you
>> want it to work on manually routed traces you need to clear the
>> "Connects -> Optimize routed tracks -> [/] Only autorouted nets"
>> checkbox.
>
> Thanks for the suggestion, but it messed up the layout something
> wicke
On Tue, May 31, 2011 at 7:21 AM, Richard Rasker wrote:
> Op donderdag 26-05-2011 om 22:56 uur [tijdzone +1000], schreef Stephen
> Ecob:
>> > Then two more usage questions:
>> > - Zero length lines in PCB: I found that when drawing lines in PCB,
>> > sometimes dot
>> > - Zero length lines in PCB: I found that when drawing lines in PCB,
>>
>> I think you're tripping over the metric-rouding bug, where what you're
>> seeing is lines that are 0.01 mil long. We're working on that with
>> the metrification of PCB.
>
> Is there already some sort of script to elimi
> Then two more usage questions:
> - Zero length lines in PCB: I found that when drawing lines in PCB,
> sometimes dots (zero length lines) get created inadvertently on corners
> and bends. This isn't much of a problem, until I start dragging lines
> and end points in rubber band mode: those dots t
On Wed, May 25, 2011 at 5:25 PM, Tom Pope wrote:
> Just dwelling on the 'what' phase a little more, can we start a few
> pages on the wiki for people to list:
>
> a) all the workflows people would like supported (maybe break it down
> into newby GUI workflows, 'power user' GUI workflows and script
> I would like to see some options added to the symbol library dialogue:
>
> 1. Create a new (e.g. local) library
> 2. Copy an existing symbol to another (e.g. local) library
> 3. Create a completely new symbol (perhaps using a wizard interface)
Incorporating DJboxsym (or similar) into the wizard
On Sat, May 21, 2011 at 1:26 AM, Kai-Martin Knaak
wrote:
> Colin D Bennett wrote:
>
>> Not to get into the whole light/heavy symbol debate
>
> Maybe, it is time to look at this issue again. When I first read geda
> documentation, there were already references that this had been discussed
> ad naus
footprint converts fine for PCB fetched from GIT on 2011-03-29
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On Thu, May 5, 2011 at 5:43 AM, Rob Butts wrote:
> I'm not clear on the groups in the PCB preferences. If I want to auto
> route a board in 4 layers how do I set up the groups?
> Thanks
>From PCB Preferences -> Layers -> Change group you can add or remove
layers, and change their order.
Gr
On Wed, May 4, 2011 at 7:37 AM, Peter Clifton wrote:
> On Tue, 2011-05-03 at 19:46 +0200, Kai-Martin Knaak wrote:
>> Peter Clifton wrote:
>>
>> > I'm very close to being able to push the basic 2D portions of PCB+GL
>> > into git HEAD.
>>
>> I feel like a supporter at the course of a marathon race:
On Mon, May 2, 2011 at 9:16 AM, Rob Butts wrote:
> Really? So now instead of having a nice clean schematic with net names
> like clk, _clk, reset and _reset I have to have clk:1, _clk:1...
> Is the way around that making the net attribute not visible and making
> the value attribute visib
On Mon, May 2, 2011 at 8:49 AM, Rob Butts wrote:
> I'm using out and in symbols in gschem to label nets in a schematic and
> tie nets together without traces running everywhere. I set the net
> attribute of the corresponding out and in symbols in the schematic to
> the same value (clk for
> What, if there was a way to flag a track as "don't look" for connectivity
> check? You'd attach the flag to the segment that bridges the domains.
> That way, the DRC check would still be sensitive to violations at other
> places. Such a DRCignore flag might have more legitimate uses. E.g, the
> o
On Fri, Mar 25, 2011 at 5:36 PM, yamazakir2 wrote:
> Anybody know of a source, other than digikey, that sells prefabbed
> prewound SMPS transformers? Digikey has a few, but their selection
> pretty limited.
Shinhom have some:
http://www.shinhom.com/produc6-1.htm
Their prices are pretty good, bu
My favorite tool for desoldering is a hot air blower. It may look
like a glorified hair dryer, but it works like a charm. No damaged
tips either :-)
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I'm looking for PCIe x1 footprints, both card and motherboard sides.
Ethan Swint posted PCIe x4 footprints to this list in February 2009,
my current plan is to reduce these down to PCIe x1.
Has anyone used Ethan's footprints ? It'd be nice to know if they've
been fabbed and loaded successfully, or
> The policy is that we allow anyone to write plugins for their own use,
> and if they want to share them, they may. I see no reason to require
> authors to contribute their plugins to the core pcb code if they do
> not wish to.
I don't want to /require/ anyone to do anything :) Both plugins are
So DJ's teardrop plugin and Ben Jackson's smartdisperse plugin are now
both broken because of changes made to PCB head in the last few
months.
This raises a question for me - should these plugins be incorporated
into PCB head ?
These plugins were written before I joined this list, has the
rationale
On Thu, Feb 24, 2011 at 9:34 AM, yamazakir2 wrote:
> Can I use this instead of distilled water?
>
> http://www.mgchemicals.com/products/406b.html
Looks like you could use it after IPA for cleaning off rosin type
fluxes. Could be worth a try.
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On Thu, Feb 24, 2011 at 8:46 AM, yamazakir2 wrote:
> So am I getting this right?
>
> Step 1. Flux Remover
> Step 2. Wash with soap and water (dish soap)
> Step 3. Wash with Isopropyl Alcohol
> Step 4. Dry
Yes, if the water has low mineral content.
> That should leave me with a nice clean board c
> Thanks for the helpful information. Are ICs and LEDs generally fine to
> wash in water and/or detergent?
Yes, should be fine - but probably a good idea to post wash with
alcohol and certainly give them a good dry.
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It's crucial for parts to be quite dry *before* soldering - otherwise
the rapid boiling of trapped moisture can cause components to crack.
*After* soldering, it's much less of an issue. Many components can be
washed with water and detergent, no problem. Most resistors, ceramic
caps and tantalum c
On Mon, Feb 21, 2011 at 1:51 PM, Kai-Martin Knaak wrote:
> Ineiev wrote:
>
>> Pushed to git-head.
>
> Great!
> Congrats to your new status!
> The geda project got a new dev!
> This is really good news :-)
+1 :-)
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On Thu, Feb 17, 2011 at 8:38 AM, Ben Jackson wrote:
> I would not recommend CustomPCB (aka Silver Circuits) for a 50 board
> run. I've used them before and the individual boards have required too
> much attention to imagine using them for 50+. I got one batch where
> most of the vias did not con
On Thu, Feb 17, 2011 at 7:59 AM, yamazakir2 wrote:
> The board size is 6.275x1.705. Modest amount of holes/vias, nothing
> too crazy. Tolerances are standard, I think the default setup in pcb.
>
> Shipping to the US, specifically CA.
Then it's certainly do-able. The price from custompcb.com for t
On Thu, Feb 17, 2011 at 7:32 AM, yamazakir2 wrote:
> Does anybody know where I can order 50 boards with the price per board
> at the most $5?
>
> The closest I could find was 150 boards with $4.47 per board cost at
> Advanced Circuits. Their 50 qty order is $9.94 :(
What board size ?
Try:
http:
I've added this patch to the corresponding LaunchPad bug, #718342
My opinion is that the patch improves PCB's generation of the solder
paste and has a very low risk of creating undesired side effects. I
recommend it for early incorporation into GIT head.
_
On Tue, Feb 15, 2011 at 10:14 AM, DJ Delorie wrote:
>
>> Limiting the paste size to min(Mask, Thickness) seems like a good
>> idea, but can anyone think of a case where you'd actually want the
>
> Can you add a check for a fully tented pad? I.e. if mask==0, don't
> draw anything?
Sure.
--- a/sr
> Right now I've got PhD work which I'm failing at (I'm on medical leave
> due to being depressed), and some part-time paid work trying to avoid
> going broke (which is otherwise imminent) so I can keep paying the rent.
Do take care - I've had depression and know how debilitating it is.
I really v
On Mon, Feb 14, 2011 at 8:08 AM, Kai-Martin Knaak wrote:
>>> 2) Pads partly covered by solder mask should receive a solder mask
>>> pillow that corresponds to the hole in the mask, rather than to the
>>> pads copper dimensions. Such partly covered pads are useful as a heat
>>> sink.
This patch a
>>> 2) Pads partly covered by solder mask should receive a solder mask
>>> pillow that corresponds to the hole in the mask, rather than to the
>>> pads copper dimensions. Such partly covered pads are useful as a heat
>>> sink.
>>
>> Yes, that works fine - see S005.fp. This is for a SMD bridge and
On Mon, Feb 14, 2011 at 6:27 AM, Kai-Martin Knaak wrote:
> Hi.
> The solder paste pattern emitted by PCB seems to coincide exactly with
> the copper of the pads. This is a reasonable default. But there are use
> cases where a different solder paste size is better.
>
> 1) A pad completely covered w
On Tue, Feb 1, 2011 at 9:25 AM, Joshua wrote:
> Here is an update for refdes_renum_slot.
>
> New Feature:
> The tool now takes into consideration the components x position along with
> its y position when assigning a part number. Thus a screen full of
> components will be numbered from left to ri
A quick solution is to just use large round holes - large enough to
accept the rectangular pins. A bit ugly, but I've successfully done
that in the past. If you're going to wave solder it would be wise to
talk with your assembler about whether their wave machine will handle
it well.
Another appr
> The main problem I have is not code, but deciding what such geometry
> needs to look like it and how to specify it. Whatever we decide we have
> to live with, as we can't go changing geometry on users with existing
> boards.
I think it would be acceptable to change geometry on the community if
i
> Flux is the secret... Applying flux is the crucial step to success.
+1
Get yourself some good quality flux, it makes this sort of problem disappear.
I've used Electrolube SMFL (aerosol with dispenser tube) with good
results, but there are many good options. Look for something with
"surface moun
> Similar to the last is a jumper location that is connected by copper by
> default to be cut if an open is needed. Consider this to be a 1 bit PROM.
>
> Rick
Yes, they're useful. I use them a lot on early revision boards when
the design is still subject to change in some areas.
__
> A similar "track is component" scenario:
>
> PCB fuse track - a dirty trick I've seen in some Honywell boiler
> controllers.. where a deliberately thin trace is used to act as a fuse.
That certainly is a dirty trick! (But on a very tight budget it could
make sense).
So there are several use cas
> Perhaps I was going a bit far to suggest full DRC for the actual antenna
> design. What I really meant was not loosing information for net
> connectivity checking leading up the antenna.
Thinking longer term, why not support DRC checking of inductance and
resistance for specially tagged traces ?
On Fri, Jan 14, 2011 at 7:22 AM, Tamas Szabo wrote:
> I made a loop antenna (for ZigBee too), same problem. I ignore DRC.
>
> There was a thread about it, maybe a year ago or more, without any good
> solution.
I've had similar problems when making low value resistors out of
copper tracks and whe
On Fri, Dec 10, 2010 at 2:09 PM, Peter Clifton wrote:
> On Fri, 2010-12-10 at 11:26 +1100, Stephen Ecob wrote:
>> Hi Peter,
>> Here's my patch that should be equivalent to your patches 0001
>> followed by 0002.
>> My patch
On Fri, Dec 10, 2010 at 10:27 AM, wrote:
> How about a Kickstarter project for the toporouter? Let Anthony make
> a proposal and put it on www.kickstarter.com, and then gEDA users can
> pledge donations. If it raises enough money by graduation (or
> whatever other deadline), then we all fund An
On Fri, Dec 10, 2010 at 9:45 AM, myken wrote:
>> fund a full time developer. But it's nothing more than a pipe dream
>> unless there are others out there who think the same.
>> Does anyone else think the same ?
>
> I think the same, but I am also in the same position (start-up, tight
> cashflow)
> I'd welcome feedback from people who actively encounter and report bugs
> (especially in favour of the move ;)).
>
> I'd also welcome feedback from anyone who works with bug reports, test
> patches, merge code etc... (Doesn't have to be with gEDA / PCB, anything
> regarding Launchpad / SourceForg
> I'm aiming to finish University in a few months.. if people would
> like to fund work on the toporouter, then I would be pretty keen to
> work on it full time.
>
> Regards,
> Anthony
Good, we've established that money could help to improve gEDA :) What
I'm *very* unsure of is whether we could
On Thu, Dec 9, 2010 at 7:46 PM, uv wrote:
> Dears,
>
> Is there any simple way to hide all component numbers on the board?
>
> Thank you
>
> Péter Papp
Yes:
1. Select all (Alt+A or use the menu Edit -> Select all visible)
2. Enter command mode by typing :
3. Type the command ToggleHideName(Selec
On Thu, Dec 9, 2010 at 7:06 PM, Peter Brett wrote:
>> 1. Would any of the existing maintainers be able to devote more time
>> to gEDA if they had financial support to do so ?
>
> In my case: yes. :-/
>
> Peter
OK, so that's a 'yes' for question 1!
Now for question 2 - money.
A few weeks
On Thu, Dec 9, 2010 at 3:16 PM, DJ Delorie wrote:
>
> There were a bunch of projects scheduled, but even LF couldn't
> generate enough funding for more than one of them.
I'm sorry to hear that :(
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htt
On Thu, Dec 9, 2010 at 3:11 PM, DJ Delorie wrote:
>
>> * You wrote the very useful visual DRC system with some financial help
>> from Linux Fund.
>
> No, I did the schematic importer.
Sorry, I must have misunderstood - that was the impression I got from
reading this page:
http://www.linuxfund.or
On Thu, Dec 9, 2010 at 2:59 PM, DJ Delorie wrote:
>
> If you want to hire a maintainer, consider that the average senior
> engineer costs about $200k per year, if you include benefits - and if
> you want a full time engineer, you'd have to provide them because
> you'd be replacing their regular jo
Boiling it down greatly, Clif and Kaimartin are both asking for more
attention from the maintainers. Has the gEDA community given thought
to the possibility of paid maintainers ? I'm a relative newbie,
please let me know if this has already been thrashed through. If it
is worth discussing, I gue
Sorry about that :-(
I've created a patch which fixes it, sourceforge patch ID 3132699:
https://sourceforge.net/tracker/?func=detail&aid=3132699&group_id=73743&atid=538813
FixSmash.patch
Description: Binary data
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On Thu, Dec 9, 2010 at 6:56 AM, DJ Delorie wrote:
>
> Anything that's STRING in parse_y.y starts off as NULL if it's the ""
> string. This is done in parse_l.l.
My assumption was wrong, thanks for spotting that DJ.
Peter, as a consequence:
create.c:789 should use STRDUP() to support NULL pin Num
On Thu, Dec 9, 2010 at 5:58 AM, DJ Delorie wrote:
>
>> quick read about gschem's approach to multiple page schematics quickly
>> convinced me that I'd rather shrink my symbols and keep to one page
>
> You don't need to shrink your symbols. Symbols don't have an absolute
> size like footprints - t
On Thu, Dec 9, 2010 at 5:52 AM, DJ Delorie wrote:
>
>> Yes, it will be fine. A pad must always have a valid number.
>
> Um, no?
>
>> Oh yes, my mistake - I forgot that there are two calls on adjacent
>> lines. strdup (Number) should be fine as a pin must always have a
>> number.
>
> Again... Um,
On Thu, Dec 9, 2010 at 4:22 AM, Kai-Martin Knaak
wrote:
> Hi.
> Thanks to the little scheme script print.scm distributed with geda,
> I finally managed to do non-interactive print of more complex projects.
> Attached to this mail you can find a little script that descends recursively
> down a hier
On Thu, Dec 9, 2010 at 12:24 AM, Peter Clifton wrote:
> On Wed, 2010-12-08 at 14:26 +1100, Stephen Ecob wrote:
>> Patch0002: we're getting close. I see only one remaining issue:
>>
>> create.c:900: you address this both in patch 0001 and patch 0002
>> In patch 00
On Thu, Dec 9, 2010 at 12:10 AM, Peter Clifton wrote:
> On Wed, 2010-12-08 at 13:40 +1100, Stephen Ecob wrote:
>> Regarding 0002-Not-so-sure-about-these-MyStrdup-calls.patch:
>>
>> buffer.c:984: I can't tell, and suggest playing it safe with STRDUP()
>
> if (li
Patch0002: we're getting close. I see only one remaining issue:
create.c:900: you address this both in patch 0001 and patch 0002
In patch 0001 you preserve the behaviour of the existing code
In patch 0002 you unconditionally call strdup()
I've looked at the code further, and I think that the appro
Regarding 0002-Not-so-sure-about-these-MyStrdup-calls.patch:
buffer.c:984: I can't tell, and suggest playing it safe with STRDUP()
create.c:593: My $0.02: CreateNewText() called with a NULL pointer
should be stopped in its tracks with a segfault rather than
propagating the error. If you're unsure
On Wed, Dec 8, 2010 at 4:51 AM, Peter Clifton wrote:
> Stephen, I'd appreciate your Acked-by: or Reviewed-by: on the attached
> patches:
Patch 0001 is good, but I can suggest some additional MyStrdup() calls
that can safely be directly replaced with strdup():
create.c
196: safe because DefaultLa
On Wed, Dec 8, 2010 at 12:52 AM, Peter Clifton wrote:
> Note that the second patch gets my test PCB loading again, but does not
> consider every possible case.
>
> Before committing, these MUST be squashed, but it is convenient to keep
> them separate for now.
>
> Thinking about it, a pre-patch co
> Agreed, and I had a similar experience. I was hoping to get a review or just
> some comments on a couple of patches I submitted (3114991, 3117075). Now I
> can understand that it was probably in an off beat area and not the topic du
> jour, so I went ahead and posted it to the patches tracker. No
I just submitted a patch for some memory leaks that have been annoying
me. The soureforge id is #3131063:
https://sourceforge.net/tracker/?func=detail&aid=3131063&group_id=73743&atid=538813
Most users won't have noticed these leaks as only around 1MB is leaked
each time a new PCB is loaded. The
On Tue, Dec 7, 2010 at 3:06 PM, timecop wrote:
>> 5. retain the MYFREE() macro as its pointer clearing side effect is required
>> 8. Instead of simply retaining MYFREE(p) (point 5), we could replace
>> each use of it with an explicit:
>> free(p);
>> p = NULL;
>
> Is this "MY" prefix actually in
I propose the following solution:
1. replace all calls to MyCalloc() with calls to calloc()
2. replace all calls to MyMalloc() with calls to malloc()
3. replace all calls to MyRealloc() with calls to realloc()
4. replace all calls to SaveFree() with calls to free()
5. retain the MYFREE() macro as
I count 54 locations in head that call MyStrdup()
A run time check of calls to MyStrdup() shows:
create.c:197 made 0 NULL calls, 48 good calls
create.c:219 made 0 NULL calls, 32 good calls
create.c:238 made 0 NULL calls, 1 good calls
create.c:240 made 0 NULL calls, 1 good calls
create.c:286 made 1
On Tue, Dec 7, 2010 at 11:48 AM, Peter Clifton wrote:
> On Tue, 2010-12-07 at 10:04 +1100, Stephen Ecob wrote:
>
>> Dropping the (a) ? (a) : 1 foolishness would be cleaner, but could
>> expose latent bugs in the 71 callers of the mymem allocators.
>> I'm happy to proc
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