al davis wrote:
On Saturday 10 May 2008, Dan McMahill wrote:
I think you want to declare your signals that you have listed
as 'voltage' as 'electrical'. Thats assuming verilog-ams
doesn't do things differently from verilog-a which I'm more
familiar with.
voltage is ok ..
It is defined
Does anybody have access to a Verilog-AMS tool and can said person
attempt to run the attached sample program? It is a very simple
program, but it is an attempt to test some of my understanding of
very basic principles of Verilog-AMS.
I understand that Verilog-AMS tools are very few and very
Stephen Williams wrote:
Does anybody have access to a Verilog-AMS tool and can said person
attempt to run the attached sample program? It is a very simple
program, but it is an attempt to test some of my understanding of
very basic principles of Verilog-AMS.
I understand that Verilog-AMS
Dan McMahill wrote:
Stephen Williams wrote:
Does anybody have access to a Verilog-AMS tool and can said person
attempt to run the attached sample program? It is a very simple
program, but it is an attempt to test some of my understanding of
very basic principles of Verilog-AMS.
I understand
On Saturday 10 May 2008, Dan McMahill wrote:
I think you want to declare your signals that you have listed
as 'voltage' as 'electrical'. Thats assuming verilog-ams
doesn't do things differently from verilog-a which I'm more
familiar with.
voltage is ok ..
It is defined in disciplines.vams.
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