DJ Delorie wrote:
I can't think of a good reason to do this, but I suppose you could
connect to a bus pin (aka pin with multiple signals) and name the
*bus* while leaving the individual *nets* unnamed, and carry that bus
name on to a second schematic page, still without naming the nets, and
DJ Delorie wrote:
I published my paper mostly to get a discussion going on what busses
*mean* though, not the implementation details. For example, what does
it mean when three busses with different names are connected?
D[15:0] ==** D[15:0]
||
\\
DJ Delorie wrote:
One of the things we need for pin/gate swapping in pcb is a UUID for
each logical symbol in the schematic set. Refdes is not unique enough :-(
Yep. Maybe it could be handled without needing to see it all the time?
Since UUIDs are long... they could be a generated attribute
D[15:0],A[1:16] with a branch called A[1:16]
I was thinking the above renames the wires but perhaps that's a bad
idea. Yeah, I guess it would have to create a bundle of 32 wires.
No reason you couldn't attach some random attribute to the bus that's
just to give it a mnemonic name :-)
When I
DJ Delorie wrote:
JG wrote:
When I say modules, I'm thinking in verilog, where a port
corresponds to a pin, and a port can be multiwire. Or, you could
define pin as single wire and create a new thing called a port, that
has multiwire function.
I'm worried about pcb, though, where pin ==
Right, when we have a signal-pin-symbol relation, we have a bunch of
information:
* net name
* pin number
* pin sequence
* pin label
* physical pin location
If I have a bus A[1:3] connected to pin EN[0:2] at pin number 4,8,7 -
I mean the same as if I had connected net A1 to pin EN0 at 4, A2 to
DJ Delorie wrote:
Right, when we have a signal-pin-symbol relation, we have a bunch of
information:
* net name
* pin number
* pin sequence
* pin label
* physical pin location
If I have a bus A[1:3] connected to pin EN[0:2] at pin number 4,8,7 -
I mean the same as if I had connected net A1 to
So, in this example, pin label is EN[0:2], pin number list is (4,8,7),
netname is A[1:3].
Right.
bus pin confuses me. Is there another name for what you are thinking?
It's a symbolic pin that means multiple physical pins. It can look
the same or look different, doesn't matter to me, but I
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Am 15.08.2010 22:25, schrieb DJ Delorie:
D[15:0],A[1:16] with a branch called A[1:16]
I was thinking the above renames the wires but perhaps that's a bad
idea. Yeah, I guess it would have to create a bundle of 32 wires.
No reason you
in general I don't like having 2 names for the same net, Maybe I'm
biased with my experience of vhdl synthesis, normally the name that you
don't expect survives synthesis and the other one gets lost (and that
even may vary between two releases of the same tool). So having only one
name has
DJ Delorie wrote:
bus pin confuses me. Is there another name for what you are thinking?
It's a symbolic pin that means multiple physical pins. It can look
the same or look different, doesn't matter to me, but I figured a bus
pin would be thicker, and could connect directly to a bus, instead
Thanks. The chip design tools don't worry with making busses look
any different unless added by the user just for looks. For them,
the different label does it all. But they done' have that
additional constraint of a package.
Right, with verilog signal is more abstract - one signal can be
DJ Delorie wrote:
You can refer to the nets within the bus when you pull them out for
a connection:
A[0:15],D[0:7],RD,WR,EN - all the nets
A[0:1],RD,EN - some of the nets
A15,D[0:7],WR,EN - some of the nets
but we could also give the *grouping* a name, like
On Aug 15, 2010, at 4:15 PM, DJ Delorie wrote:
I called it bus pin meaning a pin that connects to a bus, vs a pin
that connects to a net, in gschem. I mean, we already have two
fundamental connection types in gschem - nets and busses. Why don't
we have two pin types that correspond?
But
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Am 16.08.2010 00:07, schrieb DJ Delorie:
in general I don't like having 2 names for the same net, Maybe I'm
biased with my experience of vhdl synthesis, normally the name that you
don't expect survives synthesis and the other one gets lost (and
But in Paul's approach, every connection is a bus.
To use your own words: But synthesis is not the only geda flow!
With physical electronics, individual electrical connections are
fundamental, and groupings are synthetic. They're totally distinct
concepts, unlike in synthesis.
I completely disagree.
Yes, I expected you to.
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