[gem5-dev] Changeset 10346:d96b61d843b2 breaking Android GB Image

Hi, I am trying to debug an issue booting the Android GB image. With the latest tip (or at least from a couple of days ago) gem5 isn't able to fully boot the benchmark. It gets to the commandline, but doesn't ever progress to the benchmark (see system.terminal output below) I've tracked down

[gem5-dev] changeset in gem5: config: add --root-device machine parameter

changeset 71c40e5c8bd4 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=71c40e5c8bd4 description: config: add --root-device machine parameter In case /dev/sda1 is not actually the boot partition for an image, we can override it on the command line or

[gem5-dev] changeset in gem5: mem: mmap the backing store with MAP_NORESERVE

changeset 417ba77dedb4 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=417ba77dedb4 description: mem: mmap the backing store with MAP_NORESERVE This patch ensures we can run simulations with very large simulated memories (at least 64 TB based on some

[gem5-dev] changeset in gem5: arch: Make readMiscRegNoEffect const throughout

changeset 829adc48e175 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=829adc48e175 description: arch: Make readMiscRegNoEffect const throughout Finally took the plunge and made this apply to all ISAs, not just ARM. diffstat: src/arch/alpha/isa.cc

[gem5-dev] changeset in gem5: cpu: add support for outputing a protobuf for...

changeset ef2c71a5f02e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ef2c71a5f02e description: cpu: add support for outputing a protobuf formatted CPU trace Doesn't support x86 due to static instruction representation. diffstat: src/cpu/InstPBTrace.py

[gem5-dev] changeset in gem5: arm: Merge ISA files with pseudo instructions

changeset b5e5068fcb26 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b5e5068fcb26 description: arm: Merge ISA files with pseudo instructions This changeset moves the pseudo instructions used to signal unknown instructions and unimplemented

[gem5-dev] changeset in gem5: mem: Use the range cache for lookup as well a...

changeset d0004c12d024 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d0004c12d024 description: mem: Use the range cache for lookup as well as access This patch changes the range cache used in the global physical memory to be an iterator so that we

[gem5-dev] changeset in gem5: config: Add memcheck stress test

changeset c6cb94a14fea in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=c6cb94a14fea description: config: Add memcheck stress test This is a rather unfortunate copy of the memtest.py example script, that actually stresses the system with true sharing

[gem5-dev] changeset in gem5: dev: Fix undefined behaviuor in i8254xGBe

changeset ac3236a0873b in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ac3236a0873b description: dev: Fix undefined behaviuor in i8254xGBe This patch fixes a rather unfortunate oversight where the annotation pointer was used even though it is null.