* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing passed.
*
changeset b32578b2af99 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b32578b2af99
description:
mem: Align all MSHR entries to block boundaries
This patch aligns all MSHR queue entries to block boundaries to
simplify checks for matches. Previously
changeset d524dc4f16ae in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d524dc4f16ae
description:
mem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHED
This patch subsumes the PREFETCH_SNOOP_SQUASH flag with the more
generic BLOCK_CACHED flag. Future
changeset b2071d0eb5f1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b2071d0eb5f1
description:
mem: Modernise MSHR iterators to C++11
This patch updates the iterators in the MSHR and MSHR queues to use
C++11 range-based for loops. It also does a bit
changeset 9a34e28cd2c2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9a34e28cd2c2
description:
mem: Ignore uncacheable MSHRs when finding matches
This patch changes how we search for matching MSHRs, ignoring any MSHR
that is allocated for an
changeset 993c2baa485a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=993c2baa485a
description:
mem: Remove redundant allocateUncachedReadBuffer in cache
This patch removes the no-longer-needed
allocateUncachedReadBuffer. Besides the checks it is
changeset 8a7285d6197e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8a7285d6197e
description:
arm, configs: Do not forward snoops from I cache
This fix simply tells the I cache to not forward snoops to the fetch
unit (since there is really no
changeset 9e521c0c3877 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9e521c0c3877
description:
mem: Cleanup flow for uncacheable accesses
This patch simplifies the code dealing with uncacheable timing
accesses, aiming to align it with the existing
changeset c48310de1a51 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c48310de1a51
description:
mem: Allocate cache writebacks before new MSHRs
This patch changes the order of writeback allocation such that any
writebacks resulting from a tag lookup
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Review request for Default.
Repository: gem5
Description
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Changeset
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Review request for Default.
Repository: gem5
Description
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Changeset
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Review request for Default.
Repository: gem5
Description
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_BIG_ENDIAN is
Hello,
can someone review this ?
http://reviews.gem5.org/r/2705/
This makes freebsd ATA stack happy, as it want different access-width for two
of registers
Ruslan
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Thanks!
Again, the summary should start with sim :
- Andreas Hansson
On March 27, 2015, 2:16 p.m., Andreas Hansson wrote:
Looks great. Thanks for the contribution.
A few minor things:
1) The summary should start with dev : (see
http://gem5.org/Commit_Access for details)
2) Are any regressions affected? (or is this not impacting linux)
this is
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Looks great. Thanks for the contribution.
A few minor things:
1) The
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Ship it!
Ship It!
- Ali Saidi
On March 27, 2015, 2 p.m., Ruslan
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Ship it!
Thanks for the change!
- Ali Saidi
On March 25, 2015, 11:10
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Looks much nicer. Thanks for the changes! Sorry for the long wait for
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(Updated March 27, 2015, 10:27 p.m.)
Review request for Default.
Repository:
On March 27, 2015, 6:28 p.m., Steve Reinhardt wrote:
ext/sst/tests/test6_arm_4c.py, line 93
http://reviews.gem5.org/r/2668/diff/5/?file=43877#file43877line93
so does this require you to edit the file to replace
/XXX/abs-path-to? couldn't this path be read from an environment
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