*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing:
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing:
FAILED!
*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic:
FAILED!
*
build/RISCV/tests/opt/
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/6821 )
Change subject: alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of
ISA_HAS_DELAY_SLOT.
..
alpha,arm,mips,power,riscv,sp
Hello Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/7163
to look at the new patch set (#2).
Change subject: mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token
protocol
..
Brandon Potter has submitted this change and it was merged. (
https://gem5-review.googlesource.com/7241 )
Change subject: style: change C/C++ source permissions to noexec
..
style: change C/C++ source permissions to noexec
Se
Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/7301
Change subject: dev: Fix wrong missing fallthrough
..
dev: Fix wrong missing fallthrough
The patch that added M5_FALLTHROUGH (
Hello,
In microldstop.hh, the class LdStop is the base class for load and store
ops. But can somebody please explain me how can the load and store be
differentiated from this class and also how can I directly print the output
of this class from base.cc.
Regards
Nidhi
Chen Zou has submitted this change and it was merged. (
https://gem5-review.googlesource.com/7021 )
Change subject: configs: Fill in the cpu.isa field in etrace_replay.py
since no default are provided now
..
configs: Fill i
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/7321
Change subject: arch-riscv: Don't crash when printing unknown CSRs
..
arch-riscv: Don't crash when printing unknown CSRs
This patch
Hanhwi Jang has uploaded a new patch set (#2). (
https://gem5-review.googlesource.com/7281 )
Change subject: cpu-o3: Fix signed overflow in PhysRegIndex
..
cpu-o3: Fix signed overflow in PhysRegIndex
PhysRegIndex is typed as
Hanhwi Jang has uploaded a new patch set (#3). (
https://gem5-review.googlesource.com/7281 )
Change subject: cpu-o3: Fix signed overflow in PhysRegIndex
..
cpu-o3: Fix signed overflow in PhysRegIndex
PhysRegIndex is typed as
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7344
Change subject: x86, mem: Pass the multi level page table layout in as a
parameter.
..
x86, mem: Pass the multi level page table l
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7351
Change subject: arch: Remove the "arch/tlb.hh" switching header.
..
arch: Remove the "arch/tlb.hh" switching header.
This header is
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7346
Change subject: x86, mem: Don't try to force physical addresses on the
system.
..
x86, mem: Don't try to force physical addresses
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7343
Change subject: arch, mem: Make the page table lookup function return a
pointer.
..
arch, mem: Make the page table lookup function
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7345
Change subject: x86, mem: Get rid of PageTableOps::getBasePtr.
..
x86, mem: Get rid of PageTableOps::getBasePtr.
Pass this constant
Hello Jason Lowe-Power, Alexandru Duțu, Andreas Sandberg, Brandon Potter,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/6981
to look at the new patch set (#3).
Change subject: arch,mem: Move page table construction into the arch
classes.
.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7348
Change subject: arm, power: Make the python TLB simobjects inherit from
BaseTLB.
..
arm, power: Make the python TLB simobjects inh
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7342
Change subject: arch, mem, sim: Consolidate and rename the SE mode page
table classes.
..
arch, mem, sim: Consolidate and rename t
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7341
Change subject: mem: Change the multilevel page table to inherit from
FuncPageTable.
..
mem: Change the multilevel page table to i
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7350
Change subject: arch, mem: Abstract the data stored in the SE page tables.
..
arch, mem: Abstract the data stored in the SE page tabl
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7349
Change subject: cpu: Make the CPU's TLB parameter a BaseTLB.
..
cpu: Make the CPU's TLB parameter a BaseTLB.
This is instead of the
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7347
Change subject: x86, mem: Rewrite the multilevel page table class.
..
x86, mem: Rewrite the multilevel page table class.
The new ver
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/6981 )
Change subject: arch,mem: Move page table construction into the arch
classes.
..
arch,mem: Move page table construction i
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/6982 )
Change subject: arch,mem: Remove the default value for page size.
..
arch,mem: Remove the default value for page size.
This
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