Also, I should point out that the systemc standard defines a set of
mechanisms and an interface, not an implementation. The Accellera version
of systemc is *not* the standard, it's just an implementation (a very
common and important one) of that standard. It's dangerous to conflate
those two ideas,
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/11015
Change subject: mem-cache: Selectively clear downstream pending
..
mem-cache: Selectively clear downstream pending
Until now,
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/11016
Change subject: mem-cache: Fix promoting of targets that need writable
..
mem-cache: Fix promoting of targets that need writabl
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/11018
Change subject: mem-cache: Promote deferred targets on cache clean responses
..
mem-cache: Promote deferred targets on cache cl
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/11017
Change subject: mem-cache: Promote targets that don't require writable
..
mem-cache: Promote targets that don't require writabl
Giacomo, if you're proposing linking in the systemc library and then adding
wrappers to somehow plug that into gem5's underlying mechanisms, I'm not
sure that's technically feasible since the existing implementation isn't
intended to be built on top of something else. Also a lot of the mechanisms
a
Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/10995
to review the following change.
Change subject: misc: Substitute pointer to Request with aliased RequestPtr
I'll have some time next week to dig into this.
Cheers,
Jason
On Fri, Jun 8, 2018, 7:13 AM Dr.-Ing. Matthias Jung
wrote:
> Hi Giacomo, Gabe,
>
> I'm a large supporter of SystemC because its 'the' IEEE standard for
> simulation, therefore I support always activities towards that direction.
> How
Hi Giacomo, Gabe,
I'm a large supporter of SystemC because its 'the' IEEE standard for
simulation, therefore I support always activities towards that direction.
However I have a similar concern like Giacomo.
I would prefer to just 'use' the SystemC kernel by accellera as kernel for gem5
in ord
Thanks Gabe, I will wait then 😉
From: gem5-dev on behalf of Gabe Black
Sent: 07 June 2018 22:45:14
To: gem5 Developer List
Subject: Re: [gem5-dev] setMiscReg signature change
Hi Giacomo. Some of the register accessor functions (maybe all of them?)
used to retur
Hi Gabe,
I have had a quick glance at the patches and there's one thing I don't
understand:
It seems to me that you are sort of reimplementing the SystemC runtime kernel
inside
gem5 for scratch.
Is there a reason for doing it? Can't we just link to the external SystemC
library
and just wr
Daniel Carvalho has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10722 )
Change subject: mem-cache: Use secure bit in findVictim
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mem-cache: Use secure bit in findVictim
Sector caches must
Daniel Carvalho has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10721 )
Change subject: mem-cache: Move tagsInUse to children
..
mem-cache: Move tagsInUse to children
Move tagsInUse to chil
Daniel Carvalho has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10723 )
Change subject: mem-cache: Change Cache block tag check
..
mem-cache: Change Cache block tag check
Change tag to addr
Daniel Carvalho has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10142 )
Change subject: mem-cache: Return evictions along with victims
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mem-cache: Return evictions along with victims
For
Daniel Carvalho has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10141 )
Change subject: mem-cache: Use ReplaceableEntry in findBlockBySetAndWay
..
mem-cache: Use ReplaceableEntry in findBloc
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10661 )
Change subject: sim: Rename the SimObject cxx_bases field to
cxx_extra_bases.
..
sim: Rename the SimObject cxx_bases fie
*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing:
FAILED!
*** stat_diff: SKIPPED*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED!
*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic:
FAILED!
*
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