Hi,
Without the text search it is not easy to know if someone already posted
the same or similar patch. So, I'm for it, but not sure if it can be that
useful.
Regards,
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
2016-11-21 17:34 GMT+01:00 Jason Lowe-Power :
> Hi all
nando,
>>>
>>> I have no idea, off the top of my head. I'd have to look into the code
>>> and/or the history of the file to figure it out.
>>>
>>> I'm busy with an ISCA submission right now, but I can find time to look
>>> into this in a w
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Ship it!
Ship It!
- Fernando Endo
On Nov. 18, 2016, 3:21 p.m
ry familiar with.
>
> Cheers,
> Jason
>
> On Fri, Nov 4, 2016 at 9:46 AM Fernando Endo
> wrote:
>
> Hello all,
>
> I'd like to know if the gem5 community would like to have a TAGE branch
> prediction in gem5.
> In my branch it seems to be working, so if
Hello all,
I'd like to know if the gem5 community would like to have a TAGE branch
prediction in gem5.
In my branch it seems to be working, so if you give me a positive feedback
I may spend some spare time to rebase and test the patch over mainstream.
More specifically, I took the CBP2016 winner
Totally agree! The prediction tables must not be speculatively updated.
Regards,
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
2016-10-27 16:53 GMT+02:00 Arthur Perais :
> High guys,
>
> We just noticed some interesting behavior in the branch prediction
> infrastructur
t;
>
>
>
> On 14/10/2016, 14:26, "gem5-dev on behalf of Fernando Endo" <
> gem5-dev-boun...@gem5.org on behalf of fernando.en...@gmail.com> wrote:
>
> >Hello all,
> >
> >I'd like to know if the following patch may interest the community.
>
changeset f1e198a028be in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f1e198a028be
description:
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
Modify the opClass assigned to AArch64 FP instructions from SimdFloat*
to
Float*. Al
evision 2' works
- Fernando
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On Oct. 5, 20
Hello all,
I'd like to know if the following patch may interest the community.
I split conditionally executed AArch64 instructions into two or three uops,
in order to use at most 3 register file ports, instead of 4 in the current
code. The vast majority if not all AArch64 uops use up to 3 RF port
---
Thanks,
Fernando Endo
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register index printing
Diffs
-
src/arch/arm/insts/static_inst.cc a64a035dfbe1
src/arch/arm/insts/vfp.cc a64a035dfbe1
Diff: http://reviews.gem5.org/r/3641/diff/
Testing
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Thanks,
Fernando Endo
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Hello,
Probably I can't technically help you here, but have you considered
observing the simulator behavior when similar faults happen? For example,
simulate a program that access an invalid address and enable all related
debug flags to track it (--debug-flags option).
Hope it helps,
--
Fernando
"st3 {V9.D, V10.D, V11.D}[0], [X29]"); // 2 FloatMemWrite
asm("st3 {V9.D, V10.D, V11.D}[1], [X29]"); // 2 FloatMemWrite
asm("st4 {V9.B, V10.B, V11.B, V12.B}[0], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.B, V10.B, V11.B, V12.B}[15], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.H, V10.H, V11.H, V12.H}[0], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.H, V10.H, V11.H, V12.H}[7], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.S, V10.S, V11.S, V12.S}[0], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.S, V10.S, V11.S, V12.S}[3], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.D, V10.D, V11.D, V12.D}[0], [X29]"); // 2 FloatMemWrite
asm("st4 {V9.D, V10.D, V11.D, V12.D}[1], [X29]"); // 2 FloatMemWrite
asm("st1 {V9.16B}, [X29], #16"); // 1 FloatMemWrite
asm("st1 {V9.8H, V10.8H}, [X29], #32"); // 2 FloatMemWrite
asm("st1 {V9.4S, V10.4S, V11.4S}, [X29], #48"); // 3 FloatMemWrite
asm("st1 {V9.2D, V10.2D, V11.2D, V12.2D}, [X29], #64"); // 4 FloatMemWrite
asm("st2 {V9.8H, V10.8H}, [X29], #32"); // 2 FloatMemWrite
asm("st3 {V9.4S, V10.4S, V11.4S}, [X29], #48"); // 3 FloatMemWrite
asm("st4 {V9.2D, V10.2D, V11.2D, V12.2D}, [X29], #64"); // 4 FloatMemWrite
Thanks,
Fernando Endo
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On July 16, 2016, 4:44 p.m., Fernando Endo wrote:
>
> ---
> This is
hem.
- Fernando
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On July 16, 2016, 4:44 p.m., Fernando Endo wrote:
>
>
ot;); // 2 FloatMemWrite
asm("st3 {V9.D, V10.D, V11.D}[1], [X29]"); // 2 FloatMemWrite
asm("st4 {V9.B, V10.B, V11.B, V12.B}[0], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.B, V10.B, V11.B, V12.B}[15], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.H, V10.H, V11.H, V12.H}[0], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.H, V10.H, V11.H, V12.H}[7], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.S, V10.S, V11.S, V12.S}[0], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.S, V10.S, V11.S, V12.S}[3], [X29]"); // 1 FloatMemWrite
asm("st4 {V9.D, V10.D, V11.D, V12.D}[0], [X29]"); // 2 FloatMemWrite
asm("st4 {V9.D, V10.D, V11.D, V12.D}[1], [X29]"); // 2 FloatMemWrite
asm("st1 {V9.16B}, [X29], #16"); // 1 FloatMemWrite
asm("st1 {V9.8H, V10.8H}, [X29], #32"); // 2 FloatMemWrite
asm("st1 {V9.4S, V10.4S, V11.4S}, [X29], #48"); // 3 FloatMemWrite
asm("st1 {V9.2D, V10.2D, V11.2D, V12.2D}, [X29], #64"); // 4 FloatMemWrite
asm("st2 {V9.8H, V10.8H}, [X29], #32"); // 2 FloatMemWrite
asm("st3 {V9.4S, V10.4S, V11.4S}, [X29], #48"); // 3 FloatMemWrite
asm("st4 {V9.2D, V10.2D, V11.2D, V12.2D}, [X29], #64"); // 4 FloatMemWrite
Thanks,
Fernando Endo
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V11.S}[0], [X29]"); // 1 FloatMemWrite
asm("st3 {V9.S, V10.S, V11.S}[3], [X29]"); // 1 FloatMemWrite
asm("st3 {V9.D, V10.D, V11.D}[0], [X29]"); // 2 FloatMemWrite
asm("st3 {V9.D, V10.D, V11.D}[1], [X29]"); // 2 FloatMemWrite
asm("st4
GB) with Atomic and SPEC simulation with O3
Thanks,
Fernando Endo
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read and write of some PMU registers
Diffs
-
src/arch/arm/pmu.cc fc247b9c42b6
Diff: http://reviews.gem5.org/r/3476/diff/
Testing
---
Boot the Atomic CPU and run a simple program that counts and prints the number
of retired instructions
Thanks,
Fernando Endo
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