[gem5-dev] changeset in gem5: sim: Call regStats of base-class as well

changeset 348411ec525a in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=348411ec525a description: sim: Call regStats of base-class as well We want to extend the stats of objects hierarchically and thus it is necessary to register the statistics of the

[gem5-dev] changeset in gem5: mem, config: Selective use of snoop filter

changeset 9345c4320477 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=9345c4320477 description: mem, config: Selective use of snoop filter Disable the default snoop filter in the SystemXBar so that the typical membus does not have a snoop filter by de

Re: [gem5-dev] Review Request 3373: mem: different HMC configuration

dd the arch descriptions inthe comments. src/mem/SerialLink.py (line 64) <http://reviews.gem5.org/r/3373/#comment7178> unit? src/mem/serial_link.hh (line 315) <http://reviews.gem5.org/r/3373/#comment7179> unit? src/mem/serial_link.cc (line 217) <http://reviews.gem5.org/r/3373/#c

Re: [gem5-dev] Review Request 3374: mem : tester for new HMC configuration

need adressing. - Stephan Diestelhorst On May 17, 2016, 10:11 p.m., Abdul Mutaal Ahmad wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem

Re: [gem5-dev] Review Request 3374: mem : tester for new HMC configuration

tp://reviews.gem5.org/r/3374/#comment7157> what happens if arch==0? - Stephan Diestelhorst On May 17, 2016, 10:11 p.m., Abdul Mutaal Ahmad wrote: > > --- > This is a

[gem5-dev] changeset in gem5: mem, cpu: Add assertions to snoop invalidatio...

changeset 6668387fa488 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=6668387fa488 description: mem, cpu: Add assertions to snoop invalidation logic This patch adds assertions that enforce that only invalidating snoops will ever reach into the logic t

Re: [gem5-dev] Review Request 3029: cpu: Add TraceCPU to playback elastic traces

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3029/#review7523 --- - Stephan Diestelhorst On Nov. 5, 2015, 9:08 p.m., Curtis Dunham wrote

Re: [gem5-dev] Review Request 3029: cpu: Add TraceCPU to playback elastic traces

> On Nov. 6, 2015, 7:43 a.m., Nilay Vaish wrote: > > src/cpu/trace/trace_cpu.cc, lines 1047-1048 > > > > > > I don't think this is correct. Radhika, maybe add a comment that nextExecute() will update currElement? - Steph

Re: [gem5-dev] Review Request 3029: cpu: Add TraceCPU to playback elastic traces

ing for failure needs extra handling.) - Stephan Diestelhorst On Nov. 5, 2015, 9:08 p.m., Curtis Dunham wrote: > > --- > This is an automatically generated e-mail. To reply, visit: &

[gem5-dev] Writes + IsInvalidate vs NeedsExclusive?

/ NeedsExclusive? It seems that these two express similar things and the different behaviour is only ever exposed in cases with different commands / different layers / call streams (snoops vs req / responses). Any comments? -- Thanks, Stephan Stephan Diestelhorst Staff Engineer ARM Research - Systems

Re: [gem5-dev] Review Request 2823: O3 CPU: Adding thread specific wakeup functionality

g here), so I think you should explicitly describe why this is reasonable to expect / not expect it here. - Stephan Diestelhorst On May 12, 2015, 8:33 p.m., Tony Gutierrez wrote: > > --- > This is an automatically generated

Re: [gem5-dev] Review Request 2821: mem: add request types for acquire and release

r? So only mark loads with acquire and stores with release, no? src/mem/request.hh (line 638) <http://reviews.gem5.org/r/2821/#comment5528> Boolean OR of the flags could be faster. I am also curious how these - Stephan Diestelhorst On May 26, 2015, 8:01 p.m., Ton

Re: [gem5-dev] Review Request 2788: cpu: Add store-access operations

> On May 14, 2015, 4:11 p.m., Stephan Diestelhorst wrote: > > Great idea, some comments on style and adding too many flags and specialisations. - Stephan --- This is an automatically generated e-mail. To reply, vi

Re: [gem5-dev] Review Request 2788: cpu: Add store-access operations

hh (line 704) <http://reviews.gem5.org/r/2788/#comment5405> The comment is confusing; the "hence" part. Why isn't the HardPFexReq marked as NeedsResponse, too (similar to HardPFReq)? src/mem/packet.cc (line 96) <http://reviews.gem5.org/r/2788/#comment5406>

[gem5-dev] changeset in gem5: mem: Create a request copy for deferred snoops

changeset fe0b1f40ea5a in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=fe0b1f40ea5a description: mem: Create a request copy for deferred snoops Sometimes, we need to defer an express snoop in an MSHR, but the original request might complete and deallo

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

em/cache/cache_impl.hh <http://reviews.gem5.org/r/2691/#comment5253> This should really be: if (!mshr.hasTargets()) and all the stuff below has too deep an (or two) indentation level, IMHO. I seriously consider goto an appropriate way to improve readability here. -

[gem5-dev] changeset in gem5: mem: Add option to force in-order insertion i...

changeset 886d2458e0d6 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=886d2458e0d6 description: mem: Add option to force in-order insertion in PacketQueue By default, the packet queue is ordered by the ticks of the to-be-sent packages. With the recent

[gem5-dev] changeset in gem5: cpu: Add a PC-value to the traffic generator ...

changeset 7f67a8d786a2 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=7f67a8d786a2 description: cpu: Add a PC-value to the traffic generator requests Have the traffic generator add its masterID as the PC address to the requests. That way, prefetchers

[gem5-dev] changeset in gem5: mem: Fix initial value problem with MemChecker

changeset 41413f830836 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=41413f830836 description: mem: Fix initial value problem with MemChecker In highly loaded cases, reads might actually overlap with writes to the initial memory state. The mem checke

Re: [gem5-dev] Review Request 2636: mem: fix prefetcher bug regarding write buffer hits

ther way, if we want to go with this patch, it should address this seemingly dead bit of logic, as well. My suggestion is to give this an additional day, and in the meantime test as Andreas has suggested. - Stephan Diestelhorst On F

Re: [gem5-dev] Review Request 2607: O3CPU: Idle CPU status logic revised

threading) should be generic enough to be pulled out, or at least be similar across the cores. - Stephan Diestelhorst On Jan. 21, 2015, midnight, Alexandru Dutu wrote: > > --- > This is an automatically generated e-mail. To rep

Re: [gem5-dev] ARM DVFS : all the cores are not online when performing ARM full system simulation to test DVFS

Lokesh, from your config.ini and config.pdf, I see that you are only initialising a *single* core. Can you please double check that you initialise the right number of cores in your configuration files and retry? -- Many thanks, Stephan Stephan Diestelhorst Staff Engineer ARM R&D Systems

[gem5-dev] changeset in gem5: cpu: Move packet deallocation to recvTimingRe...

changeset 3b405d11d6dc in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=3b405d11d6dc description: cpu: Move packet deallocation to recvTimingResp in the O3 CPU Move the packet deallocations in the O3 CPU so that the completeDataAccess deals only with t

Re: [gem5-dev] Review Request 2502: cpu, o3: Ignored invalidate causing same-address load reordering

> On Nov. 23, 2014, 11:56 a.m., Nilay Vaish wrote: > > src/cpu/o3/lsq_impl.hh, line 358 > > > > > > But are you not losing the fault set by completeAcc()? It would, indeed. What do you think is the problem here? I am not

Re: [gem5-dev] Review Request 2466: ruby: provide a second copy of the memory

suggested treatment of functional writes is fine. -- Sincerely, Stephan Stephan Diestelhorst Staff Engineer, ARM R&D Systems -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify t

Re: [gem5-dev] FS mode benchmark for ARM to evaluate DVFS

bout yes > /dev/null ? -- Sincerely, Stephan Stephan Diestelhorst Staff Engineer, ARM R&D Systems +44 (0)1223 405662 -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the s

[gem5-dev] Getting started with DVFS

, Stephan Stephan Diestelhorst Staff Engineer, ARM R&D Systems +44 (0)1223 405662 -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose

Re: [gem5-dev] Review Request 2404: ruby: network: garnet: remove functions for computing power

ke the equations whenever the underlying power state changes (because the state is part of the equation / selects the equation). For some power equations / IP blocks, this is on the order of per-cycle. -- Thanks, Stephan Stephan Diestelhorst Staff Engineer ARM R&D Systems +44 (0)1223 4

[gem5-dev] changeset in gem5: mem: Add access statistics for the snoop filter

changeset b3231fc8ae9d in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b3231fc8ae9d description: mem: Add access statistics for the snoop filter Adds a simple access counter for requests and snoops for the snoop filter and also classifies hits based o

[gem5-dev] changeset in gem5: mem: Add a simple snoop counter per bus

changeset 3ab6c2a5a407 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=3ab6c2a5a407 description: mem: Add a simple snoop counter per bus This patch adds a simple counter for both total messages and a histogram for the fan-out of snoop messages. The f

[gem5-dev] changeset in gem5: mem: Simple Snoop Filter

S BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILIT

[gem5-dev] changeset in gem5: misc: Add functions for doing popcount and po...

changeset 0655a3d869ad in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=0655a3d869ad description: misc: Add functions for doing popcount and power-of-two checking Adds two public domain algorithms for determining number of set bits and also whether a v

[gem5-dev] changeset in gem5: energy: Tighter checking of levels for DFS sy...

changeset d65768b9ffc2 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d65768b9ffc2 description: energy: Tighter checking of levels for DFS systems There are cases where users might by accident / intention specify less voltage operating points thatn f

[gem5-dev] changeset in gem5: energy: Small extentions and fixes for DVFS h...

changeset 77b9f96786c1 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=77b9f96786c1 description: energy: Small extentions and fixes for DVFS handler These additions allow easier interoperability with and querying from an additional controller which wil

[gem5-dev] changeset in gem5: energy: Add the Energy Controller in the righ...

changeset 3064e1beeb49 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=3064e1beeb49 description: energy: Add the Energy Controller in the right configs Tie in the newly created energy controller components in the default configurations. diffstat: sr

[gem5-dev] changeset in gem5: mem: Tie in the snoop filter in the coherent bus

changeset 33b4ea05c261 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=33b4ea05c261 description: mem: Tie in the snoop filter in the coherent bus diffstat: src/mem/Bus.py |1 + src/mem/coherent_bus.cc | 181 +++--

Re: [gem5-dev] Review Request 2332: cpu: Fix cached block load behavior in o3 cpu

> On Aug. 16, 2014, 4:01 p.m., Nilay Vaish wrote: > > Two points that I would like to make: > > * The opening comment in the patch states that it is trying to do two > > things. I would suggest that we split the patch. > > > > * I think we should not drop the original behaviour. Firstly, it wa

Re: [gem5-dev] Review Request 2320: sim: stopgap for race-conditions when using multiple EventQueues

Martin, Andreas, I would strongly suggest not penalising the single-thread common case if at all possible in both scenarios (ref counting and locking). I would suggest to reduce the clutter: have a proxy class that either uses the atomic / thread-safe mutexes / ref counters to the simplistic imp

Re: [gem5-dev] About changeset: 6bbb7ae309ac

#x27;t make it through the patch pushing round right now. Currently working on getting it out. -- Sincerely, Stephan Stephan Diestelhorst Staff Engineer, ARM R&D Systems +44 (0)1223 405662 -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be

[gem5-dev] changeset in gem5: power: Add basic DVFS support for gem5

- a/src/sim/ClockDomain.pyMon Jun 30 13:56:04 2014 -0400 +++ b/src/sim/ClockDomain.pyMon Jun 30 13:56:06 2014 -0400 @@ -1,4 +1,4 @@ -# Copyright (c) 2013 ARM Limited +# Copyright (c) 2013-2014 ARM Limited # All rights reserved. # # The license below extends only to copyright in the softw

[gem5-dev] changeset in gem5: stats: Method stats source

changeset 3ab094e72dad in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=3ab094e72dad description: stats: Method stats source This source for stats binds an object and a method / function from the object to a stats object. This allows pulling out stats

Re: [gem5-dev] Review Request 2241: stats: Method stats source

> On April 23, 2014, 5:01 p.m., Nathan Binkert wrote: > > This is cool, but it'd be better to just change FunctorProxy to be more > > generic. If FunctorProxy held a std::function (instead of the > > T*), then anything that took no arguments and returned a stats::Counter > > could be used. T

[gem5-dev] changeset in gem5: misc: Add panic_if / fatal_if / chatty_assert

changeset 9c37adf17edf in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=9c37adf17edf description: misc: Add panic_if / fatal_if / chatty_assert This snippet can be used to replace if + {panics, fatals, asserts} constructs. The idea is to have both the

[gem5-dev] changeset in gem5: arm: Fix uninitialised warning with gcc 4.8

changeset af1ec649e251 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=af1ec649e251 description: arm: Fix uninitialised warning with gcc 4.8 Small fix for a warning that prevents compilation with gcc 4.8.1 due to detecting that a variable might be unin

Re: [gem5-dev] Review Request 2164: misc: Add panic_if / fatal_if / chatty_assert

> On March 6, 2014, 4:48 p.m., Steve Reinhardt wrote: > > Too bad "assert_if" doesn't actually make sense, as it would be a nice > > parallel. Can't say I really like the name "chatty_assert", but I don't > > have a better alternative. I'll encourage others to suggest some though. > > If we

[gem5-dev] changeset in gem5: mem: Add "const" attribute to Packet getters

changeset 2f5eec8c1010 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=2f5eec8c1010 description: mem: Add "const" attribute to Packet getters Add a "const" keywords to the getters in the Packet class so these can be invoked on const Packet objects. d

[gem5-dev] changeset in gem5: mem: De-virtualise interfaces in the CoherentBus

changeset cd0a9c975c8c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=cd0a9c975c8c description: mem: De-virtualise interfaces in the CoherentBus The CoherentBus eventually got virtual methods for its interface. The "virtuality" of the CoherentBus, how