[m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-03-14 Thread Cron Daemon
* build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic FAILED! * build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing FAILED! * build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby passed. *

Re: [m5-dev] Ruby FS - DMA Controller problem?

2011-03-14 Thread Malek Musleh
Hi Brad, I found the problem that was causing this error. Specifically, it is this changeset: changeset: 7909:eee578ed2130 user:Joel Hestness hestn...@cs.utexas.edu date:Sun Feb 06 22:14:18 2011 -0800 summary: Ruby: Fix to return cache block size to CPU for split data

Re: [m5-dev] Ruby FS - DMA Controller problem?

2011-03-14 Thread Korey Sewell
Which lines are you commenting out to get it to work? It's a bit unclear in the diff you point to (maybe because you said it's a full set of changes, not just one) (btw: The work I've been doing is comparing the old m5 memory trace to the gem5 memory trace to try to chase down the bug. I

Re: [m5-dev] Ruby FS - DMA Controller problem?

2011-03-14 Thread Beckmann, Brad
Thanks Malek. Very interesting. Yes, this 5 line changeset seems rather benign, but actually has huge ramifications. With this change, the RubyPort passes the correct block size to the cpu/device models. Without it, I believe the block size defaults to 0 or 1...I can't remember which.

Re: [m5-dev] Ruby FS - DMA Controller problem?

2011-03-14 Thread Beckmann, Brad
Hi Malek, Just to reiterate, I don't think my patches will fix the underlining problem. Instead, my patches just fix various corner cases in the protocols. I suspect these corner cases are never actually reached in real execution. The fact that your dma traces point out that the Ruby and

Re: [m5-dev] Review Request: my initial implementation of cache flushing

2011-03-14 Thread Brad Beckmann
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/552/#review958 --- Hi Somayeh, I just have one larger issue to mention, then a few minor

[m5-dev] Review Request: isa: get rid of expandForMT function

2011-03-14 Thread Korey Sewell
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/578/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [m5-dev] Review Request: my initial implementation of cache flushing

2011-03-14 Thread Somayeh Sardashti
On 2011-03-14 15:54:41, Brad Beckmann wrote: Hi Somayeh, I just have one larger issue to mention, then a few minor comments. See below for details. The larger issue is that I believe one of the transitions you specify is unecessary (see specific comments below). In general, be very

Re: [m5-dev] Review Request: isa: get rid of expandForMT function

2011-03-14 Thread Korey Sewell
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/578/ --- (Updated 2011-03-14 17:34:17.189549) Review request for Default, Ali Saidi, Gabe

Re: [m5-dev] Review Request: isa: get rid of expandForMT function

2011-03-14 Thread Korey Sewell
Reviewboard is complaining about posting consecutive changesets to the board for some reason. When I view the diff it gives an error message about not being able to apply the patch. So for now, I just posted both patches merged and will split on commit. Anyone else run into this problem? On

[m5-dev] Review Request: sparc: compilation fixes for inorder

2011-03-14 Thread Korey Sewell
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/583/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [m5-dev] Review Request: sparc: compilation fixes for inorder

2011-03-14 Thread Korey Sewell
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/583/ --- (Updated 2011-03-14 17:39:33.764506) Review request for Default, Ali Saidi, Gabe