Re: [m5-dev] Review Request: Ruby: Add support for functional accesses

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/611/#review1082 --- This looks great, I just have a few minor suggestions below. It seems li

Re: [m5-dev] Review Request: Ruby: Add new object called WireBuffer to mimic a Wire.

Looks like Nilay is getting used to our style :) On Thu, Mar 31, 2011 at 2:19 PM, Nilay Vaish wrote: >This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/627/ > > src/mem/ruby/system/WireBuffer.hh

Re: [m5-dev] Review Request: Ruby: Add support for functional accesses

> On 2011-03-31 11:11:03, Brad Beckmann wrote: > > src/mem/ruby/system/RubyPort.cc, line 321 > > > > > > This loop is probably the most complicated and important part of this > > patch. It might be easiest if we move this

Re: [m5-dev] Review Request: X86: fnstsw: Another patch from Vince Weaver

It might be ok, but I've been busy and forgot to look at it. Please give me a few more days. Gabe Quoting Lisa Hsu : --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/594/#review1056 ---

Re: [m5-dev] Review Request: Ruby: Add support for functional accesses

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/611/ --- (Updated 2011-03-31 20:44:17.499794) Review request for Default. Summary ---

Re: [m5-dev] changeset in m5: CacheMemory: add allocateVoid() that is == allo...

Lisa, should not compiler yell in this case as well? Nilay On Thu, March 31, 2011 8:22 pm, Lisa Hsu wrote: > changeset c7302d55d644 in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=c7302d55d644 > description: > CacheMemory: add allocateVoid() that is == allocate() but n

[m5-dev] changeset in m5: CacheMemory: add allocateVoid() that is == allo...

changeset c7302d55d644 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=c7302d55d644 description: CacheMemory: add allocateVoid() that is == allocate() but no return value. This function duplicates the functionality of allocate() exactly, except that it does not

Re: [m5-dev] Review Request: CacheMemory: add allocateVoid() that is == allocate() but no return value.

> On 2011-03-31 16:15:29, Brad Beckmann wrote: > > This is more of a question, then a suggestion. Is there a way to use > > allocateVoid() a wrapper around allocate() rather than have to duplicate > > code? What happens if you cast the return pointer to void? Does that > > suppresss the err

Re: [m5-dev] Review Request: CacheMemory: add allocateVoid() that is == allocate() but no return value.

> On 2011-03-31 16:15:29, Brad Beckmann wrote: > > This is more of a question, then a suggestion. Is there a way to use > > allocateVoid() a wrapper around allocate() rather than have to duplicate > > code? What happens if you cast the return pointer to void? Does that > > suppresss the err

[m5-dev] ruby_mem_tester.py

Hi all, As I prepared to push a bunch of stuff today I found that the following command line fails at the head of the the clean tree: ALPHA_SE_MOESI_hammer/m5.debug configs/example/ruby_mem_test.py -l 1000 --num-dma 2 I pushed my changes anyway because they didn't make any difference on this err

[m5-dev] changeset in m5: Ruby: Add new object called WireBuffer to mimic...

changeset 777459f7c61f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=777459f7c61f description: Ruby: Add new object called WireBuffer to mimic a Wire. This is a substitute for MessageBuffers between controllers where you don't want messages to actually

[m5-dev] changeset in m5: Ruby: Simplify SLICC and Entry/TBE handling.

changeset be38f7b6ad9e in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=be38f7b6ad9e description: Ruby: Simplify SLICC and Entry/TBE handling. Before this changeset, all local variables of type Entry and TBE were considered to be pointers, but an immediate

[m5-dev] changeset in m5: Ruby: have the rubytester pass contextId to Ruby.

changeset 8c68155aac00 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=8c68155aac00 description: Ruby: have the rubytester pass contextId to Ruby. diffstat: src/cpu/testers/rubytest/Check.cc | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diffs (27 lines):

[m5-dev] changeset in m5: Ruby: enable multiple sequencers in one control...

changeset d5ad24eb015f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=d5ad24eb015f description: Ruby: enable multiple sequencers in one controller. diffstat: src/mem/slicc/symbols/StateMachine.py | 21 + 1 files changed, 13 insertions(+), 8 deleti

[m5-dev] changeset in m5: Ruby: pass Packet->Req->contextId() to Ruby.

changeset 20dbef14192d in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=20dbef14192d description: Ruby: pass Packet->Req->contextId() to Ruby. It is useful for Ruby to understand from whence request packets came. This has all request packets going into Ruby

Re: [m5-dev] Review Request: Ruby: Add support for functional accesses

> On 2011-03-31 11:11:03, Brad Beckmann wrote: > > src/mem/ruby/system/RubyPort.cc, line 321 > > > > > > This loop is probably the most complicated and important part of this > > patch. It might be easiest if we move this

Re: [m5-dev] Review Request: CacheMemory: add allocateVoid() that is == allocate() but no return value.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/629/#review1077 --- This is more of a question, then a suggestion. Is there a way to use al

Re: [m5-dev] Review Request: Ruby: Add new object called WireBuffer to mimic a Wire.

> On 2011-03-31 14:19:44, Nilay Vaish wrote: > > src/mem/ruby/system/WireBuffer.py, line 31 > > > > > > Do we need this commented piece of code? Thanks for catching these. I thought I cleaned up that stuff, but I obviously

Re: [m5-dev] Review Request: Ruby: enable multiple sequencers in one controller.

> On 2011-03-31 15:58:14, Brad Beckmann wrote: > > src/mem/slicc/symbols/StateMachine.py, line 477 > > > > > > Do you also need to declare the contains_dma_sequencer flag here and > > set it to False? Brad, great catch - s

Re: [m5-dev] Review Request: Ruby: Simplify SLICC and Entry/TBE handling.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/630/#review1074 --- Ship it! - Brad On 2011-03-31 14:26:33, Lisa Hsu wrote: > > -

Re: [m5-dev] Review Request: Ruby: enable multiple sequencers in one controller.

> On 2011-03-31 14:22:16, Nilay Vaish wrote: > > I hope you have tested the existing protocols with these changes. > > Lisa Hsu wrote: > Yes - MOESI_[CMP_[directory|token]|hammer] all compile and run -l 1000 -n > 4 on the Ruby Tester. Since no logic has changed (for all my Ruby changes),

Re: [m5-dev] Review Request: Ruby: Add new object called WireBuffer to mimic a Wire.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/627/#review1072 --- Ship it! Other than Nilay's comments, this looks good to me. - Brad O

Re: [m5-dev] Review Request: Ruby: Add support for functional accesses

> On 2011-03-31 11:11:03, Brad Beckmann wrote: > > src/mem/ruby/system/RubyPort.cc, line 321 > > > > > > This loop is probably the most complicated and important part of this > > patch. It might be easiest if we move this

Re: [m5-dev] Review Request: Ruby: have the rubytester pass contextId to Ruby.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/625/#review1070 --- Ship it! - Brad On 2011-03-31 12:20:59, Lisa Hsu wrote: > > -

Re: [m5-dev] Review Request: Ruby: enable multiple sequencers in one controller.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/624/#review1069 --- src/mem/slicc/symbols/StateMachine.py

Re: [m5-dev] Review Request: Ruby: pass Packet->Req->contextId() to Ruby.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/623/#review1068 --- Ship it! - Brad On 2011-03-31 12:16:27, Lisa Hsu wrote: > > -

Re: [m5-dev] Review Request: Ruby: enable multiple sequencers in one controller.

> On 2011-03-31 14:22:16, Nilay Vaish wrote: > > I hope you have tested the existing protocols with these changes. Yes - MOESI_[CMP_[directory|token]|hammer] all compile and run -l 1000 -n 4 on the Ruby Tester. Since no logic has changed (for all my Ruby changes), I believe it's sufficient te

Re: [m5-dev] Review Request: Ruby: Simplify SLICC and Entry/TBE handling.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/630/#review1066 --- Ship it! Lisa, the changes look fine to me. Just make sure that all the

Re: [m5-dev] Review Request: Ruby: Simplify SLICC and Entry/TBE handling.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/630/ --- (Updated 2011-03-31 14:26:33.755740) Review request for Default, Ali Saidi, Gabe Bl

[m5-dev] Review Request: Ruby: Simplify SLICC and Entry/TBE handling.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/630/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

Re: [m5-dev] Review Request: Ruby: enable multiple sequencers in one controller.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/624/#review1065 --- Ship it! I hope you have tested the existing protocols with these change

Re: [m5-dev] Review Request: Ruby: have the rubytester pass contextId to Ruby.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/625/#review1064 --- Ship it! - Nilay On 2011-03-31 12:20:59, Lisa Hsu wrote: > >

Re: [m5-dev] Review Request: Ruby: Add new object called WireBuffer to mimic a Wire.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/627/#review1063 --- src/mem/ruby/system/WireBuffer.hh

Re: [m5-dev] Review Request: CacheMemory: add allocateVoid() that is == allocate() but no return value.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/629/#review1062 --- Ship it! - Nilay On 2011-03-31 12:21:22, Lisa Hsu wrote: > >

Re: [m5-dev] Review Request: Ruby: Simplify SLICC and Entry/TBE handling.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/628/ --- (Updated 2011-03-31 14:13:38.794443) Review request for Default, Ali Saidi, Gabe Bl

Re: [m5-dev] Review Request: Ruby: pass Packet->Req->contextId() to Ruby.

> On 2011-03-31 12:27:47, Nilay Vaish wrote: > > Is context Id being used any where? Not in any of the stock-provided protocols, but in some of our internal protocols, yes. This would also enable anyone to do context-based cache management, if they so desired, though it's not in the tree at a

[m5-dev] changeset in m5: Ruby: Bug in SLICC forgot semicolon at end of c...

changeset 99428f716e7b in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=99428f716e7b description: Ruby: Bug in SLICC forgot semicolon at end of code. diffstat: src/mem/slicc/symbols/StateMachine.py | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diffs (12 lin

Re: [m5-dev] Running Ruby w/32 Cores

Is there an attached patch I should be running or did it get bounced by m5-dev? If so, can you send it directly to me rather through m5-dev? On Wed, Mar 30, 2011 at 8:26 PM, Beckmann, Brad wrote: > Hi Korey, > > For the first trace, it looks like the L2 cache is either miscounting the > number o

Re: [m5-dev] Running Ruby w/32 Cores

Hi Lisa, I actually had sent the attachments to Brad since m5dev bounced the attachments. I think the limit is 512kB or something like that. But definitely, thanks for the heads up! On Wed, Mar 30, 2011 at 7:45 PM, Lisa Hsu wrote: > I think you forgot the attachments  :P. > Sometimes, if Protoco

Re: [m5-dev] Review Request: Ruby: pass Packet->Req->contextId() to Ruby.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/623/#review1060 --- Ship it! Is context Id being used any where? - Nilay On 2011-03-31 12

[m5-dev] Review Request: CacheMemory: add allocateVoid() that is == allocate() but no return value.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/629/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

[m5-dev] Review Request: Ruby: Simplify SLICC and Entry/TBE handling.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/628/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

[m5-dev] Review Request: Ruby: Add new object called WireBuffer to mimic a Wire.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/627/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

[m5-dev] Review Request: Ruby: have the rubytester pass contextId to Ruby.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/625/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

[m5-dev] Review Request: Ruby: enable multiple sequencers in one controller.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/624/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

[m5-dev] Review Request: Ruby: pass Packet->Req->contextId() to Ruby.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/623/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

Re: [m5-dev] Review Request: Ruby: Add support for functional accesses

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/611/#review1054 --- Hi Nilay, First, thanks for your patience. Sorry I wasn't able to provi

[m5-dev] Ruby: Protocol.hh

I am wondering what's the need of the file Protocol.hh, I removed it from different in the protocol independent part of Ruby. I also removed the file standard_1level_CMP-protocol.sm from the MOESI_hammer.slicc. Everything compiles perfectly. I am not sure what the requirement is. -- Nilay

Re: [m5-dev] Review Request: X86 ioctl: Another patch from Vince Weaver

> On 2011-03-18 13:57:35, Gabe Black wrote: > > src/sim/syscall_emul.hh, line 503 > > > > > > Why is this change necessary? I'm not 100% sure why it was the way it > > was before, but I see no reason to change it either. Ch

Re: [m5-dev] Review Request: X86: rlimit: Another patch from Vince Weaver

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/591/#review1059 --- Since there have been no objections, I'm going to commit this. - Lisa

Re: [m5-dev] Review Request: X86: haddps: Another patch from Vince Weaver

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/592/#review1058 --- Since there have been no objections, I'm going to commit this. - Lisa

Re: [m5-dev] Review Request: X86: fsincos: Another patch from Vince Weaver

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/593/#review1057 --- Since there have been no objections, I'm going to commit this. - Lisa

Re: [m5-dev] Review Request: X86: fnstsw: Another patch from Vince Weaver

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/594/#review1056 --- Since there have been no objections, I'm going to commit this. - Lisa

Re: [m5-dev] Review Request: patch from Vince Weaver for review

> On 2011-03-18 13:54:12, Gabe Black wrote: > > It seems like we should be able to emulate the access system call fairly > > easily. It basically just checks if a file can be accessed in certain ways, > > I think. We could do that on the real file descriptor, rearrange the result > > if necess

[m5-dev] trace compression

I just realized today that m5 can automatically compress the trace output generated by traceflags. Since I didn't realize this worked I've added to the documentation, but I thought I would also share it with the list: Trace file can become rather large quickly, but they do compress very well

Re: [m5-dev] Review Request: ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.

Everyone, this change alters the way that the O3 cpu switches registers from the atomic cpu. If you use checkpoint/switchover and m5 please test this (specifically the change to src/cpu/o3/thread_context_impl.hh) Thanks, Ali On Mar 30, 2011, at 4:55 PM, Ali Saidi wrote: > >

[m5-dev] Cron /z/m5/regression/do-regression quick

* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux