54:
>> system.cpu[i].workload = process
>> should set cpu[i] as the parent of the process object if the process
>> object doesn't already have a parent.
>>
>> Maybe what we really need to do is print a notification in
>> adoptOrphanParams() when a pare
Hi all,
I came across some indeterminism that causes problems. Yesterday I had a bug
that workload pagetables would not unserialize if I added an l2 cache, but
would if I had only a L1 cache. The culprit appears to be
src/python/m5/simulate.py, the portion that looks for oprhans to add to
objects
calling dup()
> again, which seems more correct.
>
> Steve
>
> On Thu, Jan 20, 2011 at 11:41 AM, Richard Strong wrote:
>
>> Hi all,
>>
>> I uncovered 3 bugs when trying to resume in ALPHA_SE from a checkpoint for
>> the spec2006 benchmarks. They are:
&g
Hi all,
I uncovered 3 bugs when trying to resume in ALPHA_SE from a checkpoint for
the spec2006 benchmarks. They are:
(1) Unserializing curTick failed because the checkpoint file wrote
curTick()=, but the unserializing code was expecting curTick=
(2) The mode bit was not being stored in the file
Hi all,
I checked out the unstable M5 last Thursday and saw a gcc-4.5.2 warning that
is being treated as an error:
scons: Building targets ...
[ CXX] ALPHA_SE/cpu/inorder/resource_pool.cc -> .do
cc1plus: warnings being treated as errors
/home/rstrong/build/m5-idle/build/ALPHA_SE/cpu/inorder/
changeset 3d417492668d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3d417492668d
description:
This fix addresses an ill formed if statement that fails
to compile. The fix was the simple addition of another set
of parenthesis to ensure the correct condit
changeset 17c0c17726ff in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=17c0c17726ff
description:
Changed BaseCPU::ProfileEvent's interval member to be of type Tick.
This was done to be consistent with its
python type of a latency. In addition, the multiple defin
The latency is set to "warn: interval=18294713441". This is for the
apache quadcore benchmark.
-Rick
nathan binkert wrote:
> What was the latency set at? I believe that it was a problem and the
> change should be committed, I'd just like to understand it.
>
> Nate
>
>
>> That was the cause
Hi,
I believe in src/cpu/base.hh::121, class ProfileEvent : public Event that:
int interval;
should be:
Tick interval;
src/cpu/base.hh::128
ProfileEvent(BaseCPU *cpu, int interval);
should be:
ProfileEvent(BaseCPU *cpu, Tick interval);
and also in src/cpu/base.cc:360,
BaseCPU::ProfileEvent:
Hi,
Great work. I noticed you added support for multithreading for simple
CPUs. I wouldn't mind figuring
out checkpoints with the multithreaded simple CPUs as it would free me
from EIO trace madness. Let
me know when the patches are in m5.
-Rick
jiayuan meng wrote:
> Thanks!
> Yeah, I used m
Hi,
Any foreseeable reason why a simple looping getpid call might fail on
the refCountingPtr declaration in detail cpu simulation on full system
alpha. Since that is a bit open ended, I am mostly wondering how would
this object constructor get called so I can trace backwards as my stack
trace
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