For the "classic" (non-Ruby) m5 memory system, the coherence protocol
is pretty tightly integrated with the cache model. I don't know that
you can just "disable" it.
You certainly can set different block sizes on different caches (as I
think you already tried)... if you really want to pursue this
Hi m5-dev list,
My understanding of the cache subsystem in M5 is that all caches (L1s in
all cores and L2 in a CMP system) must have the same line size. I
understand that it is more efficient, especially for the coherence
protocol. However, I think it is reasonable for different caches to have
