Dear Ferran,
Thank you so much for all your insights.
I managed to re-compile the benchmark after chroot to the image.
I also solved the external libraries issues and managed to run it on both Gem5
original and the other version of Gem5.
Thanks so much!
Regards,
Elena
-Original Message---
Hi Elena,
Glad to hear that! :) You're welcome!
Cheers,
Ferran O.
On 08/02/17 12:18, Woo L.L. wrote:
Dear Ferran,
Thank you so much for all your insights.
I managed to re-compile the benchmark after chroot to the image.
I also solved the external libraries issues and managed to run it on both
Dear all,
When we experience a cache miss at last level cache, we should send a
request to main memory and ask for the missed block. I was wondering if you
could help me find a file or function that does send requests to main
memory (and receive responses from that.)
Thank you.
Reza
Hi Reza,
This is handled by the port interface between the cache and the main
memory. For instance, at the DRAM controller, every request calls
recvTimingReq(). You may learn something from this chapter of my book:
http://learning.gem5.org/book/part2/memoryobject.html. The caches and the
memory co
Hi Jason,
Thank you for your response and reference to your book. I will read that.
I'm using NVmain as memory type. In this case, should I look into gem5
source files or NVmain source files? I'm looking for a file/function that
checks if the access to last level cache is a miss, then sends the re
Hello All,
I am using gem5 to perform some research on ARM/NEON performance. In particular
I'm looking into instruction timing and studying the ARM Cortex-A9 ( armv7 with
NEON).
Can you help me to clarify the following questions?
1.- ARM's documentation (Cortex™-A9 NEON™ Media ProcessingEngi
Hi all
When I run a simulation using the standard se.py, why aren't the supplied
arguments to script overwritten?
For example
build/X86/gem5.opt configs/example/se.py --cpu-clock="2GHz" -c ../MM1.x86 -o
"32"
When I check stats.txt, I see this
system.clk_domain.clock
Hi Ayman,
You may need to change the system clock with "--sys-clock". Its default
value is 1GHz.
sys-clock defines "Top-level clock for blocks running at system speed" and
cpu-clock defines "Clock for blocks running at CPU speed".
Majid
On Wed, Feb 8, 2017 at 9:47 AM, Moussa, Ayman wrote:
> Hi
Hi everyone
Could someone please tell me what parameters represent information about the
cache? i.e l1,l2,l3 I and D cache sizes, associativity , access time etc. Is
there any information about memory access time too? I searched the stats.txt
and config.ini but I could not find it anything abo
Hello,
You can find the information on caches in m5out/config.ini under
[system.cpu0.dcache], [system.cpu0.icache] etc. (search for "type=cache").
You may want to see src/mem/cache/Cache.py for Cache SimObject declaration,
configs/common/Caches.py for base implementations of the caches (latency,
Hi everyone,
Is there any tutorial on how to use KVM with gem5, especially for X86?
I'm asking because I need to perform a lot of gem5 full system simulation runs
with detailed cpu-type and with NVMainMemory as a memory controller. Using a
regular non-KVM gem5 image, only 10M instructions wit
I think you can find these information in the config.ini.
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"Moussa, Ayman" 编写:
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Hi All,
I was trying to add "page policy" as an option in hmctest.py file for
simulation purpose. I added following code:
parser.add_option("--page_policy", type = "int", default = 2,
help = "0:open; 1:open_adaptive; 2: close;
3:close_adaptive")
How would I verify if it worked o
Hi Reza,
Memory controllers (including NVMain) are behind a slave port and are generally
not aware of what the cache is doing – In other words, you want to look in the
gem5 source if you want to do something special for LLC misses. This will be
different for Ruby and classic caches:
If you ar
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