Hi all,
I am trying to build a hierarchy of caches and tester CPUs using memtest
(configs/examples/memtest.py) as my reference. I am able to connect regular
XBars and caches normally, but I want an *N*-ported connection between a
cache and a XBar (i.e. *N* simultaneous requests should be able to g
Hi All,
I was trying to run Full System Simulation using following command:
build/X86/gem5.opt configs/example/fs.py --mem-type=HMC_2500_x32 --caches
--l2cache
but getting the following error:
REAL SIMULATION
info: Entering event queue @ 0. Starting simulation...
warn: Don't know wha
Hi,
here is the debug simulation
command line: ./build/ARM/gem5.debug --debug-flags=Exec,ExecTicks
configs/example/fs.py --maxinsts=10 --machine-type=VExpress_GEM5_V1
--kernel /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image
/home/khilji/gem5/m5/system/disks/linux-aarch32-ael.img
Hi Shail,
It looks like gem5 isn't freeing the guest physical memory of the old
threads in SE mode. I'm not surprised there's a bug here. I haven't heard
of anyone testing this!
You could take a look at the code for pthread_join both in m5threads and in
gem5 (somewhere in sim/, probably). If you
Hi Ali,
You can ignore this warning at the beginning of simulation. The warning is
pretty self-explanatory. After adding some power modeling information to
gem5, there is a warning if you change power states more than once at the
same moment (which is physically impossible). But since this is at t
Hi Jason, thanks for replying. Actually, I am using SE mode and currently
relying on printings from the benchmarks themselves (these are SPEC2006
benchmarks). I expect that due to different implementation of syscalls,
some executed portion can be different, but even the printings from
benchmarks fo
Hi Sharjeel,
gem5 is likely not booting at all. I would start using debug flags to track
gem5's process. I'm not very familiar with ARM, so I'm not sure what the
best flags are to use.
Jason
On Mon, Feb 13, 2017 at 11:07 AM SHARJEEL KHILJI <
sharjeelsaeedkhi...@gmail.com> wrote:
> Hi,
>
> You m
Hi,
You mean in system.terminal file in m5.out. There is nothing in it ..blank.
I have also tried with linux-aarch32-ael.img but the result is the same.
Any suggestions plz ?
best regards,
sharjeel
On 13 February 2017 at 22:02, Jason Lowe-Power wrote:
> Is there anything in m5out/*terminal*? I
Hi,
Another difference between ARM and x86 is the OS that you're using. Maybe
the different paths are actually different paths through the OS (or
interrupts, etc.) and not different paths through your binaries. Even in SE
mode there may be different code paths based on how the syscalls are
impleme
Is there anything in m5out/*terminal*? I would bet that something is going
wrong early in the boot process and gem5 is not booting the OS correctly.
Jason
On Mon, Feb 13, 2017 at 10:51 AM SHARJEEL KHILJI <
sharjeelsaeedkhi...@gmail.com> wrote:
> Hi
>
> I am finally able to run the ARM+ RUBY full
Hi
I am finally able to run the ARM+ RUBY full system. But there is a problem
the m5 terminal is attached with the simulation but nothing appears in the
terminal.
./build/ARM/gem5.fast configs/example/fs.py --l2cache --cacheline_size=64
--l1d_size=32kB --l1i_size=32kB --l2_size=1MB
--machine-type
Dear all,
I ran a full system simulation with four cores CPU, in which each core is
hardcoded (using taskset command) to run a specific SPEC CPU2006 benchmarks
(leslie3d, leslie3d, mcf, and mcf). The architecture of the simulated system
can be inferred from the simulation command below:
build/
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