[gem5-users] Re: How to extract instruction traces

2021-09-20 Thread Francisco Carlos via gem5-users
Hello Scoot. When I want something specif that a debug-flag does not cover, I usually implement my own debug-flag printing only the information that I need. I would suggest checking if you can use an existing debug-flag to do the instruction trace (In O3CPU model I know that there are debug-fla

[gem5-users] Re: first gem5 build

2021-09-05 Thread Francisco Carlos via gem5-users
I think You didn't install libpng package. Try to run in your docker container: sudo apt-get install libpng-dev Best regards. -- Francisco Carlos Silva Jun

[gem5-users] Re: difference between DerivO3CPU and O3_ARM_v7a

2021-01-05 Thread Francisco Carlos via gem5-users
Hi Choe, The O3_ARM_v7a is a DerivO3CPU but using the parameters based on an Arm architecture (Arm Cortex A15). In other words, the O3_ARM_v7a is a specific configuration for a DerivO3CPU CPU model. Best regards.

[gem5-users] memory instructions detected as branch: O3CPU SE MODE

2020-12-14 Thread Francisco Carlos via gem5-users
Hello everyone, I detected an unexpected behavior in the fetch stage of O3CPU. Every time a memory instruction is fetched, it is detected as a branch, as we can see below. FullO3CPU: Ticking main, FullO3CPU. 203000: system.cpu.fetch: Running stage. 203000: system.cpu.fetch: Attempting to fe

[gem5-users] TLB in SE simulation

2020-12-11 Thread Francisco Carlos via gem5-users
Hello everyone, I am using gem5 SE mode and investigating memory operation latencies and how virtual memory can affect them in a superscalar processor (DerivO3CPU). Does the SE mode consider TLB delays, TLB hit and miss, for instance, or this is implemented only in FullSystem mode? I saw in th

[gem5-users] Re: Questions about CPU resource

2020-10-29 Thread Francisco Carlos via gem5-users
To the best of my knowledge, the ROB is shared, the rename table is separated for each thread and the LSQ is also shared in SMT. I am not sure about it, but I deduced this information from cpu code for O3CPU Model. I believe Jason or other more experienced user/developer can correct me if I am w

[gem5-users] Re: How to get program specific traces only?

2020-09-07 Thread Francisco Carlos via gem5-users
Hi Ahmed, I don't know what you mean by program specific traces. To get customized output from a debug-flag, I would suggest you create your own debug-flag and printing the information that you want. (http://learning.gem5.org/book/part2/debugging.html#:~:text=gem5%20provides%20support%20for%20

[gem5-users] Re: RISCV compiling error

2020-07-28 Thread Francisco Carlos via gem5-users
Hello, I used this link (https://github.com/riscv/riscv-gnu-toolchain) for install the RISC cross-compiler and worked for me. Best regards! [https://avatars0.githubusercontent.com/u/10872782?s=400&v=4] GitHub - riscv/riscv-gnu-toolchain: GNU toolcha

[gem5-users] Re: Memory -Address -Gem5-O3

2020-07-13 Thread Francisco Carlos via gem5-users
hello Abd, You can see a similar output by enabling the Exec debug-flag. I would suggest you look at the gem5 documentation to further details in the debug-flags available and how to use them. (http://learning.gem5.org/book/part2/debugging.html#:~:text=gem5%20provides%20support%20for%20printf,e

[gem5-users] Re: Adding new source files

2020-05-07 Thread Francisco Carlos via gem5-users
Did you create myFile.cc? myFile.cc should be in the same directory of the Sconscript that you added because you used the path 'myFile.cc' to the file. I hope this helps. -