[gem5-users] Re: Packet::MemCmd Class

Hi Samuel, If you're using the classic memory system, the easiest option is to add a tiny cache between the SimObject that issues the writes and the rest of the memory system. Then your SimObject can issue simple WriteReqs and the cache will take care of the rest. Otherwise, you will have to

[gem5-users] Re: CleanEvict packets in gem5

Hi Aritra, CleanEvict packets are generated by caches which have the parameter writeback_clean set to false whenever there is an eviction of a clean block. This is primarily to inform the snoop filter that a cache has a evicted a block. Hope this helps, Nikos On 02/03/2021 12:24,

[gem5-users] Re: Bypassing the last level cache in the response path

checked this by varying only the response latency of L3, while keeping other latency values the same. Any comment on this? From this observation, I concluded that the response latency is the latency a miss-fill incur at L3. Thanks and regards, Aritra On Wed, 9 Sep, 2020, 9:40 PM Nikos Nikoleris

[gem5-users] Re: Bypassing the last level cache in the response path

Hi, The response_latency doesn't necessarily correspond to the time it takes to fill in with the data from the response, but rather the time it takes for a cache to respond to a request from the point it has the data. In some cache designs, this will include the time to fill in but in other

[gem5-users] Re: Few questions about cache inclusiveness

Hi Saideepak, In the classic memory system when you configure the cache to be mostly inclusive, you always allocate on fetches and writebacks. There are a few cases where mostly-inclusive deviates from strictly-inclusive and iirc the most common one should be when a cache (e.g., LLC) evicts a

[gem5-users] Re: [ARM system] Question about the cleassic cache system

Assymetric cache hierachies should work in the classic memory system. The problem you run into is data corruption (the reported addresses are most likely invalid) but it's hard to say anything about the cause of it without more info. One quick way to test your assymetric memory hierarchy would

[gem5-users] Re: compute power and performance

gem5 doesn't provide a power model for the whole system out of the box. However, it provides the infrastructure for you to hook your own power model. You will find some very high level information here: https://www.gem5.org/documentation/general_docs/thermal_model and here:

[gem5-users] Re: How to find the virtual addresses of write requests accepted by the memory controller?

Hi May, Packets classified as writes in the memory controller are due to writebacks from the last-level cache. Writeback packets will have a physical address but will not have a valid virtual address. Mapping a physical address to a virtual address in the general case is not straightforward. In

[gem5-users] Re: Panic condition when reading a file in blocks of fixed size and processing

Hi, The simplest way to fix this, is to make sure that there is a CoherentXBar just above the memory controller (you probably have one already) and its parameter point_of_coherency is set to True. That way, all packets that are necessary for the coherency protocol are handled by that

Re: [gem5-users] Computing stat of type Value

Hi Victor, Alternatively, you can also register an exit callback that will calculate the stat. Have a look at how we use registerExitCallback(). One simple example is in the BaseTags class (src/mem/cache/tags/base.{hh,cc}). Nikos On 12/02/2020 18:43, Jason Lowe-Power wrote: Hi Victor, I have

Re: [gem5-users] 回复： 回复： ask for help about simulate with noncherentcahe

Hi all, The panic condition indicates that the noncoherent cache is receiving snoop requests. As it is noncoherent, the cache can't handle snoops and therefore gem5 crashes. For the noncoherent cache to work correctly, it has to be placed below the Point of Coherence, that is a coherent_xbar

Re: [gem5-users] Virtual/physical tagging/indexing

Hi Kevin, Caches in the classic model are physically indexed and physically tagged. Nikos On 11/11/2019 01:50, Kevin Smith wrote: > Hi, without having dived into the code -- I am wondering what kind of > tagging and indexing is used for the classic memory model in gem5. > Figured this was

Re: [gem5-users] Snoop filter panic when bypassing blocks to MM

Hi Esteban, hi Rich, Your modifications seem to confuse the snoop filter that does sanity checks for the implemented coherence protocol. I'm not sure about the specifics of your changes but I think a safe way to bypass a cache for a given writeback would be to modify BaseCache::access()

Re: [gem5-users] Classic memory model and responding to snoops

Hi Kevin, On 29/07/2019 22:22, Kevin Smith wrote: > Thanks for the explanation, Nikos! Let me ask about two specific > (similar) examples which hopefully will clear it up for me. > > Let's say L1A sends out a read request r1 for some line. No L1s have the > line. The L2 has the line in Exclusive

Re: [gem5-users] Classic memory model and responding to snoops

Hi Kevin, On 29/07/2019 03:35, Kevin Smith wrote: > Hi all, > > I have a question regarding the classic memory model, about how a cache > knows when to respond to a peer (neighbor) cache. Please bear with me as > I try to diagnose what happens and let me know where/if I'm wrong :) > In general,

Re: [gem5-users] Question about writeClean command

Hi Yuan, This is indeed what WriteClean does. It is always initiated by a cache which has a dirty copy of the block and updates any copies that might exist in memories below. This will leave the initiating cache with a clean copy of the block. Nikos On 10/07/2019 20:28, yuan wrote: > Hi, All, >

Re: [gem5-users] Adding ARM cache control instructions

On 07/06/2019 13:40, Eliot Moss wrote: > On 6/7/2019 5:06 AM, Nikos Nikoleris wrote: >> Hi Eliot, >> >> gem5 already implements the AArch32 [1] and AArch64 [2] data cache >> maintenance instructions by VA. Can you use these, or do you need to add >> some custom f

Re: [gem5-users] Adding ARM cache control instructions

Hi Eliot, gem5 already implements the AArch32 [1] and AArch64 [2] data cache maintenance instructions by VA. Can you use these, or do you need to add some custom functionality? [1]: https://github.com/gem5/gem5/commit/eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05#diff-3d3b3ed6a45c8cdc9d511a13c6caaba6

Re: [gem5-users] Memory consistency using different ISAs with classic memory system

Hi Kevin, I believe that most of the MCM depends on the CPU code rather than the memory system. The classic memory system maintains a somewhat strict order and it shouldn't alter the order of the requests further. The cache maintains the order or the requests in the MSHR and it should service

Re: [gem5-users] Write through cache

Hi Shougang, The cache is gem5 doesn't support write through, you would have to implement it yourself. The write through flag in the packet is only used for cache maintenance operations but it might be useful for implementing write-through requests in general. Nikos On 28/03/2019 18:28, yuan

Re: [gem5-users] Simulate limit reached, MinorCPU, related to PF_EXCLUSIVE

It might be obvious and I guess that's what you are doing already but I forgot to mention that another solution ofc would be to revert the patches that add support for the prefetch exclusive instruction. Nikos On 29/03/2019 11:26, Nikos Nikoleris wrote: > Hi William, > > This is ind

Re: [gem5-users] Simulate limit reached, MinorCPU, related to PF_EXCLUSIVE

Hi William, This is indeed a bug which is due to the change that implement the prefetch exclusive instruction. The classic memory system in gem5 was designed with two assumptions which are relevant here: * A cache which fetches a block with an intention to modify it is expected to become the

Re: [gem5-users] Creating Blocking caches (i.e., 1 target per MSHR)

Hi Abishek, A single MSHR can keep track of more than one requests for a given cache line. If you set tgts_per_mshr to 1, then the MSHR will only be able to keep track of a single request for any given cache line. But it can still service requests to other cache lines by allocating more MSHRs.

Re: [gem5-users] Unit-testing SimObject derived classes

Hi Robert, One solution is to link in all dependencies in the binaries. A while back I put together that does that and adds support for GTestSimObject [1] as well as an example unit test for the LRURP [2]. [1]: https://gem5-review.googlesource.com/c/public/gem5/+/15315 [2]:

Re: [gem5-users] Problem with Multiple Channels and Channel Interleaving

Hi Yasir, Are you on a reasonably recent version of gem5? A couple of months back there was a bug in the address map that would essentially route all traffic to a single memory controller. Can you check stats.txt and verify that all dram ctrls are used? Nikos On 20/03/2019 15:14, Qureshi Yasir

Re: [gem5-users] Assert error when running a simple python script

Have a look at the discussion here [1], you might be running into the same issue. However, the patch is not ready yet, I think the conclusion is that we have to send the swap packet to the writeQueue rather than the readQueue. [1]: https://gem5-review.googlesource.com/c/public/gem5/+/17349 Nikos

Re: [gem5-users] Changing configuration after taking the Simpoints

Hi Majid, Checkpoints do not save the state of the cache (at least in the classic memory system). That means that you have to warm-up the caches after restoring from a checkpoint even when the you use the same cache configuration before taking and after restoring the checkpoint. Nikos On

Re: [gem5-users] How to use Non coherence cache

Hi Ric, If you are new to gem5, Jason's website on learning gem5 is a great start. I can highly recommend part1 that explains how to setup a basic gem5 system http://learning.gem5.org/book/part1/simple_config.html . Starting from that system, you can easily add a NonCoherentCache between the

Re: [gem5-users] Doubt regarding L2 cache statsistics (Nikos Nikoleris)

Hi Varun, I am afraid, it is not possible to estimate the total number of WriteReq just by looking at the L2 cache statistics. You should see 1 ReadExReq in the L2 cache for every WriterReq that misses in the dcache but there won't be L2 requests for WriteReq that hit (including MSHR hits) in the

Re: [gem5-users] How to use Non coherence cache

Hi, You can use the NonCoherentCache just like any other cache, but you have to place it below the point of coherence. The point of coherence in gem5 is a CoherentXBar which has the parameter point_of_coherence set to True, and this means that any memory above it is expected to be coherent

Re: [gem5-users] Doubt regarding L2 cache statsistics

Hi Varun, To satisfy a WriteReq in the cache you first have to have an exclusive copy of the cache line [1]. This means that the dcache and the L2 cache will first issue a ReadExReq which will fetch an exclusive copy of the cache line that you want to right to. You should see the same number of

Re: [gem5-users] The questions about TTBR0 update cycles

Hi Dong, At the moment gem5 does not model the timing for flushing the TLB, that is the cost of going through the TLB entries and invalidating them. However, you will see that subsequent code will trigger TLB misses and and will run slower (compared to what you would get if you run the same code

Re: [gem5-users] Questions about the detailed and useful comments in the Cache access related code

Hi Gjins, On 29/08/2018 10:50, Gongjin Sun wrote: > Thank you for clear explanations, Nikos. But I still have several > follow-up discussions. Please see them below. > > > On Tue, Aug 28, 2018 at 5:32 AM, Nikos Nikoleris > mailto:nikos.nikole...@arm.com>> wrote: > >

Re: [gem5-users] Questions about the detailed and useful comments in the Cache access related code

Hi Gjins, Please see below for my response. On 27/08/2018 07:28, Gongjin Sun wrote: > > 1 BaseCache::access(PacketPtr pkt, CacheBlk *, Cycles > , PacketList ) (src/mem/cache/base.cc) > > (1) In the segment "if (pkt->isEviction()) { ...}", if I understand it > correctly, this code segment checks

Re: [gem5-users] Understanding the SnoopFilter

Hi Daniel It seems that there are two different evictions taking place. 1. First the dcache needs to allocate and for that it evicts the dirty line: 6682500: system.cpu.dcache: Create Writeback WritebackDirty [2f500:2f53f] writable: 1, dirty: 1 I am not quite sure what happens to it, I am

Re: [gem5-users] ArmTLB - Table walker must have a valid stage-2 MMU

red: Table walker must have a valid stage-2 MMU To make it easier, I attach the python wrapper of the accelerator (CacheComputeUnit.py) and configuration file (run-ccs.py) that I am using. Again, many thanks for your help!  Best, João Vieira No dia 03/08/2018, às 19:54, Nikos

Re: [gem5-users] Cache Management

Hi Abishek, Timon is right. In gem5 the caches implement a write-back policy. When there is an eviction of a dirty block from L1 then it will be written back to L2. In rare exceptions where allocation is not possible in the L2 (e.g., there is a pending request for the victim block), the

Re: [gem5-users] ArmTLB - Table walker must have a valid stage-2 MMU

Hi Joao, I can't really tell where the problem is but when you configure your system you have to make sure that the cores have a stage 2 MMU for both the data (dstage2_mmu) and the instruction side (istage2_mmu). Nikos On 03/08/2018, 15:28, "gem5-users on behalf of João Miguel Morgado

Re: [gem5-users] Connecting non-coherent component to coherent XBar

Hi Sebastian, It's hard to say which MemObject received the packet where the flag cacheResponding was set. In typical Arm systems (not very different from the one you have), packets with cacheResponding set would stop at the CoherentXBar which has the point_of_coherence parameter set

Re: [gem5-users] size variable in Packet class

Riddhi, You can get the values of these registers if you add some more Exec* flags. IIRC ExecResult might be useful as well. You can see the full list of debug flags with --debug-help. Nikos From: gem5-users on behalf of Google Reply-To: gem5 users mailing list Date: Wednesday, 11 July

Re: [gem5-users] size variable in Packet class

Hi Riddhi, I am not familiar with a way to trace the ALU operations and operands. You could trace the micro-ops and macro-ops and then post-process the trace to filter out the ALU operations. If you wish to do that then have a look at the Exec* debug flags. I believe the debug flags

Re: [gem5-users] size variable in Packet class

Hi Riddhi, Indeed, this is what the DDUMP() macro does, you can either use that or do it on your own. Nikos From: gem5-users on behalf of Google Reply-To: gem5 users mailing list Date: Tuesday, 10 July 2018 at 09:05 To: "gem5-users@gem5.org" Subject: Re: [gem5-users] size variable in

Re: [gem5-users] size variable in Packet class

Hi Riddhi, The size field in the packet class is in bytes. To print the data of a packet you could use the following: DDUMP(Flag, pkt->getConstPtr(), pkt->getSize()); Where Flag is the debugging flag that will enable the print and pkt is the packet you want to print. You will also need to

Re: [gem5-users] Dynamic Associative cache in gem5

om>> wrote: Dear Nikos, Many thanks for your reply. Your suggestion are always helpful in solving issues in gem5. I will try to use writeclean packets. Many thanks, Kind Regards, Avais On Thu, May 3, 2018 at 11:24 PM, Nikos Nikoleris <nikos.nikole...@arm.com<mailto:nikos.nikole.

Re: [gem5-users] Dynamic Associative cache in gem5

Hi Avais, I am not sure exactly what you mean by not invalidating but based on the assertion I am assuming that for some blocks you write back any dirty data and then you retain them in the cache, but it is not clear how you handle subsequent accesses and snoops to any of these blocks. I can

Re: [gem5-users] Write non allocate policy for L2 cache

L2 cache are sent to L1 as dirty blocks and they are marked as clean in L2 cache. Actually, i am also trying to skip this behavior. May be it has caused problem. Many thanks, Best Regards, Avais On Wed, Apr 25, 2018 at 7:40 PM, Nikos Nikoleris <nikos.nikole...@arm.com<mailto:nikos.nikol

Re: [gem5-users] Write non allocate policy for L2 cache

Allocate as previously } Is still there is some mistake in my implementation? Best Regards, Many thanks, Avais On Tue, Apr 24, 2018 at 8:43 PM, Nikos Nikoleris <nikos.nikole...@arm.com<mailto:nikos.nikole...@arm.com>> wrote: Hi Avais, A quick and easy way to achieve t

Re: [gem5-users] Write non allocate policy for L2 cache

Hi Avais, A quick and easy way to achieve this, would be to actually use the tempBlock to fill-in the dcache. The tempBlock will be automatically written back to the L2 as soon as the WriteReq is satisfied. This solution would actually incur a bit of extra traffic between the L1 and L2 but at

Re: [gem5-users] L2 stores data or instruction

Hi Avais, If I am not missing something, it should be quite easy to mark the blocks that are filled due to an instruction fetch. You would first need to add the relevant flag in the CacheBlk class and set the flag in the Cache::handleFill if pkt->req->isInstFetch(). Make sure that you

Re: [gem5-users] DerivO3CPU issue with Ruby memory system (all protocols)

Hi Muhammad, This probably due to the fact that the boot loader in Arm+ruby systems is not part of the memory map and therefore is not considered normal memory. One way to solve this is to disable the check in o3 cpu of whether the fetched instructions are from normal memory. This patch should

Re: [gem5-users] Invalid Program counter of Packet

req->getPC()); pf = new Packet(req, pkt->cmd); pf->allocate(); assert(pf->getAddr() == pkt->getAddr()); assert(pf->getSize() == pkt->getSize()); } On Mon, Jan 15, 2018 at 8:23 PM, Nikos Nikoleris &

Re: [gem5-users] Invalid Program counter of Packet

i modify gem5 to get valid PC value for blocks brought into L2 because of miss in L2 Many Thanks, Best Regards, Avais On Sat, Jan 13, 2018 at 12:21 AM, Nikos Nikoleris <nikos.nikole...@arm.com <mailto:nikos.nikole...@arm.com>> wrote: Hi Avais, If I remember correctly, this

Re: [gem5-users] Invalid Program counter of Packet

Hi Avais, If I remember correctly, this is expected. Evictions, for example, won't have a valid program counter. Nikos On 01/12/18 11:44, hassan yamin wrote: For the packets you are getting invalid program counter, can you check is it read or write packet? On Jan 12, 2018 8:20 PM, "Muhammad

Re: [gem5-users] About multiple cache copies and a related comment called "on the same path to memory"

" (also dirty) because only one dirty block copy can be in O state, right? Thanks On Tue, Dec 19, 2017 at 2:41 AM, Nikos Nikoleris <nikos.nikole...@arm.com<mailto:nikos.nikole...@arm.com>> wrote: Hi Gjins, In your example, for any of the two cores, the path to the memory incl

Re: [gem5-users] About multiple cache copies and a related comment called "on the same path to memory"

Hi Gjins, In your example, for any of the two cores, the path to the memory includes its private caches and the shared cache and it does not include the private caches of other core. gem5's classic memory model implements a MOESI-like snooping protocol and the cache that has the block with the

Re: [gem5-users] ARM Architecture with Ruby Memory model

o difference in stats and config files for both the protocols. Please give me some detailed insights to execute this appropriately. -- Regards, AMIT D. JOSHI On Fri, Aug 18, 2017 at 3:00 PM, Nikos Nikoleris <nikos.nikole...@arm.com<mailto:nikos.nikole...@arm.com>> wrote: Hi Amit,

Re: [gem5-users] ex5_big issues with ruby memory system

sers mailing list Subject: Re: [gem5-users] ex5_big issues with ruby memory system Hi, Thanks for the reply. Yes it crashes as the Linux starts to boot. What particular flags can i enable? best regards, Sharjeel On 25 August 2017 at 19:03, Nikos Nikoleris <nikos.nikole...@arm.com<m

Re: [gem5-users] ex5_big issues with ruby memory system

no issue when it is used in the above NoC with four cores.Any suggestions ? best regards, Sharjeel On 25 August 2017 at 16:58, Nikos Nikoleris <nikos.nikole...@arm.com<mailto:nikos.nikole...@arm.com>> wrote: Hi Sharjeel, Can you provide some more information about your simulatio

Re: [gem5-users] ARM Architecture with Ruby Memory model

Hi Amit, We've recently made some changes and you should be able to run full system simulations using arm and ruby as the memory model. I believe you should be able to boot Linux using the MOESI_CMP_directory ruby protocol and possibly other protocols as well. Nikos

Re: [gem5-users] Invalid transition DMA controller in NoC

ss ranges to DMA Controller is this possible? best regards, Muhammad On 12 June 2017 at 13:10, Nikos Nikoleris <nikos.nikole...@arm.com<mailto:nikos.nikole...@arm.com>> wrote: Hi Muhammad, If I remember correctly, MESI_Two_Level lacks support for multiple DMA controllers. The request message

Re: [gem5-users] Invalid transition DMA controller in NoC

Hi Muhammad, If I remember correctly, MESI_Two_Level lacks support for multiple DMA controllers. The request message does not store the source of the packet and the response doesn't reach the right DMA controller. If you have a look at MOESI_CMP_directory, the DMA controller

Re: [gem5-users] "Bringing multiple Cache-Lines from Main Memory"

Hi Muzamil, As Hassan wrote before you would have to generate multiple requests. You have to choose a cache where you will send these requests from. The corresponding responses will install the cache lines in the same cache. I am afraid that you can't just generate multiple responses in the

Re: [gem5-users] Correct RAS predictions detected as mispredicted

On 02.07.2012 15:56, Nikos Nikoleris wrote: Hi all, I think, I have run into a similar issue. There are cases where a control instruction will take the execution to another control instruction. If both of them are taken and the branch predictor predicts correctly only for the first one

Re: [gem5-users] Correct RAS predictions detected as mispredicted

Hi all, I think, I have run into a similar issue. There are cases where a control instruction will take the execution to another control instruction. If both of them are taken and the branch predictor predicts correctly only for the first one it will: * correctly set the predTaken flag and *