On 3/13/2023 5:33 PM, Abitha Thyagarajan via gem5-users wrote:
Hi Eliot and Mirco,
I had the same issue with `palignr_Vdq_Wdq_Ib` being unimplemented. I tried compiling my application
binary (i.e., the one I was trying to run on gem5, not gem5 itself) to exclude SSE which contains
that
Hi Eliot and Abitha,
After Eliot's advice, I also tried to compile spec using the flags you
used, and also "-march=nocona".
Unfortunately, inspecting the generated assembly, I see that the
"palignr" instruction is always present.
I'll update you if I manage to compile the binaries without
Hi Eliot and Mirco,
I had the same issue with \`palignr_Vdq_Wdq_Ib\` being unimplemented. I tried
compiling my application binary (i.e., the one I was trying to run on gem5, not
gem5 itself) to exclude SSE which contains that instruction. I used gcc flags
\`-mno-sse3 -mno-ssse3 -mno-sse4.1
On 3/9/2023 6:45 PM, Mirco Mannino via gem5-users wrote:
Hi all,
I'm trying to take checkpoints from SimPoints for SPEC CPU 2017 in SE mode. I would like to generate
checkpoints for different ISAs (RISCV and X86).
So far, I did the following:
1) BBV files created using "qpoints" tool
