Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Fri, Feb 28, 2020 at 12:15 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Bobby,
>>
>> Thank you for
Hi,
This work was started in past
You can the progress information and steps required in this link
http://www.m5sim.org/Parallel_M5
For now seeing the mailing I do not see anyone continuing this work, but
there were people who had started working on this
On Sun, Mar 1, 2020 at 2:25 AM YUCHEN ZHO
Hello everyone,
Can anyone provide me with the commit number of the previous stable version
of gem5?
This stable-tags has been removed recently like 3 days before.
*Bobby and Jason*: Is there any reason for removing it?
I am asking this because there are other simulators (mostly from Prof. Onur
t; If anyone else has any more information about this then it’d be much
> appreciated.
>
> Kind regards
> Bobby
>
> --
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> On Mar 1, 2020, at 02:50, Abhishek Singh
> wrote:
>
>
Hi,
The configuration in source code are not decided depending on any specific
architecture.
One needs to change it depending on what architecture they are targeting.
If you read papers who have used gem5, they always target a particular
architecture (skylake, coffee lake, or any and or arm, etc)
github.com/gem5/gem5/commit/bae0edb0d26dc6c4738855cf38e9a6a109ae8003
> I want to ask, whether this change ie *if (activeContexts ==0) *was a
> bug or intentional for some other reason?
>
> Thanks
> KP Arun
>
> On Tue, Feb 18, 2020 at 11:45 PM Abhishek Singh <
> abhishek.singh199...@gmail
Hi Arun,
My bad the issue is still there
Best regards,
Abhishek
On Mon, Mar 2, 2020 at 12:57 AM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:
> Hi Arun,
>
> I tested gem5_19 with classic cache x86 with O3CPU, both smt and multicore
> simulations are workin
Hi,
Follow this
https://gem5art.readthedocs.io/en/latest/
On Mon, Mar 2, 2020 at 12:50 PM FARIDEH ZIAEE
wrote:
> Hi,
> I need to run spec cpu 2006 on gem5-Fs mode but I don't know how to run it.
> also ,according to site""
> https://yulistic.gitlab.io/2016/05/gem5-make-a-new-boot-image/""; I m
y to boot linux kernel with O3 clearly shows there exist some bugs
> in gem5. We need to figure out those issues and fix them.
>
> Regards,
> Ayaz
>
> On Sat, Feb 8, 2020 at 9:30 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi Ayaz,
>>
&g
; of benchmarks didnt works.
> It shown tha :
> warn:instruction 'movntdq_Mo_Vo' unimplemented.
>So,what I do for it?
> And anyone can tell me how to deal with it? Thank you.
>
> -- 原始邮件 --
> *发件人:*
ble should have been updated.
>
> Sorry about the confusion!
>
> Regards,
> Hoa Nguyen
>
>
> On Mon, Mar 2, 2020, 7:55 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi,
>>
>> This is the i got in past when I was trying to run SPEC
Hello Ayaz,
Can this image accept the rcS script provided using the Command line?
For example in this way:
./build/X86/gem5.opt
--outdir=/home/abs218/whisper_gem5_setup/gem5_latest/scalibility_chkpt/
--stats-file=scalibility_chkpt.simout --dump-config=scalibility_chkpt.ini
--redirect-stderr --s
Hello Everyone,
Does anyone has ported spec 2017 benchmarks to SE gem5?
If yes, can you share some steps?
Currently, I am trying FS from gem5art but having some error with the
scripts and I am trying to solve but FS mode according to gem5art, can be
used only with 1 CPU in o3 CPU mode with the co
Hi,
You are right about values of ports not being sensible.
Set the values depending on the architecture (coffee lake, skylake, etc)
Correct values of hardware components can be found in their manual
On Tue, Mar 3, 2020 at 5:32 PM Chang Hyun Park
wrote:
> Thank you, Abhishek for your reply.
>
cript.sh
>
> -Ayaz
>
>
> On Tue, Mar 3, 2020 at 7:32 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Ayaz,
>>
>> Can this image accept the rcS script provided using the Command line?
>>
>> For example in this way:
workloads on O3CPU, and they ran successfully.
>
> We used gem5 19.
>
> Regards,
> Hoa Nguyen
>
> On 3/3/20, Abhishek Singh wrote:
> > Hi Hoa,
> > Are you able to run on o3 cpu.
> > Also, is it same gem5 commit as mentioned on the website?
> >
> &g
7:53 PM Hoa Nguyen wrote:
> Hi Abhishek,
>
> Yes, but the gem5 config only has one-core O3CPU. It could be tweaked to
> multiple cores.
>
> Regards,
> Hoa Nguyen
>
> On Tue, Mar 3, 2020, 3:48 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
Nguyen
>
> On Tue, Mar 3, 2020, 5:28 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi Hoa,
>>
>> For now, I will try to get a single-core.
>>
>> In Building the Disk Image Step, I get an error in compiling spec
>> benchmarks
uot;
https://gem5art.readthedocs.io/en/latest/tutorials/spec2017-tutorial.html";?
Best regards,
Abhishek
On Tue, Mar 3, 2020 at 8:52 PM Hoa Nguyen wrote:
> Did you modify any file downloaded from gem5art repo?
>
> Regards,
> Hoa Nguyen
>
> On Tue, Mar 3, 2020, 5:44 P
sr/.
>
> So, in install-spec2017.sh, we use a sed command to replace that default
> path to /usr.
>
> In your case, the default path might be different, so you would need to
> change the sed command in install-spec2017.sh to change the path to /usr.
>
> Regards,
>
/home/abs218/gem5art_fs/spec2017-experiments
My question is why is it important to make a git repo? also will making git
repo solve the above error?
Best regards,
Abhishek
On Tue, Mar 3, 2020 at 9:46 PM Hoa Nguyen wrote:
> The binaries are compiled on guest.
>
> Regards,
> Ho
d non-zero exit status 128.
(gem5art-env) abs218@comparchT640:~/gem5art_fs/spec2017-experiments$ git
--version
*git version 2.17.1*
*How can I solve this error? *
*Also, is it necessary to use docker and Celery and why? *
Best regards,
Abhishek
On Wed, Mar 4, 2020 at 12:38 AM Abhishek Singh &l
/faq.html
>
> Even though using docker is also not required, it is highly recommended
> since it is an easy way to deploy mongodb server.
>
> Regards,
> Hoa Nguyen
>
> On Tue, Mar 3, 2020 at 10:02 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
Hi,
Here is the ISCA 2011 gem5 slides
http://pages.cs.wisc.edu/~markhill/cs757/Spring2012/includes/isca_pres_2011.pdf
Best regards,
Abhishek
On Thu, Mar 5, 2020 at 4:43 PM chenboya wrote:
> Hi, Everybody
>
> I found some difficulties in using the new gem5.org
> For example, when I want to re
Hi,
I would advise using Atomic Simple Cpu with “—caches” option to create
Simpoints
On Sat, Mar 14, 2020 at 5:35 PM Ali Hajiabadi
wrote:
> Hi everyone,
>
> What is the difference between using NonCachingSimpleCPU
> and AtomicSimpleCPU in order to profile and taking simpoints and
> checkpoints?
Hello Everyone,
I am using gem5-19, I tested
"tests/test-progs/threads/bin/x86/linux/threads" application, when I run
the application using O3CPU and x86 using just one CPU, the application
prints a statement specified in its source file which is
"Validating...Success!"
The source file can be fou
:53 PM Ali Hajiabadi
wrote:
> Thanks for your reply. But se.py script checks that the CPU type is
> non-caching. Is there a reason for that? Can I ignore those checks?
>
> On Sun, Mar 15, 2020 at 5:41 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>>
Hello Everyone,
When I change the gcc/g++ version from 4.8 to 5.5, everything works fine!
Best regards,
Abhishek
On Sat, Mar 14, 2020 at 6:01 PM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:
> Hello Everyone,
>
> I am using gem5-19, I tested
> "tests/tes
Thanks !
On Sun, Mar 15, 2020 at 6:48 PM Kevin Dong wrote:
> Hi everyone,
>
> I've solved this problem, and this is a note for the future readers:
>
> Instead of directly calling queueMemoryWrite() within the L1 controller,
> though the type of its parent class, AbstractController, is as same as
Hi,
Instead macro op name use the opcode
Eg
__asm__(".byte 0xcc, 0x00, 0xcc");
You will need to have complete knowledge up on representing register names
using opcode
You can find it x86 intel manual
On Thu, Mar 19, 2020 at 10:28 AM Muhammad Aamir
wrote:
> Hi everyone,
>
> I have made a cust
Hi,
Can you paste your command line?
On Fri, Mar 20, 2020 at 8:37 PM Anirudh wrote:
> Hello,
>
> I would like some help running the backprop benchmark on AMD gem5-gpu. The
> backprop benchmark is written in OpenCL. I am using g++ v 4.8. I have rocm
> 1.6 installed.
>
> I am seeing this error: “
Hi,
You can refer Intel manual it gives you complete explanation
Also somewhere in the code I don’t remember exactly but there was a
reference to particular intel manual
Also refer to older mail threads which tell about x86 instruction deciding
On Sun, Mar 22, 2020 at 12:02 PM Anis Peysieux
wr
Hi,
Most accurate way is to read the code.
O3CPU does have http://www.m5sim.org/Visualization but it will not give the
diagram below.
Also, learning gem5 tutorial is a great starting point to make your own
architecture or the architecture shown below
On Tue, Mar 24, 2020 at 1:13 PM Md Rubel Ahmed
Hi,
Before it was required to use m5 threads but now you are not required to
use m5thread library
On Tue, Mar 24, 2020 at 5:47 PM Muhammet Abdullah Soytürk <
muhammetabdullahsoyt...@gmail.com> wrote:
> Hi all,
>
> I am trying to simulate an openmp application with 4 cores in SE mode. It
> seems
Hi,
If this is gem5_19 then create a Jira issue for the bug. Also attach
program binary or the link if the test is not part of gem5 repo, so people
can reproduce issue again and see what breaks the behavior
On Mon, Apr 27, 2020 at 3:17 AM yangyuqing--- via gem5-users <
gem5-users@gem5.org> wrot
Hi,
Is there a problem with the mailing service?
I do not get all the mails like before.
I only get emails when someone replies to the question
Currently, I have unsubscribed and subscribed to the list
Also, I have already checked my spam but I miss all the first emails
For example the email sub
Hey.
You can change those parameters for classic cache in config/common/Caches.py
For main memory search for python files in src/mem/ directory, mostly it’s
DRAMCtlr.py file
On Wed, Jun 17, 2020 at 4:00 PM ahmed khalil via gem5-users <
gem5-users@gem5.org> wrote:
> Hi, I am a beginner in gem5 ,I
Hi Ahmed,
The stats file obtained will not be able to give you such detailed
information, you will have to implement your own stats parameter to get
different types of misses.
On Sat, Jun 20, 2020 at 2:27 PM ahmed91khalil--- via gem5-users <
gem5-users@gem5.org> wrote:
> hi ,
> I am working on a
Hi,
It’s a known problem and there’s a Jira issue on it
https://gem5.atlassian.net/plugins/servlet/mobile?originPath=%2Fbrowse%2FGEM5-332#issue/GEM5-332
On Sun, Jun 21, 2020 at 9:11 AM Taiyu Zhou via gem5-users <
gem5-users@gem5.org> wrote:
> I run
> "
> ./build/X86/gem5.opt --debug-flags=DRAM,Ca
Hello Everyone,
I would like to run graph NN application on CPU based architecture, does
gem5 support applications written in pytorch or tensorfow(python)?
Also, if there is another benchmark suite that has Graph NN applications
and can run on gem5, please do tell about it?
PS: I had asked this
Hi,
Can’t you just use prefetcher here?
Just modify the next line (tagged) prefetcher to get the block you want
On Wed, Jun 24, 2020 at 11:53 PM Saideepak Bejawada via gem5-users <
gem5-users@gem5.org> wrote:
> Hi all,
>
> I am trying to bring in another block into the cache in addition to the
>
Hi,
For now the standard stats file from gem5 using classic cache model does
not have MPKI.
So you need to declare the stats and you can access the declared stats in
cpu, see the how cpu calls LSQ (or cache) objects and using that you can
access the MPKI stat from CPU
On Fri, Jun 26, 2020 at 4:2
Hi Anuj,
Method 1:
If you already know the address range, for classic cache model, in the
“src/mem/cache/base.cc” file see the recvTimingReq function.
When the address lies in your desired address range turn the NonCacheable
request flag high for that block. You can find information about this fla
Hi Yuan,
You can use AtomicSimple CPU, it’s an in order CPU
You can find more information here
https://www.gem5.org//documentation/general_docs/cpu_models/SimpleCPU
On Thu, Jul 2, 2020 at 5:23 PM Shougang Yuan via gem5-users <
gem5-users@gem5.org> wrote:
> Hi, All,
>
> I want to use the functio
Hi,
ALPHA ISA is no more supported in gem5-20
Best regards,
Abhishek
On Thu, Jul 23, 2020 at 10:15 AM Saideepak Bejawada via gem5-users <
gem5-users@gem5.org> wrote:
> Hi all,
>
> I am unable to build gem5.opt for ALPHA.
> Error: Cannot find variables file
> /home/saideepak/gem5/build/variabl
Hello Everyone,
I am trying to build a Full system image using Step 2 "Using gem5 utils and
chroot to create a disk image" mentioned here (
https://www.gem5.org/documentation/general_docs/fullsystem/disks).
I cannot locate "Makefile." in gem5_20 (util/m5) and develop branch.
Is this method no mor
rsity
> Email: chongzhizhao4 (at) gmail (dot) com
>
>
> On Fri, Aug 21, 2020 at 12:44 PM Abhishek Singh via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hello Everyone,
>>
>> I am trying to build a Full system image using Step 2 "Using gem5 utils
Hello Everyone,
I am trying to run LeNet and AlexNet (tensor flow code) at this github
(Link: https://github.com/iCAS-Lab/IMAC/tree/master/Tensorflow). I have
made a disk image using Step 2 "Using gem5 utils and chroot to create a
disk image"
I am using Linux-4.8.13 kernel and ubuntu 16. I am a
Hello Everyone,
If anyone has run AlexNet or LeNet using gem5, please let me know how you
did it (source of benchmark, which gem5 commit, which ISA)?
Best regards,
Abhishek
___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email
Hi,
Is your memory full?
On Fri, Aug 28, 2020 at 2:47 PM Dwaipayan Ray via gem5-users <
gem5-users@gem5.org> wrote:
> Hi,
>
> I am getting the attached error while building gem5 in Ubuntu 18.04.
>
> Please help me. A prompt response is really appreciated.
>
> Thanks
> Ray
>
>
> _
verify that. It will help you to provide me the
> required information.
>
> On Sat, Aug 29, 2020 at 12:19 AM Abhishek Singh via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi,
>>
>> Is your memory full?
>>
>> On Fri, Aug 28, 2020 at 2:47 PM Dwai
Hi,
Try including the same caches configuration when you take checkpoint. Your
first step do not have caches.
On Thu, Sep 17, 2020 at 11:31 AM Xuhao Chen via gem5-users <
gem5-users@gem5.org> wrote:
> Hi all,
> I have a simple program:
> #include
> #include
> #include
> #include "/home/cxh/ge
Hi Yuan,
Can you just backtrace using gdb, this will directly point the gem5
function which is giving the error?
On Fri, Oct 2, 2020 at 12:01 PM Shougang Yuan via gem5-users <
gem5-users@gem5.org> wrote:
> Hi, Giacomo,
>
> Thanks for your help. I am currently suffering a new problem. I set the
>
backtrace
On Fri, Oct 2, 2020 at 12:13 PM Shougang Yuan wrote:
> Hi, Abhishek,
>
> Thanks for your help. Do you have any hints about gdb backtrace in gem5? I
> am new to gdb debugging.
>
> Best regards.
>
> On Fri, Oct 2, 2020 at 12:03 PM Abhishek Singh <
> abhishe
Hi,
Does this happen with O3 CPU or just the in order CPU?
On Thu, Oct 22, 2020 at 1:01 PM Muhammad Aamir via gem5-users <
gem5-users@gem5.org> wrote:
> Hi everyone,
>
> I have noticed that the stat: "system.cpu.dcache.overall_miss_rate::total"
> is the same if I only use 1 level of cache or use
Hi,
I do not think that making the cache hierarchy deeper will have any effect
on 1'st level cache hit/miss rate.
Best regards,
Abhishek
On Thu, Oct 22, 2020 at 1:03 PM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:
> Hi,
>
> Does this happen with O3 CPU or j
Hi Hasan,
I have been trying to run tensorflow on gem5, have you tried full system?
I was able to run simple python code like hello on it.
Let me know if it works
On Fri, Oct 23, 2020 at 12:28 PM Hasan, S M Shamimul via gem5-users <
gem5-users@gem5.org> wrote:
> Hello,
>
> * I want to run cosmoGA
Hi,
I think you should check already implemented policies in
src/mem/cache/replacement_policies and then design yours taking that as an
template/example.
In order to get information which you mentioned, you might have to
change/add arguments to accessBlock, findBlock, insertBlock, etc function
in
Hi Krishna,
I hope you are doing well too.
The experiment which you described, I think gem5art group has been
successful to pull that off.
Here is the link
https://gem5art.readthedocs.io/en/latest/, you can see their SPEC benchmark
example as the starting point
On Sun, Nov 1, 2020 at 12:46 PM kri
Hello,
I would like to know if anyone knows of a protocol implemented in Ruby with
all the cache levels prefetcher modeling. I have been researching this
topic and am still trying to find a clear answer. If anyone has any
insights or knowledge on this matter, I would greatly appreciate your input.
Hello,
Is it possible to use prefetcher with CHI protocol for a ruby memory system
with the current CHI model implementation?
I noticed that the CHI config file has an assertion condition on setting
prefetcher.
How does the prefetcher model in ruby interact with the coherence protocol?
_
oups0.cpus.decode.branchMispred) is
separate from the Commit counter
(system.chips.clusters.cpu_groups0.cpus.commit.branchMispredicts)?
2. Are IEW branchMispredicts
(system.chips.clusters.cpu_groups0.cpus.iew.branchMispredicts) included in
the Commit counter?
Thank you,
Abhishek
Hello,
Does anyone know why doesn't the prefetcher coverage statistic in the
classic cache account for the pfUsefulButMiss metric? The existing
definition of coverage and accuracy appears flawed, as it fails to
incorporate pfUsefulButMiss in calculating the true useful prefetches
(pfUseful - pfUs
Hello,
How do the functions m5_work_begin and m5_work_end operate? I've
incorporated them into my code while running FS mode. Does it generate
multiple statistics when my fs script includes m5 dumpresetstats after
booting and utilizes m5_work_begin(0,0) before a function call, followed by
m5_work_
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