All
Following the release of z390 v1.4.01a with new date and time callable routine
named DAT that can be used for benchmark testing, I’ve published a first
solution to problem #18. The solution shows that the MIP rate dropped 15%
when using the new z10 compare and branch code, but the elapsed
In <[EMAIL PROTECTED]>, on 12/13/2007
at 07:16 AM, Rick Fochtman <[EMAIL PROTECTED]> said:
>Can anyone help me find more details on the "z" architecture so I can
>read up on this sort of thing?
It's an implementation issue rather than an architectural issue. The code
that is faster on one proc
In <[EMAIL PROTECTED]>, on 12/15/2007
at 06:36 PM, Edward Jaffe <[EMAIL PROTECTED]> said:
>The TR instruction will always be slower than equivalent instructions
>for strings shorter than 'n' bytes because of the startup costs
>associated with invoking a millicode instruction
No. You're assum
All
A new problem #10 and another solution for problem #9 have been posted on
the contest web site here:
http://z390.sourceforge.net/z390_Mainframe_Assemble_Coding_Contest.htm
This new problem should not be too hard (no floating point required) so you
can work on it while watching bowl games
John P. Baker wrote:
Is it the fastest when run on current hardware? That may be impossible to
determine. Even with millicode involvement, the compactness of the code
will ensure that everything is cached, so that the resultant execution time
"may" equal or even "better" the non-millicode solut
f Art Celestini
Sent: Saturday, December 15, 2007 9:17 AM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Mainframe Assembler Coding Contest
What is the goal of this "contest?" Instruction count or ultimate speed on
current, real hardware? Both of these solutions use TRanslate, which sends
you
in
What is the goal of this "contest?" Instruction count or ultimate speed on
current, real hardware? Both of these solutions use TRanslate, which sends you
into millicode (generally, a big ouch when it comes to performance). UNPK, as
used in another, may do the same, at least on certain microproce
P Baker
-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On Behalf
Of Joel C. Ewing
Sent: Friday, December 14, 2007 10:48 PM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Mainframe Assembler Coding Contest
Did the original problem statement require this be done wit
Rick Fochtman wrote:
Tom Marchant wrote:
On Thu, 13 Dec 2007 17:13:09 -0800, Tom Simons wrote:
Here's 8 instructions to translate 8 bits to 8 chars of 1's or 0's:
LAR3,8
ICR5,INBYTE
SLL R5,24
LOOP SLL R4,3
SLDL R4,1
BCT R3,LOOP
AIL PROTECTED]>
Subject: Re: Mainframe Assembler Coding Contest
Here's 8 instructions to translate 8 bits to 8 chars of 1's or 0's:
LAR3,8
ICR5,INBYTE
SLL R5,24
LOOP SLL R4,3
SLDL R4,1
BCT R3,LOOP
STR4,O
Tony Harminc wrote:
On Fri, 14 Dec 2007 10:48:08 -0800, Edward Jaffe wrote:
Please see David Bond's excellent presentation from SHARE 107 in
Baltimore entitled, "Session 8192: Coding Assembler for Performance".
http://shareew.prod.web.sba.com/client_files/callpapers/attach/SHARE_in_Baltimore
On Fri, 14 Dec 2007 10:48:08 -0800, Edward Jaffe wrote:
>Please see David Bond's excellent presentation from SHARE 107 in
>Baltimore entitled, "Session 8192: Coding Assembler for Performance".
>http://shareew.prod.web.sba.com/client_files/callpapers/attach/SHARE_in_Baltimore/S8192DB073718.pdf
Wha
Oops! In re-reading this, I see an error. :-[
I wrote:
The BTB keeps only those branches _predicted to be_ taken ...
This should say, "The BTB keeps only those branches _actually_ taken ..."
--
Edward E Jaffe
Phoenix Software International, Inc
5200 W Century Blvd, Suite 800
Los Angeles, CA 9
Chase, John wrote:
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of Rick Fochtman
Tom Marchant wrote:
On Thu, 13 Dec 2007 17:13:09 -0800, Tom Simons wrote:
Here's 8 instructions to translate 8 bits to 8 chars of 1's or 0's:
LAR3,8
IC
Art Celestini wrote:
Another interesting example, as discussed earlier, is LHI vs. LA. It too, has
the condition code consideration. However, consider the use of LA in the
following arithmetic (non-address) situation:
LA R1,789(R2,R3)
To do this without LA would take something like:
> -Original Message-
> From: IBM Mainframe Discussion List On Behalf Of Rick Fochtman
>
> Tom Marchant wrote:
>
> >On Thu, 13 Dec 2007 17:13:09 -0800, Tom Simons wrote:
> >
> >>Here's 8 instructions to translate 8 bits to 8 chars of 1's or 0's:
> >>
> >>LAR3,8
> >>IC
Thanks, Ed. I seemed to remember that there was a later "version" of the
microprocessor discussion, I just couldn't find it quickly.
The "problem" is that things can change in subtile ways from one processor
generation to the next. I've therefore adopted a general "KISS" approach --
within
Paul Gilmartin wrote:
On Fri, 14 Dec 2007 08:04:50 -0800, Edward Jaffe wrote:
"BC/BRC-type are statically predicted not-taken (except if the mask is
'F'x), BCT, BXLE, and BXH-type are statically guessed taken. For
BC/BRC-type this is correct about 55% of the time for most code and
BCT/BXLE-t
Tom Marchant wrote:
On Thu, 13 Dec 2007 17:13:09 -0800, Tom Simons wrote:
Here's 8 instructions to translate 8 bits to 8 chars of 1's or 0's:
LAR3,8
ICR5,INBYTE
SLL R5,24
LOOP SLL R4,3
SLDL R4,1
BCT R3,LOOP
STR4,OUTCHAR
On Fri, 14 Dec 2007 08:04:50 -0800, Edward Jaffe wrote:
>
>"BC/BRC-type are statically predicted not-taken (except if the mask is
>'F'x), BCT, BXLE, and BXH-type are statically guessed taken. For
>BC/BRC-type this is correct about 55% of the time for most code and
>BCT/BXLE-type are correct 90+% o
Art Celestini wrote:
Much of what I was talking about is described here:
http://www.research.ibm.com/journal/rd/446/webb.html
although even this paper is somewhat "dated" by now.
Art, I suggest you take a look at
http://researchweb.watson.ibm.com/journal/rd/483/slegel.html. Nearly all
of wh
> -Original Message-
> From: IBM Mainframe Discussion List
> [mailto:[EMAIL PROTECTED] On Behalf Of Art Celestini
> Sent: Friday, December 14, 2007 8:49 AM
> To: IBM-MAIN@BAMA.UA.EDU
> Subject: Re: Mainframe Assembler Coding Contest
>
>
> Much of what I was
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On
> Behalf Of Art Celestini
> Sent: Friday, December 14, 2007 9:49 AM
> To: IBM-MAIN@BAMA.UA.EDU
> Subject: Re: Mainframe Assembler Coding Contest
>
> Much of what I was talking
Much of what I was talking about is described here:
http://www.research.ibm.com/journal/rd/446/webb.html
although even this paper is somewhat "dated" by now. My understanding is that
the z9
class microprocessors have a much deeper (longer) pipeline, and the logic that
looks at
instructions ver
All
Update #5 - All z390 mainframe assembler coding contest solutions have been
reformatted using new ZMFACC macro for portability across multiple OS and
new problem and solution submission email methods. The source and
generated log files for each of the ranked solutions are now directly
On Thu, 13 Dec 2007 17:13:09 -0800, Tom Simons wrote:
>Here's 8 instructions to translate 8 bits to 8 chars of 1's or 0's:
>
> LAR3,8
> ICR5,INBYTE
> SLL R5,24
>LOOP SLL R4,3
> SLDL R4,1
> BCT R3,LOOP
> STR4,OUTCHAR
> U
Not my day. The 404 is fixed.
And after slagging off the Vole, I just got this from "a Microsoft
spokesperson":
"We believe Platform Solutions, Inc. is uniquely positioned to bridge the gap
between legacy
mainframe computing and 21st century server technology in today's enterprise
environment
>http://www.isham-research.co.uk/images/teeth.jpg
I get a 404: Not found
-
Too busy driving to stop for gas!
--
For IBM-MAIN subscribe / signoff / archive access instructions,
send email to [EMAIL PROTECTED] with the message: GET
> .. BCTR Rx,0 ..
I've had conversations with processor designers at both Amdahl and IBM. The
general idea is
that a BCTR that cannot be taken (target register = 0) is recognized as a
special form of BCTR
and has been, in fact, since the 360/85.
And a BCTR or BCT with a non-zero target is alwa
Here's 8 instructions to translate 8 bits to 8 chars of 1's or 0's:
LAR3,8
ICR5,INBYTE
SLL R5,24
LOOP SLL R4,3
SLDL R4,1
BCT R3,LOOP
STR4,OUTCHAR
UNPK OUTCHAR(9),OUTCHAR(5)
OUTCHAR DSCL8
DSX
I
Of course, as fate would have it, I spotted a bug just after I posted.
The SLR R2,R2 has to be inside the loop:
ICM R3,8,BYTE
LHI R1,8
LHI R0,X'F0'
LOOP SLR R2,R2
SLDL R4,8
SLDL R2,1
ORR5,R2
ORR5,R0
BCT
Okay, this is absolutely my last cut at this. (I've got other things to
do ;-) .) The thing that bothered me in the last iteration was the STC
inside the loop -- too many storage references. Here's a solution that
is very similar to Bob Rutledge's that I like much better because it
performs a
Similar to what I said in an earlier post about BCTR Rx,0, I suspect that
the early stages of the pipeline just do a "raw" classification of the
upcoming instructions -- perhaps just by their op-codes. Because Load-
Address involves a process of generating an address from a base/displacement
(and
> -Original Message-
> From: IBM Mainframe Discussion List On Behalf Of Art Celestini
>
> Well, just for the sport of it, I think this requires even
> less (not tested):
>
> LHI R1,8
> ICR2,BYTE
> STC STC R2,RESULT-1(R1)
> SRL R2,1
> BCT
---:
I understand that LA can cause an "address generation interrupt" in
the pipeline on some "z" models and as a rule of thumb, LHI is better
to use when you can. Similar nasties occur with things like BCTR Rx,0
(typically used to decrement a register),
Got it, John. The MVO threw me; I mis-interpreted its action.
Rick
---
John P. Baker wrote:
Actually, it will be exactly what it should be, if my desk checking is
correct.
Step by step:
Contents of IBYTE = X'10'
After: MVC OBUFF(1),IBYTE (Note the correction
A modification of a previous submission:
LA R1,8
IC R2,BYTE
STC LA R15,RESULT-1(R1)
STCR2,0(,R15)
NI 0(R15),X'01'
OI 0(R15),X'F0'
SRLR2,1
BCT R1,STC
*
BYTE DCB'01
Actually, it will be exactly what it should be, if my desk checking is
correct.
Step by step:
Contents of IBYTE = X'10'
After: MVC OBUFF(1),IBYTE (Note the correction "(1)")
Contents of OBUFF = X'10xx'
After: MVC OBUFF+1(7),OBUFF
Contents of OBUFF = X'1010101010101010'
After:
I should have added "after WORK8 is changed to OBUFF", a correction which
was mentioned in earlier posts.
Bill
On Wed, 12 Dec 2007 23:42:12 -0600, Bill Godfrey wrote:
>John's code is correct. There won't be a value X'10' in OBUFF. Only hex
values
>00, 01, 02, 04, and 08.
>
>Even this would wor
Sorry, I didn't see your correction until after I made my "submission."
For at least the past few generations of mainframe processors, "storage
references" have been pretty much the most "costly" kind of operation.
Even with the data in Level 1 cache, it takes one or two machine cycles
to update
John's code is correct. There won't be a value X'10' in OBUFF. Only hex values
00, 01, 02, 04, and 08.
Even this would work:
TR OBUFF,=C'011-1---1'
Bill
On Wed, 12 Dec 2007 22:38:30 -0600, Rick Fochtman wrote:
>Look again at your translate table. What will value X'10" translate to???
>
I understand that LA can cause an "address generation interrupt" in
the pipeline on some "z" models and as a rule of thumb, LHI is better
to use when you can. Similar nasties occur with things like BCTR Rx,0
(typically used to decrement a register), such that AHI Rx,-1 tends to
work better. (I
---
Well, just for the sport of it, I think this requires even less
(not tested):
LHI R1,8
ICR2,BYTE
STC STC R2,RESULT-1(R1)
SRL R2,1
BCT R1,STC
NCRESULT,=8X'01'
OCRESULT,=8X'F0'
*
B
Look again at your translate table. What will value X'10" translate to???
Nice try...
Rick
John P Baker wrote:
I have not tested it, but the following code should be the most compact form of
generating a binary character string from a by
,R0 Decrement R2
B NEXT1 Go get next one
*
PRINTIT TPUT BINNUM,L'BINNUMTPUT Results
*
*
BINNUM DCCL8'' Converted Number
-Original Message-
From: IBM Mainframe Discussion List on behalf of Binyamin Dissen
Sen
hardware.
John P Baker
-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On Behalf
Of Art Celestini
Sent: Wednesday, December 12, 2007 8:52 PM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Mainframe Assembler Coding Contest
Well, just for the sport of it, I think
I didn't originally think of doing the AND and OR inside the loop,
but based on the reduction in storage references, I think this
might be even faster, albeit more instructions:
LHI R1,8
LHI R4,X'F0'
ICR2,BYTE
LOOP LHI R3,X'01'
NRR3,R2
I've been testing all... Might as well come out of the dark...
You pass !
-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On
Behalf Of Art Celestini
Sent: Wednesday, December 12, 2007 8:52 PM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Mainframe Asse
Well, just for the sport of it, I think this requires even less
(not tested):
LHI R1,8
ICR2,BYTE
STC STC R2,RESULT-1(R1)
SRL R2,1
BCT R1,STC
NCRESULT,=8X'01'
OCRESULT,=8X'F0'
*
BYTE DCB'01110101'Sample i
Tables? We don't need no steenkin' tables!
ic3,byte
sll 3,24
lhi 4,8
lp sllg 5,5,8
slr 2,2
sldl 2,1
ahi 2,c'0'
or5,2
jct 4,lp
stg 5,wherever
Bob
Untested:
DISPBITS SUBENTRY ,
ICR0,INPUTGET BYTE TO DISPLAY IN R0
LAR2,8NUMBER OF BITS
LOOP DS0H
SRDL R0,1SHIFT NEXT BIT INTO R1
SRL R1,7+24 SHIFT TO THE BOTTOM
STC R1
> -Original Message-
> From: IBM Mainframe Discussion List On Behalf Of John P Baker
>
> Sorry. WORK8 should be OBUFF.
>
> I was changing labels and missed one.
No biggie. I changed mine from shifting left to shifting right, and
missed the target register . TWICE.
-jc-
--
Sorry. WORK8 should be OBUFF.
I was changing labels and missed one.
John P Baker
--
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send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO
Search the
fun on a slow wednesday
variation on theme at bottom saves 2 instructs/8 bytes :>)
> BINPRINT CSECT ,
> YREGS
> LBR0,BYTE
la r14,2
la r15,word2
l0 ds 0h
> LAR2,4
> L1 SRDL R0,1
SRL
7;b
whereverBYTES DCX'FF2B1C3F' OP1DSCL8' '
Bill > Date: Wed, 12 Dec 2007 15:09:47 -0600> From: [EMAIL
PROTECTED]> Subject: Re: Mainframe Assembler Coding Contest> To:
IBM-MAIN@BAMA.UA.EDU
I have not tested it, but the following code should be the most compact form of
generating a binary character string from a byte value (Problem #6):
MVC OBUFF,IBYTE
MVC OBUFF+1(7),WORK8
NCOBUFF,=X'8040201008040201'
MVO WORK5,OBUFF(4)
MVC OB
> -Original Message-
> From: Chase, John
>
> > -Original Message-
> > From: IBM Mainframe Discussion List On Behalf Of Arthur T.
> >
> > I don't have a working assembler or emulator at the
> moment, so I
> > can't test this. Also, I'm not joining a Yahoo group just for t
On 12 Dec 2007 11:52:42 -0800, in bit.listserv.ibm-main
(Message-ID:<[EMAIL PROTECTED]>)
[EMAIL PROTECTED] (Binyamin Dissen) wrote:
Constraints are not well defined.
If one can use an 8*256 byte table 3 silicon
instructions (4, if LB is in
silicon) - not tested
If you went to th
> -Original Message-
> From: IBM Mainframe Discussion List On Behalf Of Arthur T.
>
> I don't have a working assembler or emulator at the
> moment, so I can't test this. Also, I'm not joining a Yahoo
> group just for this contest. But I think this is a solution
> to #6: "Given
On Wed, 12 Dec 2007 14:18:51 -0500 "Arthur T." <[EMAIL PROTECTED]> wrote:
:>On 12 Dec 2007 04:50:17 -0800, in bit.listserv.ibm-main
:>(Message-ID:<[EMAIL PROTECTED]>)
:>[EMAIL PROTECTED] (Don Higgins) wrote:
:>>There is a new Mainframe Assembler Coding Conte
On 12 Dec 2007 04:50:17 -0800, in bit.listserv.ibm-main
(Message-ID:<[EMAIL PROTECTED]>)
[EMAIL PROTECTED] (Don Higgins) wrote:
There is a new Mainframe Assembler Coding Contest underway
here:
http://z390.sourceforge.net/z390_Mainframe_Assemble_Coding_Contest.htm
Check out prob
Just uploaded EZSAMPLE for #6.
Raymond Wong
Brookline, MA
-Original Message-
From: Don Higgins <[EMAIL PROTECTED]>
To: IBM-MAIN@BAMA.UA.EDU
Sent: Wed, 12 Dec 2007 6:50 am
Subject: Mainframe Assembler Coding Contest
There is a new Mainframe Assembler Coding Contest underwa
Have just signed up to this. Looks like fun. IBM has something like that
in place as well.
Looking at the TROT example, which caught my eye not having used the
instruction before, I think there is a bug as TROT can be interrupted
according to POPS.
I posted a reply, but being an ejit at times
There is a new Mainframe Assembler Coding Contest underway here:
http://z390.sourceforge.net/z390_Mainframe_Assemble_Coding_Contest.htm
I've just added direct link to Powerpoint presentation by Khristine Harper on
Asembler in the 21 Century. There is also a new link to upcoming SHARE
se
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