Re: [Intel-gfx] i915 and 1440p display w/ corrupt EDID

On Wed, 24 Sep 2014, Mathias Burén wrote: > I've a 1440p display with a non-sufficient/corrupt EDID. Just to double check, you mean the display really is broken in this regard, *not* that the driver is unable to read the EDID? Does your monitor have other connections than HDMI? Can you try to se

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Adds graphic address space ballooning logic

Hi Chris & Daniel, Thanks for your comments. Following are my understandings about the changes needed for this patch: 1> We do not need the guard page anymore between different VMs. For the very last physical GTT entry, let's keep it pointing to a guard page. 2> To reserve the GMs in our

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Adds graphic address space ballooning logic

On Fri, Sep 26, 2014 at 04:26:20PM +0800, Zhang, Yu wrote: > Hi Chris & Daniel, > > Thanks for your comments. Following are my understandings about > the changes needed for this patch: > > 1> We do not need the guard page anymore between different VMs. For > the very last physical GTT entry, le

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Adds graphic address space ballooning logic

On 9/26/2014 4:48 PM, Chris Wilson wrote: On Fri, Sep 26, 2014 at 04:26:20PM +0800, Zhang, Yu wrote: Hi Chris & Daniel, Thanks for your comments. Following are my understandings about the changes needed for this patch: 1> We do not need the guard page anymore between different VMs. For th

[Intel-gfx] [PATCH 1/2] lib/igt_core: make single/simple tests use igt_exit

From: Tim Gore Currently tests that use igt_simple_main will simply call "exit()" if they pass, making it difficult to ensure that any required cleanup is done. At present this is not an issue, but it will be when I submit a patch to turn off the lowmemorykiller for all tests. Signed-off-by: Tim

[Intel-gfx] [PATCH 0/2] Disable Android low memory killer

From: Tim Gore For some tests that put pressure on memory, the Android lowmemorykiller needs to be disabled for the test to run to completion. The first patch is a simple bit of preparation to ensure that all (well written) "simple" tests exit via a call to igt_exit, in the same way as tests with

[Intel-gfx] [PATCH 2/2] lib/igt_core.c: disable lowmemorykiller during tests

From: Tim Gore Several IGT tests put a lot of pressure on memory and when running these tests on Android they tend to get killed by the lowmemorykiller. The lowmemorykiller really is not usefull in this context and is just preventing the test from doing its job. So this commit disables the lowmem

[Intel-gfx] [PATCH] drm/i915: Do not store the error pointer for a failed userptr registration

If we fail to create our mmu notification, we report the error back and currently store the error inside the i915_mm_struct. This not only causes subsequent registerations of the same mm to fail (an issue if the first was interrupted by a signal and needed to be restarted) but also causes us to eve

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

On Fri, Sep 26, 2014 at 10:27:22AM +0100, tim.g...@intel.com wrote: > From: Tim Gore > > For some tests that put pressure on memory, the Android > lowmemorykiller needs to be disabled for the test to run to > completion. The first patch is a simple bit of preparation > to ensure that all (well wr

Re: [Intel-gfx] [PATCH] drm/i915: Do not store the error pointer for a failed userptr registration

On 09/26/2014 10:31 AM, Chris Wilson wrote: If we fail to create our mmu notification, we report the error back and currently store the error inside the i915_mm_struct. This not only causes subsequent registerations of the same mm to fail (an issue if the first was interrupted by a signal and ne

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

> -Original Message- > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > Sent: Friday, September 26, 2014 10:50 AM > To: Gore, Tim > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer > > On Fri, Sep 26, 2014 at 10:27:22AM +0

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

On Fri, Sep 26, 2014 at 10:08:54AM +, Gore, Tim wrote: > > > > -Original Message- > > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > > Sent: Friday, September 26, 2014 10:50 AM > > To: Gore, Tim > > Cc: intel-gfx@lists.freedesktop.org > > Subject: Re: [Intel-gfx] [PATCH 0/2] D

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

On Fri, Sep 26, 2014 at 10:08:54AM +, Gore, Tim wrote: > I don't think so. This is really just about the Android low memory killer > having > Different goals to kswapd. Kswapd tries to keep a certain amount of free > memory > so that the kernel can run smoothly. On Android the lowmemorykiller

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

> -Original Message- > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > Sent: Friday, September 26, 2014 11:30 AM > To: Gore, Tim > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer > > On Fri, Sep 26, 2014 at 10:08:54AM +0

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

On Fri, Sep 26, 2014 at 10:46:48AM +, Gore, Tim wrote: > > > > -Original Message- > > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > > Sent: Friday, September 26, 2014 11:30 AM > > To: Gore, Tim > > Cc: intel-gfx@lists.freedesktop.org > > Subject: Re: [Intel-gfx] [PATCH 0/2] D

Re: [Intel-gfx] [PATCH 3/5] drm/i915/bdw: WaProgramL3SqcReg1Default

Rodrigo Vivi writes: > Program the default initial value of the L3SqcReg1 on BDW for performance > > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

Rodrigo Vivi writes: > This helps when including or removing cs workarounds. > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 16 > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/driv

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

On Fri, 26 Sep 2014, Mika Kuoppala wrote: > Rodrigo Vivi writes: > >> This helps when including or removing cs workarounds. >> Signed-off-by: Rodrigo Vivi >> --- >> drivers/gpu/drm/i915/intel_ringbuffer.c | 16 >> 1 file changed, 12 insertions(+), 4 deletions(-) >> >> diff --gi

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

On Fri, Sep 26, 2014 at 03:56:02PM +0300, Jani Nikula wrote: > On Fri, 26 Sep 2014, Mika Kuoppala wrote: > > Rodrigo Vivi writes: > > > >> This helps when including or removing cs workarounds. > >> Signed-off-by: Rodrigo Vivi > >> --- > >> drivers/gpu/drm/i915/intel_ringbuffer.c | 16 ++

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

On Fri, Sep 26, 2014 at 01:58:12PM +0100, Chris Wilson wrote: > > > I have a bit mixed feelings with this patch as I have tripped > > > around here myself recently. > > > > > > I think we should just drop this patch and use: > > > ret = intel_ring_begin(ring, 3 * ) on the subsequent > > > patches t

[Intel-gfx] [PATCH libdrm 3/3] intel/skl: add gen9 to the CS decoding init

Signed-off-by: Damien Lespiau Reviewed-by: Kenneth Graunke Signed-off-by: Ben Widawsky --- intel/intel_decode.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/intel/intel_decode.c b/intel/intel_decode.c index a5d6e04..7d5cbe5 100644 --- a/intel/intel_decode.c +++ b/intel

[Intel-gfx] [PATCH libdrm 2/3] intel/skl: Add gen9 to the buffer manager init

Signed-off-by: Damien Lespiau Reviewed-by: Kenneth Graunke Signed-off-by: Ben Widawsky --- intel/intel_bufmgr_gem.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index ba65527..a6fa224 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/

[Intel-gfx] [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids

v2: Add more PCI IDs (Michael H. Nguyen) v3: Synchronize one more with the kernel PCI IDs (Damien) Signed-off-by: Damien Lespiau Signed-off-by: Ben Widawsky Signed-off-by: Michael H. Nguyen --- intel/intel_chipset.h | 43 ++- 1 file changed, 42 insertion

[Intel-gfx] [PATCH i-g-t 10/26] rendercopy/skl: Set Instruction Buffer size Modify Enable to 1

From: Zhao Yakui This is ported from that on BDW. Reviewed-by: Damien Lespiau Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/rendercopy_gen9.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/rendercopy_gen9.c b/lib/renderc

[Intel-gfx] [PATCH i-g-t 11/26] rendercopy/skl: Fix the STATE_BASE_ADDRESS instruction length

From: Zhao Yakui Reviewed-by: Damien Lespiau Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/rendercopy_gen9.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index dce63

[Intel-gfx] [PATCH i-g-t 07/26] rendercopy/skl: Update 3DSTATE_SBE

SBE has now to be explicitely told which channels of which components are used by the pixel shader. Signed-off-by: Damien Lespiau Signed-off-by: Ben Widawsky --- lib/gen9_render.h | 5 + lib/rendercopy_gen9.c | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/lib/ge

[Intel-gfx] [PATCH i-g-t 14/26] rendercopy/skl: Follow the spec to add the Pipeline selection mask

From: Zhao Yakui Reviewed-by: Damien Lespiau Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/gen9_render.h | 2 ++ lib/rendercopy_gen9.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/gen9_render.h b/lib/gen9_render.

[Intel-gfx] [PATCH i-g-t 01/26] skl: Add SKL PCI ids

v2: Update to the latest PCI ids Signed-off-by: Damien Lespiau Signed-off-by: Ben Widawsky --- lib/intel_chipset.h | 58 +++-- 1 file changed, 52 insertions(+), 6 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 404c632..

[Intel-gfx] [PATCH i-g-t 06/26] rendercopy/skl: Set the 3DSTATE_VF state

This is to ensure the "Component Packing Enable" bit is set to 0. Signed-off-by: Damien Lespiau Signed-off-by: Ben Widawsky --- lib/gen9_render.h | 1 + lib/rendercopy_gen9.c | 5 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/gen9_render.h b/lib/gen9_render.h index

[Intel-gfx] [PATCH i-g-t 08/26] rendercopy/skl: Pass the context to rendercopy function on SKL

From: Zhao Yakui Reviewed-by: Damien Lespiau Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky --- lib/rendercopy.h | 1 + lib/rendercopy_gen9.c | 12 +++- tools/intel_error_decode.c | 1 + 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/lib/renderc

[Intel-gfx] [PATCH i-g-t 03/26] skl: initialize instdone bits for gen9

gen9 uses the same bits as gen8. Signed-off-by: Damien Lespiau Reviewed-by: Jesse Barnes Signed-off-by: Ben Widawsky --- lib/instdone.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/lib/instdone.c b/lib/instdone.c index 51cdff9..fffb949 100644 --- a/lib/instdone

[Intel-gfx] [PATCH i-g-t 15/26] rendercopy/skl: Set the URB VS start address to 4

From: "Xiang, Haihao" A value less than 4 might result in GPU hang on simulation Signed-off-by: Xiang, Haihao Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/rendercopy_gen9.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/rendercopy_gen9.c b/lib/re

[Intel-gfx] [PATCH i-g-t 02/26] skl: Add gen9 to intel_gen()

Signed-off-by: Damien Lespiau Reviewed-by: Jesse Barnes Signed-off-by: Ben Widawsky --- lib/intel_chipset.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c index 0828e44..fafd232 100644 --- a/lib/intel_chipset.c +++ b/lib/intel_chipset.c @@ -172,6

[Intel-gfx] [PATCH i-g-t 04/26] list-workarounds/skl: Add Skylake to the list of valid platorms

Signed-off-by: Damien Lespiau --- scripts/list-workarounds | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/list-workarounds b/scripts/list-workarounds index 5a84ee8..620d02f 100755 --- a/scripts/list-workarounds +++ b/scripts/list-workarounds @@ -18,7 +18,7 @@ def find

[Intel-gfx] [PATCH i-g-t 09/26] rendercopy/skl: update instruction length

From: Zhao Yakui This is ported from that on BDW. v2: Only bump the prefix when we need to program the instruction differently with the previous generations. Reviewed-by: Damien Lespiau Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/rendercopy_g

[Intel-gfx] [PATCH i-g-t 05/26] rendercopy/skl: Start the gen9 rendercopy from the gen8 version

v2 (Ben): Rebased on: commit ea11d103e0617e33bce6f11328521d15b13422b0 Author: Oscar Mateo Date: Tue Nov 12 11:50:35 2013 + build: list all test/tool/lib source files in their own Makefile.sources v3: (Ben): Rebased on the doc/API rework. Probably needs review Signed-off-by: Damien Le

[Intel-gfx] [PATCH i-g-t 16/26] assembler/skl: Add gen 9 to the -g option

Signed-off-by: Damien Lespiau Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- assembler/disasm-main.c | 4 ++-- assembler/main.c| 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/assembler/disasm-main.c b/assembler/disasm-main.c index 5e4cb0e..b365556

[Intel-gfx] [PATCH i-g-t 12/26] rendercopy/skl: Fix the 3DSTATE_DS instruction length

From: Zhao Yakui Reviewed-by: Damien Lespiau Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/rendercopy_gen9.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index f98019e..

[Intel-gfx] [PATCH i-g-t 13/26] rendercopy/skl: Emit 3DSTATE_WM_HZ_OP

From: Zhao Yakui This is from that on BDW. Without it, the pixel pipeline can't work well. Reviewed-by: Damien Lespiau Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/rendercopy_gen9.c | 11 +++ 1 file changed, 11 insertions(+) diff --git

[Intel-gfx] [PATCH i-g-t 23/26] mediafill/skl: Follow the spec to add pipeline_select mask

From: Zhao Yakui Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/gen8_media.h | 3 +++ lib/media_fill_gen9.c | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/gen8_media.h b/lib/gen8_media.h index 1214cd1..d1df8b9 10064

[Intel-gfx] [PATCH i-g-t 17/26] assembler/skl: Redefine the cache agent type for some fixed functions

From: Zhao Yakui The different cache agent type is defined for SKL although it still uses the same function ID as the previous generations. Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- assembler/brw_defines.h | 7 +++ 1 file changed, 7 insertion

[Intel-gfx] [PATCH i-g-t 19/26] assembler/skl: Add more cache agent for write(...)

From: Zhao Yakui Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- assembler/gram.y | 40 ++-- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index 157ce79..9689352 1

[Intel-gfx] [PATCH i-g-t 20/26] assembler/skl: update the extdesc field for SEND instruction

From: Zhao Yakui The send instruction on gen9 uses the 32bit immediate instead of 6bit immediate for the extended message descriptors. And some bits of SEND instruction are defined as the extdesc field. Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau ---

[Intel-gfx] [PATCH i-g-t 24/26] mediafill/skl: Follow spec to configure FORCE_MEDIA_AWAKE in PIPELINE_SELECTION

From: Zhao Yakui The FORCE_MEDIA_AWAKE bit is added for the PIPELINE_SELECTION command and some instructions requires that the media enginee is awake. Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/gen8_media.h | 7 +++ lib/media_fill_gen

[Intel-gfx] [PATCH i-g-t 22/26] mediafill/skl: follow the spec to update STATE_BASE_ADDRESS command

From: Zhao Yakui Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/media_fill_gen9.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/lib/media_fill_gen9.c b/lib/media_fill_gen9.c index 98e2403..a067221 100644 --- a/lib/

[Intel-gfx] [PATCH i-g-t 25/26] mediafill/skl: Follow spec to configure media sampler DOP clock gating in PIPELINE_SELECTION

From: Zhao Yakui Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/gen8_media.h | 4 lib/media_fill_gen9.c | 4 2 files changed, 8 insertions(+) diff --git a/lib/gen8_media.h b/lib/gen8_media.h index f654215..15cd799 100644 --- a/lib/g

[Intel-gfx] [PATCH i-g-t 21/26] mediafill/skl: Start the gen9 media_fill from the gen8 version

From: Zhao Yakui Signed-off-by: Zhao Yakui Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/Makefile.sources | 1 + lib/media_fill.c | 16 +++ lib/media_fill.h | 7 + lib/media_fill_gen9.c | 378 ++ 4 files chang

[Intel-gfx] [PATCH i-g-t 26/26] lib/skl: Return the render copy and media fill functions

From: "Xiang, Haihao" Signed-off-by: Xiang, Haihao [Ben: Reordered if tree] Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/intel_batchbuffer.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index 95

[Intel-gfx] [PATCH i-g-t 18/26] assembler/skl: update read(...)

From: Zhao Yakui READ(...) is used for Render Target read and Media Block read. But there is no sampler cache agent on gen9. At the same time two message types don't share the same cache agent any more. So a parameter is needed for cache agent. The 2th parameter of read(...) is not used for gen6/

[Intel-gfx] [PATCH] drm/i915: Do not leak pages when freeing userptr objects

From: Tvrtko Ursulin sg_alloc_table_from_pages() can build us a table with coalesced ranges which means we need to iterate over pages and not sg table entries when releasing page references. Signed-off-by: Tvrtko Ursulin Cc: Chris Wilson Cc: "Barbalho, Rafael" --- drivers/gpu/drm/i915/i915_g

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

Jani Nikula writes: > On Fri, 26 Sep 2014, Mika Kuoppala wrote: >> Rodrigo Vivi writes: >> >>> This helps when including or removing cs workarounds. >>> Signed-off-by: Rodrigo Vivi >>> --- >>> drivers/gpu/drm/i915/intel_ringbuffer.c | 16 >>> 1 file changed, 12 insertions(+),

Re: [Intel-gfx] [PATCH] drm/i915: Do not leak pages when freeing userptr objects

> -Original Message- > From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com] > Sent: Friday, September 26, 2014 3:05 PM > To: Intel-gfx@lists.freedesktop.org > Cc: Ursulin, Tvrtko; Chris Wilson; Barbalho, Rafael > Subject: [PATCH] drm/i915: Do not leak pages when freeing userptr obje

[Intel-gfx] [QA 09/26 ww39] Testing report for `drm-intel-testing` (was: Updated -next)

Summary We covered the platform: BSW, Broadwell, Baytrail-M, Haswell, Ivybridge, SandyBridge, IronLake. We involved BSW first time. Basically HDMI/DP works, and eDP doesn't works for a regression issue. In this circle, 5 new bugs are filed. Bug 84320

Re: [Intel-gfx] [PATCH 84/89] drm/i915/skl: add turbo support

Damien Lespiau writes: > From: Jesse Barnes > > Per latest PM programming guide. > > v2: the wrong flavour of the function updating the ring frequency was > called, leading to dead locks (Tvrtko) > > Signed-off-by: Jesse Barnes > Signed-off-by: Damien Lespiau > --- > drivers/gpu/drm/i915/

Re: [Intel-gfx] [PATCH] drm/i915: Do not leak pages when freeing userptr objects

On Fri, Sep 26, 2014 at 03:05:22PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > sg_alloc_table_from_pages() can build us a table with coalesced ranges which > means we need to iterate over pages and not sg table entries when releasing > page references. > > Signed-off-by: Tvrtko Ursul

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

On Fri, Sep 26, 2014 at 05:16:57PM +0300, Mika Kuoppala wrote: > Jani Nikula writes: > > > On Fri, 26 Sep 2014, Mika Kuoppala wrote: > >> Rodrigo Vivi writes: > >> > >>> This helps when including or removing cs workarounds. > >>> Signed-off-by: Rodrigo Vivi > >>> --- > >>> drivers/gpu/drm/i91

Re: [Intel-gfx] [PATCH 85/89] drm/i915/skl: Retrieve the frequency limits

Damien Lespiau writes: > Signed-off-by: Damien Lespiau Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_pm.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 9e9377a..77e1d52 100644 > --- a/dri

Re: [Intel-gfx] [PATCH 87/89] drm/i915/skl: AUX irqs have moved

Damien Lespiau writes: > From: Jesse Barnes > > Use the new AUX port irq bits where needed. > > v2: Rebase on top of upstream changes > v3: Rebase on top of Oscar change to write IIR as soon as possible (Damien) > v4: Rebase on top of the for_each_pipe() change adding dev_priv as first > arg

Re: [Intel-gfx] [PATCH 89/89] drm/i915/skl: Disable contexts if execlists aren't enabled

Damien Lespiau writes: > We were hiting a BUG() in get_context_size() with execlist disabled. > > "legacy" contexts are not supported on gen9 so we don't have a gen9 > specific size to add in there. Instead, let's disable legacy contexts > altogether on gen9, whether we're booting with execlist e

Re: [Intel-gfx] [PATCH 89/89] drm/i915/skl: Disable contexts if execlists aren't enabled

On Fri, Sep 26, 2014 at 06:28:53PM +0300, Mika Kuoppala wrote: > Damien Lespiau writes: > > > We were hiting a BUG() in get_context_size() with execlist disabled. > > > > "legacy" contexts are not supported on gen9 so we don't have a gen9 > > specific size to add in there. Instead, let's disable

[Intel-gfx] [PATCH i-g-t] kms_cursor_crc: Remove two unused local variables

Signed-off-by: Damien Lespiau --- tests/kms_cursor_crc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c index 718699d..c348d7a 100644 --- a/tests/kms_cursor_crc.c +++ b/tests/kms_cursor_crc.c @@ -79,7 +79,6 @@ static void draw_cursor(cairo_t *

Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Compute port_clock for 27.027 pixel replicated modes

On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote: > From: Clint Taylor > > port_clock was being incorrectly computed and WRPLL was incorrectly > programmed for pixel doubled modes using a 27.027MHz pixel clock. > port_clock was set to 27.026 resulting in an output pixel

Re: [Intel-gfx] [PATCH v2] drm/i915: Audio N value computed for pixel doubled modes

On Thu, Sep 25, 2014 at 09:26:36AM -0700, clinton.a.tay...@intel.com wrote: > From: Clint Taylor > > HDMI audio clock config was incorrectly choosing the default for > pixel doubled interlaced modes. The table was missing pixel clock > values 13.500 (27.000) and 13.513 (27.027). Luckily the defau

Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Compute port_clock for 27.027 pixel replicated modes

On 09/26/2014 08:58 AM, Ville Syrjälä wrote: On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor port_clock was being incorrectly computed and WRPLL was incorrectly programmed for pixel doubled modes using a 27.027MHz pixel clock. port_clock was set t

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable pixel replicated modes on BDW and HSW.

On Thu, Sep 25, 2014 at 10:03:53AM -0700, clinton.a.tay...@intel.com wrote: > From: Clint Taylor > > Haswell and later silicon has added a new pixel replication register > to the pipe timings for each transcoder. Now in addition to the > DPLL_A_MD register for the pixel clock double, we also need

Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Compute port_clock for 27.027 pixel replicated modes

On 09/26/2014 08:58 AM, Ville Syrjälä wrote: On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor port_clock was being incorrectly computed and WRPLL was incorrectly programmed for pixel doubled modes using a 27.027MHz pixel clock. port_clock was set t

[Intel-gfx] [PATCH] drm/edid: Add missing interlaced flag to 576i@100 modes.

From: Clint Taylor CEA VICs 44 and 45 were missing DRM_MODE_FLAG_INTERLACE. Signed-off-by: Clint Taylor --- drivers/gpu/drm/drm_edid.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 1bdbfd0..3bf9991 10064

Re: [Intel-gfx] [PATCH] drm/i915: intel_backlight scale() math WA v2

> -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Joe Konno > Sent: Wednesday, September 24, 2014 8:55 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH] drm/i915: intel_backlight scale() math WA v2 > > From: Joe Ko

[Intel-gfx] [PATCH] drm/i915: Organize HSW and BDW Forcewake MT Ack.

0x130040 is actually a LCPLL_CTL and never was a Forcewake MT Ack. The fixed value was introduced but the wrong one was never removed. So let's clean the code and definitions a bit. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 3 +-- drivers/gpu/drm/i915/intel_uncore.c

Re: [Intel-gfx] [PATCH] drm/edid: Add missing interlaced flag to 576i@100 modes.

On Fri, Sep 26, 2014 at 09:55:24AM -0700, clinton.a.tay...@intel.com wrote: > From: Clint Taylor > > CEA VICs 44 and 45 were missing DRM_MODE_FLAG_INTERLACE. > > Signed-off-by: Clint Taylor Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/drm_edid.c |4 ++-- > 1 file changed, 2 insert

Re: [Intel-gfx] [PATCH] drm/i915: Organize HSW and BDW Forcewake MT Ack.

On Fri, Sep 26, 2014 at 01:15:26PM -0400, Rodrigo Vivi wrote: > 0x130040 is actually a LCPLL_CTL and never was a Forcewake MT Ack. > The fixed value was introduced but the wrong one was never removed. > So let's clean the code and definitions a bit. NAK. 0x130040 is the forcewake MT ack on IVB. >

Re: [Intel-gfx] [PATCH] drm/i915: Organize HSW and BDW Forcewake MT Ack.

oh true. Please just ignore it... On Fri, Sep 26, 2014 at 11:12 AM, Ville Syrjälä < ville.syrj...@linux.intel.com> wrote: > On Fri, Sep 26, 2014 at 01:15:26PM -0400, Rodrigo Vivi wrote: > > 0x130040 is actually a LCPLL_CTL and never was a Forcewake MT Ack. > > The fixed value was introduced but t

Re: [Intel-gfx] [PATCH 3/5] drm/i915/bdw: WaProgramL3SqcReg1Default

On Fri, Sep 26, 2014 at 5:03 AM, Mika Kuoppala wrote: > > Rodrigo Vivi writes: > > > Program the default initial value of the L3SqcReg1 on BDW for performance > > > > Signed-off-by: Rodrigo Vivi > > --- > > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > >

Re: [Intel-gfx] [PATCH 3/5] drm/i915/bdw: WaProgramL3SqcReg1Default

On Fri, Sep 26, 2014 at 03:03:19PM +0300, Mika Kuoppala wrote: > Rodrigo Vivi writes: > > > Program the default initial value of the L3SqcReg1 on BDW for performance > > > > Signed-off-by: Rodrigo Vivi > > --- > > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > > drivers/gpu/drm/i915/intel_pm.c | 3

Re: [Intel-gfx] [PATCH] ACPI / i915: Update the condition to ignore firmware backlight change request

On Friday, September 26, 2014 10:30:08 AM Aaron Lu wrote: > Some of the Thinkpads' firmware will issue a backlight change request > through i915 operation region unconditionally on AC plug/unplug, the > backlight level used is arbitrary and thus should be ignored. This is > handled by commit 0b9f7d

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable pixel replicated modes on BDW and HSW.

On 09/26/2014 09:38 AM, Ville Syrjälä wrote: On Thu, Sep 25, 2014 at 10:03:53AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition to the DPLL_A_MD register fo