Re: [Intel-gfx] [PATCH] drm/i915/cfl: Remove alpha support protection.

On Thu, 2017-09-07 at 16:06 -0700, Rodrigo Vivi wrote: > We now have Coffee Lake on our CI systems. > > Coffee Lake is at this point in same stage as Kaby Lake. > > And it seems that we don't have any risk of bad blank > screens or anything like that. So let's remove the protection. >

Re: [Intel-gfx] [PATCH 11/11] drm/i915/psr: Add enable_source vfunc.

On Thu, 2017-09-07 at 16:00 -0700, Rodrigo Vivi wrote: > Continue on VLV PSR split with vfunc, let's also create one > for enabling source. > > Also since we are touching *_enable_source functions let's > fix a comment with wrong name for vlv's one. > > v2: Fix typo on commit message (DK). > >

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cfl: Remove alpha support protection.

== Series Details == Series: drm/i915/cfl: Remove alpha support protection. URL : https://patchwork.freedesktop.org/series/29981/ State : success == Summary == Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 fdo#99912

[Intel-gfx] ✗ Fi.CI.IGT: failure for PSR clean-up and vfuncs for clear split between different psr implementations

== Series Details == Series: PSR clean-up and vfuncs for clear split between different psr implementations URL : https://patchwork.freedesktop.org/series/29980/ State : failure == Summary == Test kms_flip: Subgroup wf_vblank-vs-dpms-interruptible: pass ->

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cfl: Remove alpha support protection.

== Series Details == Series: drm/i915/cfl: Remove alpha support protection. URL : https://patchwork.freedesktop.org/series/29981/ State : success == Summary == Series 29981v1 drm/i915/cfl: Remove alpha support protection.

[Intel-gfx] ✓ Fi.CI.BAT: success for PSR clean-up and vfuncs for clear split between different psr implementations

== Series Details == Series: PSR clean-up and vfuncs for clear split between different psr implementations URL : https://patchwork.freedesktop.org/series/29980/ State : success == Summary == Series 29980v1 PSR clean-up and vfuncs for clear split between different psr implementations

[Intel-gfx] [PATCH] drm/i915/cfl: Remove alpha support protection.

We now have Coffee Lake on our CI systems. Coffee Lake is at this point in same stage as Kaby Lake. And it seems that we don't have any risk of bad blank screens or anything like that. So let's remove the protection. Cc: Daniel Vetter Cc: Dhinakaran Pandiyan

[Intel-gfx] ✓ Fi.CI.IGT: success for igt/tools_test: Remove dmesg subtest

== Series Details == Series: igt/tools_test: Remove dmesg subtest URL : https://patchwork.freedesktop.org/series/29970/ State : success == Summary == Test kms_atomic_transition: Subgroup plane-use-after-nonblocking-unbind: incomplete -> FAIL (shard-hsw)

[Intel-gfx] [PATCH 03/11] drm/i915/psr: hsw_psr_activate.

On HSW+ the real activate of PSR is decided by the source after certain amount of configured idle frames. However for the driver perspective where we track psr.active variable this function here is the actual activate one. So let's rename it before moving to vfunc with that. v2: Fix typo on

[Intel-gfx] [PATCH 11/11] drm/i915/psr: Add enable_source vfunc.

Continue on VLV PSR split with vfunc, let's also create one for enabling source. Also since we are touching *_enable_source functions let's fix a comment with wrong name for vlv's one. v2: Fix typo on commit message (DK). Cc: Daniel Vetter Cc: Dhinakaran Pandiyan

[Intel-gfx] [PATCH 00/11] PSR clean-up and vfuncs for clear split between different psr implementations

The ultimate goal is to be able to use more HW tracking on the PSR implementation where that is possible, i.e. all other platforms but VLV/CHV. But before doing that, let's organize PSR a bit more so it will be really clear the platforms where HW tracking is possible. This series is not

[Intel-gfx] [PATCH 05/11] drm/i915/psr: Unify VSC setup functions.

VSC package is decided per eDP spec for psr1 or psr2, and not per platform, so let's unify it and kill "skl" func. v2: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb crtc_state to PSR enable/disable") Cc: Dhinakaran Pandiyan Cc: Vathsala Nagaraju

[Intel-gfx] [PATCH 06/11] drm/i915/psr: Re-create a hsw_psr_enable_source.

This sequence is part of enable source anyways, but they only need to be executed once and not on every activation, So let's re-create hsw_enable_source. v2: Avoid changing order here to avoid changing behaviour as suggested by Jani. v3: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb

[Intel-gfx] [PATCH 02/11] drm/i915/psr: vfunc for disabling source.

VLV/CHV has a total different PSR implementation than the other platforms, so let's start moving that to vfuncs. Let's start with disable_src one. v2: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb crtc_state to PSR enable/disable") Cc: Daniel Vetter Cc:

[Intel-gfx] [PATCH 09/11] drm/i915/psr: Add setup VSC vfunc.

Continue on VLV PSR split with vfunc, let's also create one for setting up VSC. v2: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb crtc_state to PSR enable/disable") Cc: Daniel Vetter Cc: Dhinakaran Pandiyan Cc: Vathsala

[Intel-gfx] [PATCH 01/11] drm/i915/psr: Avoid any PSR stuff on platforms without support.

We really don't want to setup vfuncs and lock mutexes on platforms that has no support to PSR. Also we know what platforms they are so let's do it quietly. Cc: Daniel Vetter Cc: Dhinakaran Pandiyan Cc: Vathsala Nagaraju

[Intel-gfx] [PATCH 10/11] drm/i915/psr: Add enable_sink vfunc.

Continue on VLV PSR split with vfunc, let's also create one for enabling sink. v2: Fix typo on commit message (DK). Cc: Daniel Vetter Cc: Dhinakaran Pandiyan Cc: Vathsala Nagaraju Signed-off-by: Rodrigo Vivi

[Intel-gfx] [PATCH 04/11] drm/i915/psr: Add activate vfunc.

Continue on VLV PSR split with vfunc, let's move activate function there. Cc: Daniel Vetter Cc: Dhinakaran Pandiyan Cc: Vathsala Nagaraju Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH 07/11] drm/i915/psr: Move hsw_enable_source after enabling sink.

No functional change is expected here since at this point PSR is not allowed to go to any active state. In other words, not really enabled. However let's do in a separated patch so it gets clear on what is change and specially it can helps on bisect case if we figure something has caused changes

[Intel-gfx] [PATCH 08/11] drm/i915/psr: Re-org Activate after enable

Let's move the activation calls together after enable is done. No real functional change should be expected here. Just an attempt to get it clear when we are really activating PSR after enabling it. v2: Add braces on if/else because commit message there is too long as suggested by Jani. v3:

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC Load time to debugfs

Quoting Tvrtko Ursulin (2017-09-07 09:49:02) > > On 07/09/2017 01:37, Anusha Srivatsa wrote: > > Calculate the time that GuC takes to load. > > This information could be very useful in > > determining if GuC is taking unreasonably long time > > to load in a certain platforms. > > Do we need this

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/8] drm/i915: Try harder to finish the idle-worker

Quoting Chris Wilson (2017-09-04 13:02:27) > Quoting Patchwork (2017-09-03 15:17:57) > > == Series Details == > > > > Series: series starting with [1/8] drm/i915: Try harder to finish the > > idle-worker > > URL : https://patchwork.freedesktop.org/series/29764/ > > State : success > > > > ==

Re: [Intel-gfx] [PATCH 4/4] drm/i915/selftests: Introduce live tests of private PAT management

Quoting Zhi Wang (2017-09-05 20:58:27) > Introduce two live tests of private PAT managment: > > igt_ppat_init - This test is to check if all the PPAT configuration is > written into HW. > > igt_ppat_get - This test performs several sub-tests on intel_ppat_get() > and intel_ppat_put(). > > The

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Do not allocate unused PPAT entries

Quoting Zhi Wang (2017-09-05 20:58:26) > static void gen6_gmch_remove(struct i915_address_space *vm) > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h > b/drivers/gpu/drm/i915/i915_gem_gtt.h > index e10ca89..575da15 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h > +++

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Introduce private PAT management

Quoting Zhi Wang (2017-09-05 20:58:25) > The private PAT management is to support PPAT entry manipulation. Two > APIs are introduced for dynamically managing PPAT entries: intel_ppat_get > and intel_ppat_put. > > intel_ppat_get will search for an existing PPAT entry which perfectly > matches the

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Factor out setup_private_pat()

Quoting Zhi Wang (2017-09-05 20:58:24) > Factor out setup_private_pat() for introducing the following patches. > > Cc: Ben Widawsky > Cc: Rodrigo Vivi > Cc: Chris Wilson > Cc: Joonas Lahtinen

Re: [Intel-gfx] [git pull] drm/i915 fixes for v4.14-rc1

On 8 September 2017 at 06:03, Rodrigo Vivi wrote: > Hi Linus, > > Since Dave is on paternity leave we are sending drm/i915 fixes for > v4.14-rc1 directly to you as he had asked us to do. > > The most critical ones are the GPU reset fix for gen2-4 and GVT fix > for a

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

Quoting Patchwork (2017-09-07 16:58:53) > == Series Details == > > Series: series starting with [1/6] drm/i915: Transform > WaInPlaceDecompressionHang into a simple reg write > URL : https://patchwork.freedesktop.org/series/29957/ > State : success > > == Summary == > > Series 29957v1 series

Re: [Intel-gfx] [PATCH v2] drm/i915: Apply the GTT write flush for all !llc machines

Quoting Ville Syrjälä (2017-09-07 19:50:13) > On Thu, Sep 07, 2017 at 07:45:20PM +0100, Chris Wilson wrote: > > We also see the delayed GTT write issue on i915g/i915gm, so let's > > presume that it is a universal problem for all !llc machines, and that we > > just haven't yet noticed on g33, gen4

Re: [Intel-gfx] [PATCH 11/12] drm/i915/psr: Add enable_source vfunc.

On Wed, 2017-07-12 at 12:20 -0700, Rodrigo Vivi wrote: > Continue on VPV PSR split with vfunc, let's also create one Typo: s/VPV/VLV > for enabling source. > > Also since we are touching *_enable_source functions let's > fix a comment with wrong name for vlv's one. > > Cc: Daniel Vetter

Re: [Intel-gfx] [PATCH 10/12] drm/i915/psr: Add enable_sink vfunc.

On Wed, 2017-07-12 at 12:20 -0700, Rodrigo Vivi wrote: > Continue on VPV PSR split with vfunc, let's also create one Typo s/VPV/VLV > for enabling sink. > > Cc: Daniel Vetter > Cc: Dhinakaran Pandiyan > Cc: Jim Bride

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

== Series Details == Series: series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write URL : https://patchwork.freedesktop.org/series/29957/ State : success == Summary == Test kms_setmode: Subgroup basic: pass -> FAIL

[Intel-gfx] ✗ Fi.CI.BAT: failure for lib/igt_dummyload: Use -1 for all engines

== Series Details == Series: lib/igt_dummyload: Use -1 for all engines URL : https://patchwork.freedesktop.org/series/29973/ State : failure == Summary == IGT patchset tested on top of latest successful build e49c3feda5e379fbba58731b74beccb8f77a9b88 igt/gem_exec_suspend: Try to suspend with

Re: [Intel-gfx] [PATCH 00/12] PSR clean-up, new vfuncs and more use of HW tracking.

Sorry for the delayed review, this series needs to rebased as we are passing crtc_state to a lot of these functions now. I don't see any issues based on my cursory review. On Wed, 2017-07-12 at 12:20 -0700, Rodrigo Vivi wrote: > Most of patches on this series is only a clean up with > no

Re: [Intel-gfx] [PATCH 04/12] drm/i915/psr: hsw_psr_activate.

On Wed, 2017-07-12 at 12:20 -0700, Rodrigo Vivi wrote: > Oh HSW the real activate of PSR is decided by the source Typos: On HSW+ > after certain amount of configured idle frames. > > However for the driver perspective where we track psr.active > variable this function here is the actual

[Intel-gfx] [git pull] drm/i915 fixes for v4.14-rc1

Hi Linus, Since Dave is on paternity leave we are sending drm/i915 fixes for v4.14-rc1 directly to you as he had asked us to do. The most critical ones are the GPU reset fix for gen2-4 and GVT fix for a regression that is blocking gvt init to work on your tree. The rest is general fixes for

[Intel-gfx] [PATCH igt] lib/igt_dummyload: Use -1 for all engines

Random change when it copied broke the interface I was using. Signed-off-by: Chris Wilson --- lib/igt_dummyload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c index c3516b96..d19b4e5e 100644 ---

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/tools_test: Remove dmesg subtest

== Series Details == Series: igt/tools_test: Remove dmesg subtest URL : https://patchwork.freedesktop.org/series/29970/ State : success == Summary == IGT patchset tested on top of latest successful build e49c3feda5e379fbba58731b74beccb8f77a9b88 igt/gem_exec_suspend: Try to suspend with a

Re: [Intel-gfx] [PATCH igt] igt/tools_test: Remove dmesg subtest

Quoting Chris Wilson (2017-09-07 19:29:25) > It's a silly test. If fails if there is an *ERROR* in the dmesg ringbuf, > so it neither is testing that errors are generated as expected, and as a > pre-check it can only see what's at the end of the dmesg and may miss > earlier faults. As a test it

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Apply the GTT write flush for all !llc machines (rev2)

== Series Details == Series: drm/i915: Apply the GTT write flush for all !llc machines (rev2) URL : https://patchwork.freedesktop.org/series/29953/ State : failure == Summary == Series 29953v2 drm/i915: Apply the GTT write flush for all !llc machines

Re: [Intel-gfx] [PATCH] i915: Fix obj size vs. alignment for drm_pci_alloc()

On Thu, Sep 07, 2017 at 05:53:30PM +0300, Ville Syrjälä wrote: > On Thu, Sep 07, 2017 at 03:43:26PM +0100, Chris Wilson wrote: > > Quoting ville.syrj...@linux.intel.com (2017-09-07 15:32:03) > > > From: Ville Syrjälä > > > > > > drm_pci_alloc() refuses to cooperate

Re: [Intel-gfx] [PATCH v2] drm/dp/mst: Sideband message transaction to power up/down nodes

On Thu, 2017-09-07 at 14:04 -0400, Lyude Paul wrote: > Looks good to me. > > Reviewed-by: Lyude Paul > Thanks for the review. -DK > On Wed, 2017-09-06 at 17:14 -0700, Dhinakaran Pandiyan wrote: > > The POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions > >

Re: [Intel-gfx] [PATCH v2] drm/i915: Apply the GTT write flush for all !llc machines

On Thu, Sep 07, 2017 at 07:45:20PM +0100, Chris Wilson wrote: > We also see the delayed GTT write issue on i915g/i915gm, so let's > presume that it is a universal problem for all !llc machines, and that we > just haven't yet noticed on g33, gen4 and gen5 machines. > > v2: Use a register that

Re: [Intel-gfx] [PATCH] drm/i915: Apply the GTT write flush for all !llc machines

On Thu, Sep 07, 2017 at 07:35:22PM +0100, Chris Wilson wrote: > Quoting Ville Syrjälä (2017-09-07 19:23:27) > > On Thu, Sep 07, 2017 at 03:31:08PM +0100, Chris Wilson wrote: > > > We also see the delayed GTT write issue on i915g/i915gm, so let's > > > presume that it is a universal problem for all

[Intel-gfx] [PATCH v2] drm/i915: Apply the GTT write flush for all !llc machines

We also see the delayed GTT write issue on i915g/i915gm, so let's presume that it is a universal problem for all !llc machines, and that we just haven't yet noticed on g33, gen4 and gen5 machines. v2: Use a register that exists on all platforms Testcase: igt/gem_mmap_gtt/coherency # i915gm

Re: [Intel-gfx] [PATCH i-g-t] lib/sysfs: Fix fbcon rebind

Quoting ville.syrj...@linux.intel.com (2017-09-06 14:04:01) > From: Ville Syrjälä > > "echo 1 > vtconN/bind" doesn't actually do anything. Looks like the only > way to rebind fbcon is to unbind the current console. > > I suppose the failure to rebind might be a

Re: [Intel-gfx] [PATCH] drm/i915: Apply the GTT write flush for all !llc machines

Quoting Ville Syrjälä (2017-09-07 19:23:27) > On Thu, Sep 07, 2017 at 03:31:08PM +0100, Chris Wilson wrote: > > We also see the delayed GTT write issue on i915g/i915gm, so let's > > presume that it is a universal problem for all llc machines, and that we > > just haven't yet noticed on g33, gen4

[Intel-gfx] [PATCH igt] igt/tools_test: Remove dmesg subtest

It's a silly test. If fails if there is an *ERROR* in the dmesg ringbuf, so it neither is testing that errors are generated as expected, and as a pre-check it can only see what's at the end of the dmesg and may miss earlier faults. As a test it just randomly fails; worse than useless.

Re: [Intel-gfx] [PATCH i-g-t] pm_rps: [RFC] RPS tests documentation update

On 9/7/2017 5:15 AM, Katarzyna Dec wrote: Added comments in tricky places for better feature understanding. Added IGT_TEST_DESCRIPTION and short description for non-obvious subtests. Changed name of 'magic' checkit() function to something meaningfull. Changed junk struct and stuff array names.

Re: [Intel-gfx] [PATCH] drm/i915: Apply the GTT write flush for all !llc machines

On Thu, Sep 07, 2017 at 03:31:08PM +0100, Chris Wilson wrote: > We also see the delayed GTT write issue on i915g/i915gm, so let's > presume that it is a universal problem for all llc machines, and that we > just haven't yet noticed on g33, gen4 and gen5 machines. > > Testcase:

Re: [Intel-gfx] [PATCH igt] igt/gem_evict_(alignment, everything): Limit to low 4G

Quoting Chris Wilson (2017-08-15 11:34:30) > These tests do not tell the kernel they can use the upper 48bits of > aperture space, and cause eviction on the low 4G just as effectively > exercising the evict code. > > Signed-off-by: Chris Wilson * Crickets. > --- >

Re: [Intel-gfx] [PATCH igt] igt/gem_fence_thresh: Use streaming reads for verify

Quoting Chris Wilson (2017-08-23 13:55:55) > At the moment, the verify tests use an extremely brutal write-read of > every dword, degrading performance to UC. If we break those up into > cachelines, we can do a wcb write/read at a time instead, roughly 8x > faster. We lose the accuracy of the

Re: [Intel-gfx] [PATCH v2] drm/dp/mst: Sideband message transaction to power up/down nodes

Looks good to me. Reviewed-by: Lyude Paul On Wed, 2017-09-06 at 17:14 -0700, Dhinakaran Pandiyan wrote: > The POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions > allow > the source to reqest any node in a mst path or a whole path to be > powered down or up. This

Re: [Intel-gfx] [PATCH 4/4] drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9

On Fri, Sep 01, 2017 at 11:02:12AM +0530, Sagar Arun Kamble wrote: > With GuC v9, new type of Default/critical logging in GuC to enable > capturing minimal important logs in production systems efficiently. > This patch enables this logging in GuC by default always. It should > be noted that

[Intel-gfx] ✓ Fi.CI.IGT: success for i915: Fix obj size vs. alignment for drm_pci_alloc()

== Series Details == Series: i915: Fix obj size vs. alignment for drm_pci_alloc() URL : https://patchwork.freedesktop.org/series/29954/ State : success == Summary == Test kms_atomic_transition: Subgroup plane-use-after-nonblocking-unbind: incomplete -> FAIL

Re: [Intel-gfx] [PATCH 3/4] drm/i915/guc: Fix GuC HW/SW state cleanup in unload path

On Fri, Sep 01, 2017 at 11:02:11AM +0530, Sagar Arun Kamble wrote: > Teardown of GuC HW/SW state was not properly done in unload path. > During unload, we can rely on intel_guc_reset_prepare being done > as part of i915_gem_suspend for disabling GuC interfaces. > We will have to disable GuC

Re: [Intel-gfx] [PATCH 2/4] drm/i915/guc: Fix GuC interaction in reset/suspend scenarios

On Fri, Sep 01, 2017 at 11:02:10AM +0530, Sagar Arun Kamble wrote: > Tearing down of guc_ggtt_invalidate/guc_interrupts/guc_communication > setup should happen towards end of reset/suspend as these are > setup back again during recovery/resume. > > Prepared helpers intel_guc_pause and

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Separate GuC/HuC specific functionality from intel_uc

On Fri, Sep 01, 2017 at 11:02:09AM +0530, Sagar Arun Kamble wrote: > Removed unnecessary intel_uc.h includes as it is present in i915_drv.h. > Created intel_guc.c and intel_guc.h for placing GuC specific code. > Created intel_huc.h to refer to HuC specific functions. > > v2: Prepared

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC Load time to debugfs

>-Original Message- >From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com] >Sent: Thursday, September 7, 2017 1:49 AM >To: Srivatsa, Anusha ; intel- >g...@lists.freedesktop.org >Cc: Sundaresan, Sujaritha >Subject: Re:

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC Load time to debugfs

>-Original Message- >From: Wajdeczko, Michal >Sent: Thursday, September 7, 2017 3:23 AM >To: Tvrtko Ursulin >Cc: Srivatsa, Anusha ; intel- >g...@lists.freedesktop.org; Sundaresan, Sujaritha >

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Disable mmio debugging during user access (rev2)

Quoting Patchwork (2017-09-07 17:52:37) > == Series Details == > > Series: drm/i915: Disable mmio debugging during user access (rev2) > URL : https://patchwork.freedesktop.org/series/29935/ > State : success > > == Summary == > > Test kms_setmode: > Subgroup basic: >

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Disable mmio debugging during user access (rev2)

== Series Details == Series: drm/i915: Disable mmio debugging during user access (rev2) URL : https://patchwork.freedesktop.org/series/29935/ State : success == Summary == Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 Test perf:

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/5] Fix compiler warnings about printf() arguments

== Series Details == Series: series starting with [1/5] Fix compiler warnings about printf() arguments URL : https://patchwork.freedesktop.org/series/29961/ State : warning == Summary == IGT patchset tested on top of latest successful build 4a1c8daff2005e2cbfe980d63bc0a0fb09cb017d

Re: [Intel-gfx] [PATCH i-g-t 5/5] tests/kms_properties: Require atomic for the atomic invalid props test

Quoting ville.syrj...@linux.intel.com (2017-09-07 17:11:20) > From: Ville Syrjälä > > The invalid props test forgot to check for atomic. Add the required > check. > > Signed-off-by: Ville Syrjälä Series is Reviewed-by: Chris Wilson

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Separate GuC/HuC specific functionality from intel_uc

On 9/7/2017 5:54 PM, Michał Winiarski wrote: On Fri, Sep 01, 2017 at 11:02:09AM +0530, Sagar Arun Kamble wrote: Removed unnecessary intel_uc.h includes as it is present in i915_drv.h. Created intel_guc.c and intel_guc.h for placing GuC specific code. Created intel_huc.h to refer to HuC

[Intel-gfx] [PATCH i-g-t 4/5] tests/kms_draw_crc: Skip mmap_wc tests if the platforms doesn't support mmap_wc

From: Ville Syrjälä Signed-off-by: Ville Syrjälä --- tests/kms_draw_crc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/kms_draw_crc.c b/tests/kms_draw_crc.c index 906d89f9b77d..260950c76e00 100644 ---

[Intel-gfx] [PATCH i-g-t 2/5] lib/kms: Fix the connector name strings to match what the kernel uses

From: Ville Syrjälä We depend on kmstest_connector_type_str() matching the kernel. Fix up the cases where we differ currently. Also add the missing DPI "connector" type. Signed-off-by: Ville Syrjälä --- lib/igt_aux.c | 11

[Intel-gfx] [PATCH i-g-t 3/5] lib/kms: Skip rather than fail when a suitable plane can't be found

From: Ville Syrjälä If the system doesn't have the plane the test wants, let's skip the test rather than fail it. Signed-off-by: Ville Syrjälä --- lib/igt_kms.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff

[Intel-gfx] [PATCH i-g-t 5/5] tests/kms_properties: Require atomic for the atomic invalid props test

From: Ville Syrjälä The invalid props test forgot to check for atomic. Add the required check. Signed-off-by: Ville Syrjälä --- tests/kms_properties.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/kms_properties.c

[Intel-gfx] [PATCH i-g-t 1/5] Fix compiler warnings about printf() arguments

From: Ville Syrjälä gem_spin_batch.c:51:13: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘long unsigned int’ [-Wformat=] intel_opregion_decode.c:313:9: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but

Re: [Intel-gfx] [PATCH v2] drm/i915: Disable mmio debugging during user access

Quoting Michal Wajdeczko (2017-09-07 16:55:39) > On Thu, Sep 07, 2017 at 02:44:41PM +0100, Chris Wilson wrote: > > If the user bypasses i915 and accesses mmio directly, that easily > > confuses our automatic mmio debugging (any error we then detect is > > likely to be as a result of the user).

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Factor out setup_private_pat()

Ping. -Original Message- From: Wang, Zhi A Sent: Tuesday, September 5, 2017 10:58 PM To: intel-gfx@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org Cc: joonas.lahti...@linux.intel.com; ch...@chris-wilson.co.uk; zhen...@linux.intel.com; Wang, Zhi A ;

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

== Series Details == Series: series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write URL : https://patchwork.freedesktop.org/series/29957/ State : success == Summary == Series 29957v1 series starting with [1/6] drm/i915: Transform

Re: [Intel-gfx] [PATCH v2] drm/i915: Disable mmio debugging during user access

On Thu, Sep 07, 2017 at 02:44:41PM +0100, Chris Wilson wrote: > If the user bypasses i915 and accesses mmio directly, that easily > confuses our automatic mmio debugging (any error we then detect is > likely to be as a result of the user). Since we expect userspace to open >

[Intel-gfx] ✓ Fi.CI.IGT: success for pm_rps: [RFC] RPS tests documentation update

== Series Details == Series: pm_rps: [RFC] RPS tests documentation update URL : https://patchwork.freedesktop.org/series/29947/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 Test kms_atomic_transition:

Re: [Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

On 09/07/2017 02:30 AM, Mika Kuoppala wrote: Oscar Mateo writes: Hey Mika, Regarding this patch: is there a consensus on where is the most appropriate place to apply workarounds? My understanding is that per-context workarounds (WAS_SET_BIT, etc...) go in

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

On 09/07/2017 04:03 AM, Michał Winiarski wrote: On Wed, Sep 06, 2017 at 05:15:49PM -0700, Oscar Mateo wrote: Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing it on every context creation is overkill (and wrong). v2: Missing end parenthesis Though there was a

[Intel-gfx] [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort into a simple reg write

GAMT_CHKN_BIT_REG does not live in the context. Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi Signed-off-by: Oscar Mateo Reviewed-by: Michał Winiarski ---

[Intel-gfx] [PATCH 4/6] drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write

GEN7_UCGCTL4 does not live in the context. v2: Missing parenthesis Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi Signed-off-by: Oscar Mateo Reviewed-by: Michał Winiarski

[Intel-gfx] [PATCH 3/6] drm/i915: WaPushConstantDereferenceHoldDisable needs to modify a masked register

So do it correctly. Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi Signed-off-by: Oscar Mateo Reviewed-by: Michał Winiarski ---

[Intel-gfx] [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing it on every context creation is overkill (and wrong). v2: Missing end parenthesis Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi

[Intel-gfx] [PATCH 6/6] drm/i915: Transform WaDisablePooledEuLoadBalancingFix into a simple register write

FF_SLICE_CS_CHICKEN2 does not belong to the context image. Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi Signed-off-by: Oscar Mateo Reviewed-by: Michał Winiarski

[Intel-gfx] [PATCH 5/6] drm/i915: Transform WaDisableDynamicCreditSharing into a simple register write

GAMT_CHKN_BIT_REG does not live in the context image. Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi Signed-off-by: Oscar Mateo Reviewed-by: Michał Winiarski ---

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/prime_vgem: Split out the fine-grain coherency check

== Series Details == Series: igt/prime_vgem: Split out the fine-grain coherency check URL : https://patchwork.freedesktop.org/series/29952/ State : success == Summary == IGT patchset tested on top of latest successful build 4a1c8daff2005e2cbfe980d63bc0a0fb09cb017d igt/gem_ringfill: Prime

Re: [Intel-gfx] [PATCH 0/8] Fixed16.16 wrapper cleanup & wm optimization

Op 17-08-17 om 17:16 schreef Mahesh Kumar: > Hi, > > My bad, I forgot to modify cover-letter before sending series to intel-gfx. > > yes this is for upstream consideration. Thanks, applied. I changed the enableddisabled in the debugfs patch to yesno, so if you want to write to it you can use yes

[Intel-gfx] ✓ Fi.CI.IGT: success for pm_rps: [RFC] RPS tests documentation update

== Series Details == Series: pm_rps: [RFC] RPS tests documentation update URL : https://patchwork.freedesktop.org/series/29947/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 Test pm_lpsp: Subgroup

Re: [Intel-gfx] [PATCH i-g-t v2] kms_rotation_crc: 90 degree flip test is not a stress test

On Thu, Sep 07, 2017 at 03:20:19PM +0100, Tvrtko Ursulin wrote: > > Hi, > > On 07/09/2017 15:13, Katarzyna Dec wrote: > > On Mon, Sep 04, 2017 at 03:27:26PM +0100, Tvrtko Ursulin wrote: > > > > > > On 07/08/2017 16:53, Daniel Vetter wrote: > > > > On Fri, Aug 04, 2017 at 09:43:41AM +0100,

[Intel-gfx] ✓ Fi.CI.BAT: success for i915: Fix obj size vs. alignment for drm_pci_alloc()

== Series Details == Series: i915: Fix obj size vs. alignment for drm_pci_alloc() URL : https://patchwork.freedesktop.org/series/29954/ State : success == Summary == Series 29954v1 i915: Fix obj size vs. alignment for drm_pci_alloc()

Re: [Intel-gfx] [PATCH] i915: Fix obj size vs. alignment for drm_pci_alloc()

On Thu, Sep 07, 2017 at 03:43:26PM +0100, Chris Wilson wrote: > Quoting ville.syrj...@linux.intel.com (2017-09-07 15:32:03) > > From: Ville Syrjälä > > > > drm_pci_alloc() refuses to cooperate if the passed alignment exceeds the > > object size. So round up the obj

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Apply the GTT write flush for all !llc machines

== Series Details == Series: drm/i915: Apply the GTT write flush for all !llc machines URL : https://patchwork.freedesktop.org/series/29953/ State : warning == Summary == Series 29953v1 drm/i915: Apply the GTT write flush for all !llc machines

Re: [Intel-gfx] [PATCH] i915: Fix obj size vs. alignment for drm_pci_alloc()

Quoting ville.syrj...@linux.intel.com (2017-09-07 15:32:03) > From: Ville Syrjälä > > drm_pci_alloc() refuses to cooperate if the passed alignment exceeds the > object size. So round up the obj size to the next power of two as well > to make this actually work.

[Intel-gfx] [PATCH] i915: Fix obj size vs. alignment for drm_pci_alloc()

From: Ville Syrjälä drm_pci_alloc() refuses to cooperate if the passed alignment exceeds the object size. So round up the obj size to the next power of two as well to make this actually work. Obviously things work just fine as long as the size was a power of two

[Intel-gfx] [PATCH] drm/i915: Apply the GTT write flush for all !llc machines

We also see the delayed GTT write issue on i915g/i915gm, so let's presume that it is a universal problem for all llc machines, and that we just haven't yet noticed on g33, gen4 and gen5 machines. Testcase: igt/gem_mmap_gtt/coherency # i915gm References:

[Intel-gfx] [PATCH igt] igt/prime_vgem: Split out the fine-grain coherency check

We don't expect every machine to be able to pass the WC/GTT coherency check, see kernel commit 3b5724d702ef24ee41ca008a1fab1cf94f3d31b5 Author: Chris Wilson Date: Thu Aug 18 17:16:49 2016 +0100 drm/i915: Wait for writes through the GTT to land before reading back

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915 perf support for command stream based OA, GPU and workload metrics capture (rev3)

== Series Details == Series: i915 perf support for command stream based OA, GPU and workload metrics capture (rev3) URL : https://patchwork.freedesktop.org/series/28104/ State : failure == Summary == Test perf: Subgroup short-reads: pass -> FAIL

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable mmio debugging during user access (rev2)

== Series Details == Series: drm/i915: Disable mmio debugging during user access (rev2) URL : https://patchwork.freedesktop.org/series/29935/ State : success == Summary == Series 29935v2 drm/i915: Disable mmio debugging during user access

[Intel-gfx] [PATCH v2] drm/i915: Disable mmio debugging during user access

If the user bypasses i915 and accesses mmio directly, that easily confuses our automatic mmio debugging (any error we then detect is likely to be as a result of the user). Since we expect userspace to open debugfs/i915_forcewake_user if i915.ko is loaded and they want mmio access, that makes the

Re: [Intel-gfx] [PATCH i-g-t] pm_rps: [RFC] RPS tests documentation update

On Thu, Sep 07, 2017 at 02:15:14PM +0200, Katarzyna Dec wrote: > Added comments in tricky places for better feature understanding. > Added IGT_TEST_DESCRIPTION and short description for non-obvious > subtests. > Changed name of 'magic' checkit() function to something meaningfull. > Changed junk

Re: [Intel-gfx] [PATCH] drm/i915: Disable mmio debugging during user access

Quoting Mika Kuoppala (2017-09-07 14:22:21) > Chris Wilson writes: > > > If the user bypasses i915 and accesses mmio directly, that easily > > confuses our automatic mmio debugging (any error we then detect is > > likely to be as a result of the user). Since we expect

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Disable mmio debugging during user access

== Series Details == Series: drm/i915: Disable mmio debugging during user access URL : https://patchwork.freedesktop.org/series/29935/ State : success == Summary == Test kms_atomic_transition: Subgroup plane-use-after-nonblocking-unbind: incomplete -> FAIL

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