== Series Details ==
Series: drm/i915/dp: Do not set the eDP link rate/lane count to max
URL : https://patchwork.freedesktop.org/series/39662/
State : failure
== Summary ==
Possible new issues:
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
pass -> FAIL
Hi Michal,
One comment was missed and another comment update suggested.
On 3/8/2018 9:16 PM, Michał Winiarski wrote:
We have all the information we need at relay_open call time.
Since there's no reason to split the process into relay_open and
relay_late_setup_files, let's remove the extra code.
From: Mahesh Kumar
Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.
v2: Addressed review comments by Maarten
v3: Rebased and addressed r
From: Mahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
v2: Added reviewed by tag from Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Mahesh Kumar
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
v2: Added reviewed by tag from Mika Kahola
Reviewed-by: Mika Kahola
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drive
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offs
From: Mahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl
This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
Previous revision history:
The first version of patches were reviewed when floated b
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats
v4: Addressed review comments
From: Mahesh Kumar
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below the
current level. Render decompression requires level WM to be as high as
wm level-0. This patch fulfils both the requirements.
v2: Change
From: Mahesh Kumar
For YUV 420 Planar formats like NV12,
buffer allocation is done for Y and UV surfaces separately.
For NV12 plane formats, the UV buffer
allocation must be programmed in the Plane Buffer Config register
and the Y buffer allocation must be programmed in the
Plane NV12 Buffer Conf
From: Mahesh Kumar
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable late
From: Chandra Konduru
This patch updates scaler max limit support for NV12
v2: Rebased (me)
v3: Rebased (me)
v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v5: Addressed review comments from Ville and rebased
- calculation of max
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function
for sprite planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
v3: Rebased (me)
v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats
v5: Rebased (me)
v6: M
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
v2: Addressed review comments from Shashank Sharma.
v3: Addressed review comments from Shashank Sharma
Changed plane_num to plane_id in skl_compute_plane_wm_par
From: Mahesh Kumar
This patch passes skl_wm_level structure itself to watermark
computation function skl_compute_plane_wm function (instead
of its internal parameters). It reduces number of arguments
required to be passed.
v2: Addressed review comments by Shashank Sharma
v3: Adding reviewed by
From: Chandra Konduru
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler
v3: Rebased (me)
v
Display WA 827 applies to GEN9 (excluede GLK) and CNL.
Switching the plane format from NV12 to RGB and leaving system idle
results in display underrun and corruption.
WA: Set the bit 15 & bit 19 to 1b in the CLKGATE_DIS_PSL
register for the pipe in which NV12 plane is enabled.
Signed-off-by: Chand
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
v2: Addressed review comments from Shashank Sharma
Alignment issue fixed in i915_reg.h
v3: Adding Reviewed By from Shashank Sharma
v4: Rebased the patch. As part of rebasing, re-using
the color series defines which are a
== Series Details ==
Series: Add NV12 support
URL : https://patchwork.freedesktop.org/series/39670/
State : failure
== Summary ==
Series 39670v1 Add NV12 support
https://patchwork.freedesktop.org/api/1.0/series/39670/revisions/1/mbox/
Possible new issues:
Test prime_vgem:
Subgro
== Series Details ==
Series: drm/i915: Remove support for legacy debugfs crc interface (rev2)
URL : https://patchwork.freedesktop.org/series/33053/
State : failure
== Summary ==
Possible new issues:
Test kms_pipe_crc_basic:
Subgroup bad-nb-words-1:
pass -> S
On Thu, Mar 08, 2018 at 06:03:32PM +0530, Ramalingam C wrote:
> On Thursday 08 March 2018 06:00 PM, Winkler, Tomas wrote:
> >
> > > -Original Message-
> > > From: C, Ramalingam
> > > Sent: Thursday, March 08, 2018 13:58
> > > To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop
On 3/8/2018 9:16 PM, Michał Winiarski wrote:
Having both guc_flush_logs and guc_log_flush functions is confusing.
While we could just rename things, guc_flush_logs implementation is
quite simple. Let's get rid of it and move its content to unregister.
v2: s/dev_priv/i915 (Sagar)
Signed-off-by
On 08/03/2018 18:46, Daniele Ceraolo Spurio wrote:
On 08/03/18 01:31, Tvrtko Ursulin wrote:
On 07/03/2018 19:45, Daniele Ceraolo Spurio wrote:
The mmio bases we're currently storing in the intel_engines array are
only valid for a subset of gens, so we need to ignore them and use
different val
If we timeout waiting for the GPU to idle, something went seriously
wrong. We currently dump the engine state, but we can also dump the
ftrace buffer showing our last operations (when available).
In passing, note that since commit 559e040f1f08 ("drm/i915: Show the GPU
state when declaring wedged",
On 09/03/2018 01:38, Chris Wilson wrote:
Quoting Chris Wilson (2018-03-09 01:33:08)
gen11_gt_engine_intr(struct drm_i915_private * const i915,
const unsigned int bank, const unsigned int bit)
@@ -2836,10 +2798,23 @@ static void
gen11_gt_irq_handler(struct drm_i915_priv
If we timeout waiting for the GPU to idle, something went seriously
wrong. We currently dump the engine state, but we can also dump the
ftrace buffer showing our last operations (when available).
In passing, note that since commit 559e040f1f08 ("drm/i915: Show the GPU
state when declaring wedged",
Quoting Tvrtko Ursulin (2018-03-09 10:06:48)
>
> On 09/03/2018 01:38, Chris Wilson wrote:
> And in general I think too many bike-sheds on this area of code before
> we are even running it on real hw. :(
Come on now, it's not a proper bikeshed if the discussion is meaningful!
-Chris
_
On Thu, 08 Mar 2018, Manasi Navare wrote:
> The panels are generally designed to support only a single
> clock and lane configuration, and typically these values
> correspond to the native resolution of the panel. But some
> panels advertise the MAX_LINK_RATE in DPCD higher than what
> is required
Quoting Jani Nikula (2018-03-09 10:20:37)
> On Thu, 08 Mar 2018, Manasi Navare wrote:
> > The panels are generally designed to support only a single
> > clock and lane configuration, and typically these values
> > correspond to the native resolution of the panel. But some
> > panels advertise the
Joonas, so did this miss the deadline for v4.17? You're not making
another pull request?
BR,
Jani.
On Thu, 08 Mar 2018, Joonas Lahtinen wrote:
> Pulled.
>
> Regards, Joonas
>
> Quoting Zhenyu Wang (2018-03-08 04:31:52)
>>
>> Hi,
>>
>> Here's gvt-next update for 4.17. Biggest update is for hug
On Tue, 06 Mar 2018, Ville Syrjälä wrote:
> On Tue, Mar 06, 2018 at 12:41:55PM +0200, Jani Nikula wrote:
>> We don't want to preserve the DDI A 4 lane bit on ICL.
>>
>> Fixes: 3d2011cfa41f ("drm/i915/icl: remove port A/E lane sharing
>> limitation.")
>> Cc: Mahesh Kumar
>> Cc: Paulo Zanoni
>>
Quoting Chris Wilson (2018-03-09 01:08:08)
> Originally we were inlining gen8_cs_irq_handler() and so expected the
> compiler to constant-fold away the irq_shift (so we had hardcoded it as
> opposed to use engine->irq_shift). However, we dropped the inline given
> the proliferation of gen8_cs_irq_h
== Series Details ==
Series: drm/i915: Show GEM_TRACE when detecting a failed GPU idle (rev2)
URL : https://patchwork.freedesktop.org/series/39674/
State : success
== Summary ==
Series 39674v2 drm/i915: Show GEM_TRACE when detecting a failed GPU idle
https://patchwork.freedesktop.org/api/1.0/s
On 3/8/2018 9:17 PM, Michał Winiarski wrote:
Those two concepts are really separate. Since GuC is writing data into
its own buffer and we even provide a way for userspace to read directly
from it using i915_guc_log_dump debugfs, there's no real reason to tie
log level with relay creation.
Let's
On bxt, we see that the rc6 subtest flip-flops as RC6 does not restart
within our desired interval. Improve the likelihood of the inspection
passing by idling the GPU and waiting for 2 Evaluation Intervals before
we start polling of RC6 residency.
Signed-off-by: Chris Wilson
---
tests/gem_mocs_s
On 3/8/2018 9:17 PM, Michał Winiarski wrote:
Runtime is not a very good name. Let's also move counting relay
overflows inside relay struct.
v2: Rename things rather than remove the struct (Chris)
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Sagar Arun Kam
On Thu, 08 Mar 2018 16:47:00 +0100, Michał Winiarski
wrote:
Those two concepts are really separate. Since GuC is writing data into
its own buffer and we even provide a way for userspace to read directly
from it using i915_guc_log_dump debugfs, there's no real reason to tie
log level with rela
On 3/8/2018 9:17 PM, Michał Winiarski wrote:
If nobody has enabled the relay, we're not comunicating with GuC, which
means that the stats don't have any meaning. Let's also remove interrupt
counter and tidy the debugfs formatting.
v2: Correct stats accounting (Sagar)
Signed-off-by: Michał Win
On 3/8/2018 9:17 PM, Michał Winiarski wrote:
Now that we've decoupled logging from relay, GuC log level is only
controlling the GuC behavior - there shouldn't be any impact on i915
behaviour. We're only going to see a single extra interrupt when log
will get half full.
That, and the fact that w
From: Tvrtko Ursulin
We need to use absolute tolerance when asserting on percentages. Relative
tolerance in this case is unfair and inaccurate since it's strictness
varies with relative target busyness.
v2:
* Do not include spin batch edit and submit into measured time.
* Open PMU before child
On 3/9/2018 2:30 AM, Michal Wajdeczko wrote:
Instead of dancing around uC on reset/suspend/resume scenarios,
explicitly sanitize uC when we sanitize GEM to force uC reload
and start from known beginning.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Sagar Arun Kamble
Cc: Ch
Op 06-03-18 om 16:57 schreef Maxime Ripard:
> Hi,
>
> On Mon, Mar 05, 2018 at 07:14:16PM +0100, Maarten Lankhorst wrote:
>> Only try to set those values if the properties are supported.
>> This fixes the kms_chameium tests to run on vc4 again.
>>
>> Reported-by: Maxime Ripard
>> Cc: Paul Kocialkow
No significant changes from either context offsets, nor report
formats, nor register whitelist.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_oa_icl.c | 118 +
drivers/gpu/drm/i915/i915_oa_icl.h |
On Thu, 08 Mar 2018, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> Previously it was assumed that eDP panels would advertise the lowest link
> rate required for their singular mode to function. With the introduction
> of more advanced features there are advantages to a panel advertisin
== Series Details ==
Series: drm/i915: Show GEM_TRACE when detecting a failed GPU idle (rev2)
URL : https://patchwork.freedesktop.org/series/39674/
State : failure
== Summary ==
Possible new issues:
Test kms_cursor_legacy:
Subgroup cursorb-vs-flipb-atomic-transitions-varying-size
== Series Details ==
Series: drm/i915/perf: enable perf support on ICL
URL : https://patchwork.freedesktop.org/series/39689/
State : success
== Summary ==
Series 39689v1 drm/i915/perf: enable perf support on ICL
https://patchwork.freedesktop.org/api/1.0/series/39689/revisions/1/mbox/
Kno
This patch replaces use of remaining _MMIO_PORT6 macro and removes the
macro.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_reg.h | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7
This patch creates a new macro to get PORT_TX register for any given DW.
This will remove the need of defining register address for each port & DW.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_reg.h | 28
1 file changed, 28 insertions(+)
diff --git a/dr
This series fixes CNL PORT_TX_DW5/7_LNO_D register address.
This series also introduces macros to get register address of
CNL_PORT_TX registers instead of defining for each DW instance.
changes since V1:
completely kill _MMIO_PORT6 macro
Mahesh Kumar (3):
drm/i915/cnl; Add macro to get PORT_TX
This patch replaces CNL_PORT_TX register macros with new macros defined
in previous patch.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_reg.h | 107 +---
1 file changed, 11 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg
Chris Wilson writes:
> Before we reset the GPU after marking the device as wedged, we wait for
> all the remaining requests to be completed (and marked as EIO).
> Afterwards, we should flush the request lists so the next batch start
> with the driver in an idle start.
s/start/state?
>
> Signed-
On Fri, Mar 09, 2018 at 12:55:24PM +0100, Maarten Lankhorst wrote:
> Op 06-03-18 om 16:57 schreef Maxime Ripard:
> > Hi,
> >
> > On Mon, Mar 05, 2018 at 07:14:16PM +0100, Maarten Lankhorst wrote:
> >> Only try to set those values if the properties are supported.
> >> This fixes the kms_chameium tes
Quoting Chris Wilson (2018-03-07 13:42:22)
> With a series of unusual events (a sequence of interrupted request
> allocations), we could gradually leak the ring->space estimate by
> unwinding the ring back to the start of the request, but not return the
> used space back to the ring. Eventually and
Chris Wilson writes:
> With a series of unusual events (a sequence of interrupted request
> allocations), we could gradually leak the ring->space estimate by
> unwinding the ring back to the start of the request, but not return the
> used space back to the ring. Eventually and with great misfortu
Quoting Mika Kuoppala (2018-03-09 13:17:09)
> Chris Wilson writes:
>
> > With a series of unusual events (a sequence of interrupted request
> > allocations), we could gradually leak the ring->space estimate by
> > unwinding the ring back to the start of the request, but not return the
> > used sp
Chris Wilson writes:
> When wedged, we do not update the ring->tail as we submit the requests
> causing us to leak the ring->space upon cleaning up the wedged driver.
> We can just use the value stored in rq->tail, and keep the submission
> backend details away from set-wedge.
>
> Signed-off-by:
Chris Wilson writes:
> Include ring->emit and ring->space alongside ring->(head,tail) when
> printing debug information.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_debugfs.c| 4 ++--
> drivers/gpu/drm/i915/intel_engine_cs.c | 10 +++---
> 2 f
On 9 March 2018 at 11:58, Lionel Landwerlin
wrote:
> No significant changes from either context offsets, nor report
> formats, nor register whitelist.
>
> Signed-off-by: Lionel Landwerlin
> ---
The usual spiel about disabling clock-ratio-change reports, do we need it?
So this will need the time
Chris Wilson writes:
> Similar to the staging around handling of engine->submit_request, we
> need to stop adding to the execlists->queue prior to calling
> engine->cancel_requests. cancel_requests will move requests from the
> queue onto the timeline, so if we add a request onto the queue after
Quoting Mika Kuoppala (2018-03-09 13:38:37)
> Chris Wilson writes:
>
> > When wedged, we do not update the ring->tail as we submit the requests
> > causing us to leak the ring->space upon cleaning up the wedged driver.
> > We can just use the value stored in rq->tail, and keep the submission
> >
== Series Details ==
Series: CNL port refactoring (rev2)
URL : https://patchwork.freedesktop.org/series/38334/
State : success
== Summary ==
Series 38334v2 CNL port refactoring
https://patchwork.freedesktop.org/api/1.0/series/38334/revisions/2/mbox/
Known issues:
Test kms_frontbuffer_tr
Exercise some new API that allows applications to request that
individual contexts are executed within a desired frequency range.
v2: Split single/continuous set_freq subtests
v3: Do an up/down ramp for individual freq request, check nothing
changes after each invalid request
Signed-off-by: Chris
Chris Wilson writes:
> tasklet_kill() will spin waiting for the current tasklet to be executed.
> However, if tasklet_disable() has been called, then the tasklet is never
> executed but permanently put back onto the runlist until
> tasklet_enable() is called. Ergo, we cannot use tasklet_kill() in
Quoting Chris Wilson (2018-03-07 13:42:26)
> tasklet_kill() will spin waiting for the current tasklet to be executed.
> However, if tasklet_disable() has been called, then the tasklet is never
> executed but permanently put back onto the runlist until
> tasklet_enable() is called. Ergo, we cannot u
On 09/03/18 13:49, Matthew Auld wrote:
On 9 March 2018 at 11:58, Lionel Landwerlin
wrote:
No significant changes from either context offsets, nor report
formats, nor register whitelist.
Signed-off-by: Lionel Landwerlin
---
The usual spiel about disabling clock-ratio-change reports, do we nee
Quoting Chris Wilson (2018-03-09 14:10:34)
> Quoting Chris Wilson (2018-03-07 13:42:26)
> > tasklet_kill() will spin waiting for the current tasklet to be executed.
> > However, if tasklet_disable() has been called, then the tasklet is never
> > executed but permanently put back onto the runlist un
On Fri, Mar 09, 2018 at 10:42:40AM +, Chris Wilson wrote:
> On bxt, we see that the rc6 subtest flip-flops as RC6 does not restart
> within our desired interval. Improve the likelihood of the inspection
> passing by idling the GPU and waiting for 2 Evaluation Intervals before
> we start polling
From: Ville Syrjälä
Add a function to check whether there is at least one plane that
supports a specific format and modifier combination. Drivers can
use this to reject unsupported formats/modifiers in .fb_create().
v2: Accept anyformat if the driver doesn't do planes (Eric)
s/planes_have_fo
From: Ville Syrjälä
Replace the messy framebuffer format/modifier validation code
with a single call to drm_any_plane_has_format(). The code was
extremely annoying to maintain as you had to have a lot of platform
checks for different formats. The new code requires zero maintenance.
v2: Nuke the
From: Ville Syrjälä
Only create framebuffers with supported format/modifier combinations by
checking that at least one plane supports the requested combination.
Using drm_any_plane_has_format() is somewhat suboptimal for vc4 since
the planes have (mostly) uniform capabilities. But I was lazy and
From: Ville Syrjälä
Put an empty line between the variable declarations and the code, and
use tabs for alignment.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_framebuffer.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_framebuffer.c
b/dri
== Series Details ==
Series: series starting with [v3,1/4] drm: Add drm_any_plane_has_format()
URL : https://patchwork.freedesktop.org/series/39700/
State : success
== Summary ==
Series 39700v1 series starting with [v3,1/4] drm: Add drm_any_plane_has_format()
https://patchwork.freedesktop.org/
== Series Details ==
Series: drm/i915/perf: enable perf support on ICL
URL : https://patchwork.freedesktop.org/series/39689/
State : success
== Summary ==
Known issues:
Test gem_eio:
Subgroup in-flight:
incomplete -> PASS (shard-apl) fdo#105341
Test kms_curs
On Apollolake, with stress test warm reboot, audio card
was not getting enumerated after reboot. This was a
spurious issue happening on Apollolake. HW codec and
HD audio controller link was going out of sync for which
there was a fix in i915 driver but was not getting invoked
for BXT. Extending thi
Attempt to sanitize uC for better alignment with rest of GEM driver.
v2: cover reset path and sanitize uc before gem
Michal Wajdeczko (3):
drm/i915/uc: Sanitize uC options early
drm/i915/uc: Sanitize uC together with GEM
HAX: Enable GuC for CI
drivers/gpu/drm/i915/i915_drv.c| 2 --
d
We are sanitizing uC related modparams together with other driver
modparams in intel_sanitize_options called from i915_driver_init_hw,
but this is too late for us as we will want to use USES_GUC/USES_HUC
macros at earlier stage. Since our sanitizing does not require any
MMIO access, we can do it in
Instead of dancing around uC on reset/suspend/resume scenarios,
explicitly sanitize uC when we sanitize GEM to force uC reload
and start from known beginning.
v2: don't forget about reset path (Daniele)
sanitize uc before gem initiated full reset (Daniele)
Signed-off-by: Michal Wajdeczko
Cc:
v2: except running with HYPERVISOR
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
inde
On Thu, Mar 08, 2018 at 04:22:55PM +0100, Michal Wajdeczko wrote:
> On Thu, 08 Mar 2018 13:58:48 +0100, Petri Latvala
> wrote:
>
> > On Thu, Mar 08, 2018 at 02:20:41PM +0200, Jani Nikula wrote:
> > > On Thu, 08 Mar 2018, Chris Wilson wrote:
> > > > Quoting Michal Wajdeczko (2018-03-08 09:50:33)
== Series Details ==
Series: drm: i915: Fix audio issue on BXT (rev2)
URL : https://patchwork.freedesktop.org/series/35955/
State : failure
== Summary ==
Series 35955v2 drm: i915: Fix audio issue on BXT
https://patchwork.freedesktop.org/api/1.0/series/35955/revisions/2/mbox/
Possible new
On Fri, Mar 09, 2018 at 12:00:06PM +0100, Michal Wajdeczko wrote:
> On Thu, 08 Mar 2018 16:47:00 +0100, Michał Winiarski
> wrote:
>
> > Those two concepts are really separate. Since GuC is writing data into
> > its own buffer and we even provide a way for userspace to read directly
> > from it us
== Series Details ==
Series: drm/i915/uc: Sanitize uC (rev2)
URL : https://patchwork.freedesktop.org/series/39634/
State : success
== Summary ==
Series 39634v2 drm/i915/uc: Sanitize uC
https://patchwork.freedesktop.org/api/1.0/series/39634/revisions/2/mbox/
Known issues:
Test debugfs_te
Quoting Michał Winiarski (2018-03-09 16:30:42)
> On Fri, Mar 09, 2018 at 12:00:06PM +0100, Michal Wajdeczko wrote:
> > On Thu, 08 Mar 2018 16:47:00 +0100, Michał Winiarski
> > wrote:
> >
> > > Those two concepts are really separate. Since GuC is writing data into
> > > its own buffer and we even
From: Michal Wajdeczko
v2: except running with HYPERVISOR
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9
From: Michal Wajdeczko
To allow future code reuse. While here, fix comment style.
v2: Notifications are a separate thing - rename the handler (Sagar)
Suggested-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Os
From: Michał Winiarski
We plan to decouple log runtime (mapping + relay) from verbosity control.
Let's tidy the code now to reduce the churn in the following patches.
v2: Tidy macros, keep debug messages, use helper var for enable,
correct typo (Michał)
Fix incorrect input validaction (S
From: Michał Winiarski
We have many functions responsible for allocating different parts of
GuC log runtime called from multiple places. Let's stick with keeping
everything in guc_log_register instead.
v2: Use more generic intel_uc_register name, keep using "misc" suffix (Michał)
s/dev_priv/
On 09/03/2018 13:46, Chris Wilson wrote:
Exercise some new API that allows applications to request that
individual contexts are executed within a desired frequency range.
v2: Split single/continuous set_freq subtests
v3: Do an up/down ramp for individual freq request, check nothing
changes afte
== Series Details ==
Series: drm/i915: misc fixes in headers (RESEND)
URL : https://patchwork.freedesktop.org/series/39589/
State : success
== Summary ==
Series 39589v1 drm/i915: misc fixes in headers (RESEND)
https://patchwork.freedesktop.org/api/1.0/series/39589/revisions/1/mbox/
Known
On 08/03/2018 14:07, Chris Wilson wrote:
There is some redundancy between dma_fence->ops->enable_signaling (via
i915_fence_enable_signaling) and our backend,
intel_engine_enable_signaling() in that both levels recheck the fence
status multiple times. If we convert intel_engine_enable_signaling()
Quoting Tvrtko Ursulin (2018-03-09 17:06:45)
>
> On 09/03/2018 13:46, Chris Wilson wrote:
> > Exercise some new API that allows applications to request that
> > individual contexts are executed within a desired frequency range.
> >
> > v2: Split single/continuous set_freq subtests
> > v3: Do an u
== Series Details ==
Series: CNL port refactoring (rev2)
URL : https://patchwork.freedesktop.org/series/38334/
State : success
== Summary ==
Known issues:
Test gem_eio:
Subgroup in-flight-external:
pass -> INCOMPLETE (shard-apl) fdo#105341
Test kms_cursor_cr
Quoting Tvrtko Ursulin (2018-03-09 17:24:33)
>
> On 08/03/2018 14:07, Chris Wilson wrote:
> > There is some redundancy between dma_fence->ops->enable_signaling (via
> > i915_fence_enable_signaling) and our backend,
> > intel_engine_enable_signaling() in that both levels recheck the fence
> > statu
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control
URL : https://patchwork.freedesktop.org/series/39710/
State : success
== Summary ==
Series 39710v1 series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control
https://patchwork.freedesktop.org/ap
== Series Details ==
Series: Add NV12 support
URL : https://patchwork.freedesktop.org/series/39670/
State : success
== Summary ==
Series 39670v1 Add NV12 support
https://patchwork.freedesktop.org/api/1.0/series/39670/revisions/1/mbox/
Known issues:
Test debugfs_test:
Subgroup re
Hi Dave,
Here are the -misc-next pulls for the last 2 weeks. Sorry for the hold-up
last week.
drm-misc-next-2018-03-09-3:
drm-misc-next for 4.17:
UAPI Changes:
plane: Add color encoding/range properties (Jyri)
nouveau: Replace iturbt_709 property with color_encoding property (Ville)
Core Chan
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values. Also added the code,
for extracting the same from values passed from userspace.
S
This patch series adds properties for plane color features. It adds
properties for degamma used to linearize data, CSC used for gamut
conversion, and gamma used to again non-linearize data as per panel
supported color space. These can be utilize by user space to convert
planes from one format to an
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