Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v8,01/12] drm/i915: Park before resetting the submission backend

On 4/9/2018 9:02 PM, Michal Wajdeczko wrote: On Mon, 09 Apr 2018 17:09:18 +0200, Patchwork wrote: == Series Details == Series: series starting with [v8,01/12] drm/i915: Park before resetting the submission backend URL   :

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

== Series Details == Series: series starting with [v3,1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes URL : https://patchwork.freedesktop.org/series/41409/ State : failure == Summary == Possible new issues: Test gem_eio: Subgroup execbuf:

Re: [Intel-gfx] [PATCH v1 00/14] Preparation patches for NV12

> -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Monday, April 9, 2018 5:15 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Cc: Kamath, Sunil > Subject: Re: [Intel-gfx]

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3)

== Series Details == Series: series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3) URL : https://patchwork.freedesktop.org/series/41095/ State : success == Summary == Possible new issues: Test kms_cursor_legacy: Subgroup pipe-c-torture-move:

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

== Series Details == Series: series starting with [v3,1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes URL : https://patchwork.freedesktop.org/series/41409/ State : success == Summary == Series 41409v1 series starting with [v3,1/4] drm/i915: Always do WOPCM

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3)

== Series Details == Series: series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3) URL : https://patchwork.freedesktop.org/series/41095/ State : success == Summary == Series 41095v3 series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3)

== Series Details == Series: series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3) URL : https://patchwork.freedesktop.org/series/41095/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0a22dbbae8f8 drm/i915: Enable edp psr error interrupts on hsw

[Intel-gfx] [PATCH v3 2/4] drm/i915: Always set HUC_LOADING_AGENT_GUC bit in WOPCM offset register

The enable_guc modparam is used to enable/disable GuC/HuC FW uploading dynamcially during i915 module loading. If WOPCM offset register was locked without having HUC_LOADING_AGENT_GUC bit set to 1, the module reloading with both GuC and HuC FW will fail since we need to set this bit to 1 for HuC

[Intel-gfx] [PATCH v3 3/4] drm/i915: Add code to accept valid locked WOPCM register values

In current code, we only compare the locked WOPCM register values with the calculated values. However, we can continue loading GuC/HuC firmware if the locked (or partially locked) values were valid for current GuC/HuC firmware sizes. This patch added a new code path to verify whether the locked

[Intel-gfx] [PATCH v3 4/4] HAX enable guc for CI

Signed-off-by: Jackie Li --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c963603..53037b5 100644 ---

[Intel-gfx] [PATCH v3 1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

After enabled the WOPCM write-once registers locking status checking, reloading of the i915 module will fail with modparam enable_guc set to 3 (enable GuC and HuC firmware loading) if the module was originally loaded with enable_guc set to 1 (only enable GuC firmware loading). This is because

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq is enabled

== Series Details == Series: series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq is enabled URL : https://patchwork.freedesktop.org/series/41396/ State : failure == Summary == Possible new issues: Test gem_eio: Subgroup execbuf: pass ->

Re: [Intel-gfx] [PATCH 3/8] drm/i915/icl: add basic support for the ICL clocks

On Wed, Mar 28, 2018 at 02:57:58PM -0700, Paulo Zanoni wrote: > This commit introduces the definitions for the ICL clocks and adds the > basic functions to the shared DPLL framework. It adds code for the > Enable and Disable sequences for some PLLs, but it does not have the > code to compute the

Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

On 4/9/2018 4:20 PM, Pandiyan, Dhinakaran wrote: On Mon, 2018-04-09 at 12:18 -0700, Kumar, Abhay wrote: On 4/9/2018 12:10 PM, Rodrigo Vivi wrote: On Mon, Apr 09, 2018 at 05:07:31PM +0300, Jani Nikula wrote: On Sun, 08 Apr 2018, Gaurav K Singh wrote: On

Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

On Mon, 2018-04-09 at 12:18 -0700, Kumar, Abhay wrote: > > On 4/9/2018 12:10 PM, Rodrigo Vivi wrote: > > On Mon, Apr 09, 2018 at 05:07:31PM +0300, Jani Nikula wrote: > >> On Sun, 08 Apr 2018, Gaurav K Singh wrote: > >>> On Geminilake, sometimes audio card is not

Re: [Intel-gfx] [PATCH v2] drm/i915: set minimum CD clock to twice the BCLK.

On 4/9/2018 3:33 AM, Ville Syrjälä wrote: On Fri, Apr 06, 2018 at 04:47:08PM +0300, Jani Nikula wrote: On Thu, 05 Apr 2018, Abhay Kumar wrote: In glk when device boots with 1366x768 panel, HDA codec doesn't comeup. This result in no audio forever as cdclk is < 96Mhz.

Re: [Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

On 4/9/2018 12:53 PM, Chris Wilson wrote: Quoting Oscar Mateo (2018-04-06 23:24:57) Inherit workarounds from previous platforms that are still valid for Icelake. Speaking of the workarounds, where do we stand with at least landing the split out of init_workarounds_ring()? Rebuilding the

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/pmu: check runtime resume vs pmu race

== Series Details == Series: drm/i915/pmu: check runtime resume vs pmu race URL : https://patchwork.freedesktop.org/series/41380/ State : warning == Summary == Possible new issues: Test perf_pmu: Subgroup rc6-runtime-pm: pass -> DMESG-WARN (shard-apl)

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq is enabled

== Series Details == Series: series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq is enabled URL : https://patchwork.freedesktop.org/series/41396/ State : success == Summary == Series 41396v1 series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq is enabled

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq is enabled

== Series Details == Series: series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq is enabled URL : https://patchwork.freedesktop.org/series/41396/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2fc2ed95e6cd drm/i915/guc: Check that the breadcrumb irq is

Re: [Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

Quoting Oscar Mateo (2018-04-06 23:24:57) > Inherit workarounds from previous platforms that are still valid for > Icelake. Speaking of the workarounds, where do we stand with at least landing the split out of init_workarounds_ring()? Rebuilding the invariant wa_regs[] on every reset is

Re: [Intel-gfx] [PATCH] drm/i915: Add debugfs file to clear FIFO underruns.

On Wed, Mar 28, 2018 at 06:20:26PM +0200, Maarten Lankhorst wrote: > Op 28-03-18 om 12:21 schreef Jani Nikula: > > On Wed, 28 Mar 2018, Maarten Lankhorst > > wrote: > >> Adding a i915_fifo_underrun_reset debugfs file will make it possible > >> for IGT tests to

[Intel-gfx] [PATCH 2/2] HAX:guc

--- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c96360398072..53037b5eff22 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++

[Intel-gfx] [PATCH 1/2] drm/i915/guc: Check that the breadcrumb irq is enabled

Our execlists emulation for GuC requires use of the breadcrumb following every request as a simulcrum for the context-switch interrupt, which we then use to drive the submission tasklet. Therefore, when we unpark the engine for use with the GuC, we pin the breadcrumb interrupt to keep it enabled

Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

On 4/9/2018 12:10 PM, Rodrigo Vivi wrote: On Mon, Apr 09, 2018 at 05:07:31PM +0300, Jani Nikula wrote: On Sun, 08 Apr 2018, Gaurav K Singh wrote: On Geminilake, sometimes audio card is not getting detected after reboot. This is a spurious issue happening on

Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock

On Sat, Apr 07, 2018 at 10:05:25AM +0100, Chris Wilson wrote: > Quoting Rodrigo Vivi (2018-04-06 23:18:16) > > On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote: > > > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote: > > > > + struct drm_crtc *crtc = > > > > +

Re: [Intel-gfx] [PATCH] drm/i915/cnp: Properly handle VBT ddc pin out of bounds.

On Mon, Apr 09, 2018 at 12:48:15PM +0300, Jani Nikula wrote: > On Fri, 23 Mar 2018, Timo Aaltonen wrote: > > On 30.01.2018 00:12, Rodrigo Vivi wrote: > >> On Mon, Jan 29, 2018 at 05:42:53AM +, Kai Heng Feng wrote: > >>> > On 26 Jan 2018, at 6:25 AM, Rodrigo Vivi

Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

On Mon, Apr 09, 2018 at 05:07:31PM +0300, Jani Nikula wrote: > On Sun, 08 Apr 2018, Gaurav K Singh wrote: > > On Geminilake, sometimes audio card is not getting > > detected after reboot. This is a spurious issue happening on > > Geminilake. HW codec and HD audio

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable display workaround 827 for all planes, v2.

== Series Details == Series: drm/i915: Enable display workaround 827 for all planes, v2. URL : https://patchwork.freedesktop.org/series/41371/ State : success == Summary == Known issues: Test kms_flip: Subgroup 2x-flip-vs-expired-vblank-interruptible: fail

Re: [Intel-gfx] [PATCH 6/7] drm/i915/dp: abstract link config selection

On Mon, Apr 09, 2018 at 05:12:03PM +0300, Jani Nikula wrote: > On Thu, 05 Apr 2018, Manasi Navare wrote: > > On Thu, Apr 05, 2018 at 05:39:04PM +0300, Jani Nikula wrote: > >> For now, there's just the one link config selection, optimizing for slow > >> and wide link. No

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/debugfs: Print sink PSR status

On Fri, 2018-04-06 at 18:40 -0700, Dhinakaran Pandiyan wrote: > > > On Sat, 2018-04-07 at 00:49 +, Souza, Jose wrote: > > On Fri, 2018-04-06 at 16:36 -0700, José Roberto de Souza wrote: > > > On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote: > > > > On Mon, 2018-04-02 at 13:51

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Change use get_new_plane_state instead of existing plane state

== Series Details == Series: series starting with [1/4] drm/i915: Change use get_new_plane_state instead of existing plane state URL : https://patchwork.freedesktop.org/series/41370/ State : success == Summary == Known issues: Test kms_flip: Subgroup flip-vs-absolute-wf_vblank:

[Intel-gfx] ✗ Fi.CI.BAT: failure for Queued/runnable/running engine stats (rev7)

== Series Details == Series: Queued/runnable/running engine stats (rev7) URL : https://patchwork.freedesktop.org/series/36926/ State : failure == Summary == Series 36926v7 Queued/runnable/running engine stats https://patchwork.freedesktop.org/api/1.0/series/36926/revisions/7/mbox/

Re: [Intel-gfx] [PATCH i-g-t] tools/aubdump: Fix ISO C90 forbids mixed declarations and code warning

Tvrtko Ursulin writes: > From: Tvrtko Ursulin > > Back to a clean build with no warnings, at least for me. Why c90? If that's the language we mean to target then we should probably add it to the build system so people with gcc 5.1 and later will

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Check that the breadcrumb irq is enabled

== Series Details == Series: drm/i915/guc: Check that the breadcrumb irq is enabled URL : https://patchwork.freedesktop.org/series/41368/ State : success == Summary == Known issues: Test kms_flip: Subgroup 2x-wf_vblank-ts-check: fail -> PASS

[Intel-gfx] [PATCH v3 7/7] drm/i915: Engine queues query

From: Tvrtko Ursulin As well as exposing active requests on engines via PMU, we can also export the current raw values (as tracked by i915 command submission) via a dedicated query. This is to satisfy customers who have userspace load balancing solutions implemented on

[Intel-gfx] [PATCH v10 2/7] drm/i915: Keep a count of requests waiting for a slot on GPU

From: Tvrtko Ursulin Keep a per-engine number of runnable (waiting for GPU time) requests. We choose to mange the runnable counter at the backend level instead of at the request submit_notify callback. The latter would be more consolidated and less code, but it would

[Intel-gfx] [PATCH v4 3/7] drm/i915: Keep a count of requests submitted from userspace

From: Tvrtko Ursulin Keep a count of requests submitted from userspace and not yet runnable due unresolved dependencies. v2: Rename and move under the container struct. (Chris Wilson) v3: Rebase. v4: Move decrement site to the backend to shrink the window of double-

[Intel-gfx] [PATCH i-g-t] tools/aubdump: Fix ISO C90 forbids mixed declarations and code warning

From: Tvrtko Ursulin Back to a clean build with no warnings, at least for me. Signed-off-by: Tvrtko Ursulin Cc: Jordan Justen Cc: Scott D Phillips --- tools/aubdump.c | 7 --- 1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: check runtime resume vs pmu race

== Series Details == Series: drm/i915/pmu: check runtime resume vs pmu race URL : https://patchwork.freedesktop.org/series/41380/ State : success == Summary == Series 41380v1 drm/i915/pmu: check runtime resume vs pmu race

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

== Series Details == Series: drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout URL : https://patchwork.freedesktop.org/series/41366/ State : success == Summary == Known issues: Test kms_flip: Subgroup 2x-wf_vblank-ts-check: fail -> PASS

[Intel-gfx] [CI] drm/i915/pmu: check runtime resume vs pmu race

From: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_pmu.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index

Re: [Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote: As we always call intel_uc_sanitize after every call to intel_uc_fini_hw we may drop redundant call and sanitize uC from the fini_hw function. Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v8,01/12] drm/i915: Park before resetting the submission backend

On Mon, 09 Apr 2018 17:09:18 +0200, Patchwork wrote: == Series Details == Series: series starting with [v8,01/12] drm/i915: Park before resetting the submission backend URL : https://patchwork.freedesktop.org/series/41365/ State : failure == Summary

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v8,01/12] drm/i915: Park before resetting the submission backend

== Series Details == Series: series starting with [v8,01/12] drm/i915: Park before resetting the submission backend URL : https://patchwork.freedesktop.org/series/41365/ State : failure == Summary == Possible new issues: Test drm_mm: Subgroup sanitycheck: pass

Re: [Intel-gfx] [PATCH v8 05/12] drm/i915: Add i915_gem_fini_hw to i915_gem_suspend

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote: By calling i915_gem_init_hw in i915_gem_resume and not calling i915_gem_fini_hw in i915_gem_suspend we introduced asymmetry in init_hw/fini_hw calls. Let's fix that. Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable display workaround 827 for all planes, v2.

== Series Details == Series: drm/i915: Enable display workaround 827 for all planes, v2. URL : https://patchwork.freedesktop.org/series/41371/ State : success == Summary == Series 41371v1 drm/i915: Enable display workaround 827 for all planes, v2.

Re: [Intel-gfx] [PATCH v8 04/12] drm/i915: Introduce i915_gem_fini_hw for symmetry with i915_gem_init_hw

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote: We have i915_gem_init_hw function that on failure requires some cleanup in uC and then in other places we were trying to do such cleanup directly. Let's fix that by adding i915_gem_fini_hw for nice symmetry with init_hw and call it on cleanup paths.

Re: [Intel-gfx] [PATCH v8 03/12] drm/i915: Move i915_gem_fini to i915_gem.c

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote: We should keep i915_gem_init/fini functions together for easier tracking of their symmetry. Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915/guc: Check that the breadcrumb irq is enabled

Quoting Michal Wajdeczko (2018-04-09 15:08:40) > On Mon, 09 Apr 2018 14:42:19 +0200, Chris Wilson > wrote: > > > Our execlists emulation for GuC requires use of the breadcrumb following > > every request as a simulcrum for the context-switch interrupt, which we > >

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable display workaround 827 for all planes, v2.

== Series Details == Series: drm/i915: Enable display workaround 827 for all planes, v2. URL : https://patchwork.freedesktop.org/series/41371/ State : warning == Summary == $ dim checkpatch origin/drm-tip b8f0788dfd3f drm/i915: Enable display workaround 827 for all planes, v2. -:58:

Re: [Intel-gfx] [PATCH] drm/i915: Enable display workaround 827 for all planes, v2.

On Mon, Apr 09, 2018 at 04:21:23PM +0200, Maarten Lankhorst wrote: > The workaround was applied only to the primary plane, but is required > on all planes. Iterate over all planes in the crtc atomic check to see > if the workaround is enabled, and only perform the actual toggling in > the pre/post

[Intel-gfx] [PATCH] drm/i915: Enable display workaround 827 for all planes, v2.

The workaround was applied only to the primary plane, but is required on all planes. Iterate over all planes in the crtc atomic check to see if the workaround is enabled, and only perform the actual toggling in the pre/post plane update functions. Changes since v1: - Track active NV12 planes in a

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Change use get_new_plane_state instead of existing plane state

== Series Details == Series: series starting with [1/4] drm/i915: Change use get_new_plane_state instead of existing plane state URL : https://patchwork.freedesktop.org/series/41370/ State : success == Summary == Series 41370v1 series starting with [1/4] drm/i915: Change use

Re: [Intel-gfx] [PATCH 15/36] drm/i915: Mark up Ironlake ips with rpm wakerefs

Quoting Sagar Arun Kamble (2018-03-16 06:04:03) > i915_mch_val() called from i915_emon_status debugfs is not protected > under rpm_get and mchdev_lock. > Can that also be updated as part of this patch. Actually, we can just do that unlocked since we know that debugfs teardown is itself

Re: [Intel-gfx] [PATCH 6/7] drm/i915/dp: abstract link config selection

On Thu, 05 Apr 2018, Manasi Navare wrote: > On Thu, Apr 05, 2018 at 05:39:04PM +0300, Jani Nikula wrote: >> For now, there's just the one link config selection, optimizing for slow >> and wide link. No functional changes. >> >> Signed-off-by: Jani Nikula

Re: [Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

On Mon, 09 Apr 2018 14:47:24 +0200, Chris Wilson wrote: Quoting Michal Wajdeczko (2018-04-09 13:23:28) As we always call intel_uc_sanitize after every call to intel_uc_fini_hw we may drop redundant call and sanitize uC from the fini_hw function. Signed-off-by:

Re: [Intel-gfx] [PATCH] drm/i915/guc: Check that the breadcrumb irq is enabled

On Mon, 09 Apr 2018 14:42:19 +0200, Chris Wilson wrote: Our execlists emulation for GuC requires use of the breadcrumb following every request as a simulcrum for the context-switch interrupt, which we then use to drive the submission tasklet. Therefore, when we

Re: [Intel-gfx] [PATCH 15/36] drm/i915: Mark up Ironlake ips with rpm wakerefs

Quoting Sagar Arun Kamble (2018-03-16 04:58:22) > > > On 3/14/2018 3:07 PM, Chris Wilson wrote: > > Currently Ironlake operates under the assumption that rpm awake (and its > > error checking is disabled). As such, we have missed a few places where we > > access registers without taking the rpm

Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

On Sun, 08 Apr 2018, Gaurav K Singh wrote: > On Geminilake, sometimes audio card is not getting > detected after reboot. This is a spurious issue happening on > Geminilake. HW codec and HD audio controller link was going > out of sync for which there was a fix in i915

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Remove last references to drm_atomic_get_existing* macros

Op 09-04-18 om 15:04 schreef Ville Syrjälä: > On Mon, Apr 09, 2018 at 02:46:55PM +0200, Maarten Lankhorst wrote: >> All the references to get_existing_state can be converted to >> get_new_state or get_old_state, which means that i915 is now >> get_existing_state free. >> >> Signed-off-by: Maarten

Re: [Intel-gfx] [PATCH 12/36] drm/i915: Merge sbi read/write into a single accessor

Quoting Sagar Arun Kamble (2018-03-16 03:39:56) > > > On 3/14/2018 3:07 PM, Chris Wilson wrote: > > Since intel_sideband_read and intel_sideband_write differ by only a > > couple of lines (depending on whether we feed the value in or out), > > merge the two into a single common accessor. > > > >

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Change use get_new_plane_state instead of existing plane state

== Series Details == Series: series starting with [1/4] drm/i915: Change use get_new_plane_state instead of existing plane state URL : https://patchwork.freedesktop.org/series/41370/ State : warning == Summary == $ dim checkpatch origin/drm-tip 591b58b45998 drm/i915: Change use

Re: [Intel-gfx] [PATCH] drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

On Mon, Apr 09, 2018 at 03:27:16PM +0300, Imre Deak wrote: > On GLK sporadic timeouts occur during PHY0 enabling. Based on logs it looks > like they happen sometime after a system suspend/resume cycle, with the > same power well enabling succeeding both before and after the failed > one and no

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Check that the breadcrumb irq is enabled

== Series Details == Series: drm/i915/guc: Check that the breadcrumb irq is enabled URL : https://patchwork.freedesktop.org/series/41368/ State : success == Summary == Series 41368v1 drm/i915/guc: Check that the breadcrumb irq is enabled

Re: [Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr

On Fri, 06 Apr 2018, Rodrigo Vivi wrote: > On Fri, Apr 06, 2018 at 10:58:51PM +0530, vathsala nagaraju wrote: >> From: Vathsala Nagaraju >> >> For psr block #9, the vbt description has moved to options [0-3] for >> TP1,TP2,TP3 Wakeup time

Re: [Intel-gfx] [PATCH 10/36] drm/i915: Replace pcu_lock with sb_lock

Quoting Sagar Arun Kamble (2018-03-15 12:06:57) > On 3/14/2018 3:07 PM, Chris Wilson wrote: > > struct intel_rps { > > + struct mutex lock; > > + > I think this lock can now become part of struct intel_gt_pm. Maybe, haven't decided yet. Anything but rps is so infrequent as not to really

Re: [Intel-gfx] [PATCH 08/36] drm/i915: Reduce RPS update frequency on Valleyview/Cherryview

Quoting Sagar Arun Kamble (2018-03-15 09:23:25) > > > On 3/14/2018 3:07 PM, Chris Wilson wrote: > > Valleyview and Cherryview update the GPU frequency via the punit, which > > is very expensive as we have to ensure the cores do not sleep during the > > comms. > But the patch 5 applies this

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/selftests: Extend partial vma coverage to check parallel creation

== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extend partial vma coverage to check parallel creation URL : https://patchwork.freedesktop.org/series/41359/ State : failure == Summary == Possible new issues: Test drv_selftest: Subgroup mock_vma:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

== Series Details == Series: drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout URL : https://patchwork.freedesktop.org/series/41366/ State : success == Summary == Series 41366v1 drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Enable display workaround 827 for all planes.

On Mon, Apr 09, 2018 at 02:46:56PM +0200, Maarten Lankhorst wrote: > The workaround was applied only to the primary plane, but is required > on all planes. Iterate over all planes in the crtc atomic check to see > if the workaround is enabled, and only perform the actual toggling in > the pre/post

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/18] drm/i915/execlists: Set queue priority from secondary port

== Series Details == Series: series starting with [01/18] drm/i915/execlists: Set queue priority from secondary port URL : https://patchwork.freedesktop.org/series/41357/ State : failure == Summary == Possible new issues: Test gem_ctx_param: Subgroup invalid-param-get:

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Remove last references to drm_atomic_get_existing* macros

On Mon, Apr 09, 2018 at 02:46:55PM +0200, Maarten Lankhorst wrote: > All the references to get_existing_state can be converted to > get_new_state or get_old_state, which means that i915 is now > get_existing_state free. > > Signed-off-by: Maarten Lankhorst >

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Remove get_existing_crtc_state

On Mon, Apr 09, 2018 at 02:46:54PM +0200, Maarten Lankhorst wrote: > get_existing_crtc_state is currently unused, get rid of it. > > Signed-off-by: Maarten Lankhorst Reviewed-by: Ville Syrjälä > --- >

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Change use get_new_plane_state instead of existing plane state

On Mon, Apr 09, 2018 at 02:46:53PM +0200, Maarten Lankhorst wrote: > The get_existing macros are deprecated and should be replaced by > get_old/new_state for clarity. > > Signed-off-by: Maarten Lankhorst > --- > drivers/gpu/drm/i915/intel_atomic.c | 5 +++-- >

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v8,01/12] drm/i915: Park before resetting the submission backend

== Series Details == Series: series starting with [v8,01/12] drm/i915: Park before resetting the submission backend URL : https://patchwork.freedesktop.org/series/41365/ State : success == Summary == Series 41365v1 series starting with [v8,01/12] drm/i915: Park before resetting the

[Intel-gfx] [PATCH 2/4] drm/i915: Remove get_existing_crtc_state

get_existing_crtc_state is currently unused, get rid of it. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_drv.h | 14 -- 1 file changed, 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h

Re: [Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

Quoting Michal Wajdeczko (2018-04-09 13:23:28) > As we always call intel_uc_sanitize after every call to > intel_uc_fini_hw we may drop redundant call and sanitize > uC from the fini_hw function. > > Signed-off-by: Michal Wajdeczko > Cc: Sagar Arun Kamble

[Intel-gfx] [PATCH 4/4] drm/i915: Enable display workaround 827 for all planes.

The workaround was applied only to the primary plane, but is required on all planes. Iterate over all planes in the crtc atomic check to see if the workaround is enabled, and only perform the actual toggling in the pre/post plane update functions. Signed-off-by: Maarten Lankhorst

[Intel-gfx] [PATCH 1/4] drm/i915: Change use get_new_plane_state instead of existing plane state

The get_existing macros are deprecated and should be replaced by get_old/new_state for clarity. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_atomic.c | 5 +++-- drivers/gpu/drm/i915/intel_drv.h| 11 ---

[Intel-gfx] [PATCH 3/4] drm/i915: Remove last references to drm_atomic_get_existing* macros

All the references to get_existing_state can be converted to get_new_state or get_old_state, which means that i915 is now get_existing_state free. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_display.c | 51

[Intel-gfx] [PATCH] drm/i915/guc: Check that the breadcrumb irq is enabled

Our execlists emulation for GuC requires use of the breadcrumb following every request as a simulcrum for the context-switch interrupt, which we then use to drive the submission tasklet. Therefore, when we unpark the engine for use with the GuC, we pin the breadcrumb interrupt to keep it enabled

Re: [Intel-gfx] [PATCH v8 06/12] drm/i915: Add i915_gem_fini_hw to i915_reset

Quoting Michal Wajdeczko (2018-04-09 13:23:26) > By calling in i915_reset only i915_gem_init_hw without previous > i915_gem_fini_hw we introduced asymmetry. Let's fix that. > > Signed-off-by: Michal Wajdeczko > Cc: Sagar Arun Kamble > Cc:

[Intel-gfx] [PATCH] drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

On GLK sporadic timeouts occur during PHY0 enabling. Based on logs it looks like they happen sometime after a system suspend/resume cycle, with the same power well enabling succeeding both before and after the failed one and no other problems observed. The current timeout in the code is not

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v6] intel-gpu-top: Rewrite the tool to be safe to use

[Adding some people to Cc for more ack/nack type feedback.] Executive question is ack or nack on replacing intel_gpu_top with a new implementation which uses only perf PMU for counter gathering. A short history on how this came to be: There was a recent external patch contribution from

[Intel-gfx] [PATCH v8 05/12] drm/i915: Add i915_gem_fini_hw to i915_gem_suspend

By calling i915_gem_init_hw in i915_gem_resume and not calling i915_gem_fini_hw in i915_gem_suspend we introduced asymmetry in init_hw/fini_hw calls. Let's fix that. Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Chris Wilson

[Intel-gfx] [PATCH v8 11/12] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c

Some functions already use i915 name instead of dev_priv. Let's rename this param in all remaining functions, except those that still use legacy macros. v2: don't forget about function descriptions (Sagar) v3: rebased Signed-off-by: Michal Wajdeczko Reviewed-by:

[Intel-gfx] [PATCH v8 12/12] HAX: Enable GuC for CI

Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c963603..53037b5 100644 ---

[Intel-gfx] [PATCH v8 10/12] drm/i915/uc: Use helper functions to detect fw load status

We don't have to check load status values. Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Chris Wilson Reviewed-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_huc.c | 2

[Intel-gfx] [PATCH v8 06/12] drm/i915: Add i915_gem_fini_hw to i915_reset

By calling in i915_reset only i915_gem_init_hw without previous i915_gem_fini_hw we introduced asymmetry. Let's fix that. Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Chris Wilson ---

[Intel-gfx] [PATCH v8 07/12] drm/i915/guc: Restore symmetric doorbell cleanup

In commit 9192d4fb811e ("drm/i915/guc: Extract doorbell creation from client allocation") we introduced asymmetry in doorbell cleanup to avoid warnings due to failed communication with already reset GuC. As we improved our reset/unload paths, we can restore symmetry in doorbell cleanup, as GuC

[Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

As we always call intel_uc_sanitize after every call to intel_uc_fini_hw we may drop redundant call and sanitize uC from the fini_hw function. Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Chris Wilson

[Intel-gfx] [PATCH v8 03/12] drm/i915: Move i915_gem_fini to i915_gem.c

We should keep i915_gem_init/fini functions together for easier tracking of their symmetry. Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.c | 20

[Intel-gfx] [PATCH v8 04/12] drm/i915: Introduce i915_gem_fini_hw for symmetry with i915_gem_init_hw

We have i915_gem_init_hw function that on failure requires some cleanup in uC and then in other places we were trying to do such cleanup directly. Let's fix that by adding i915_gem_fini_hw for nice symmetry with init_hw and call it on cleanup paths. Signed-off-by: Michal Wajdeczko

[Intel-gfx] [PATCH v8 09/12] drm/i915/uc: Use correct error code for GuC initialization failure

Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure") we believed that we correctly handle all errors encountered during GuC initialization, including special one that indicates request to run driver with disabled GPU submission (-EIO). Unfortunately since commit 121981fafe69

[Intel-gfx] [PATCH v8 02/12] drm/i915: Correctly handle error path in i915_gem_init_hw

In function gem_init_hw() we are calling uc_init_hw() but in case of error later in function, we missed to call matching uc_fini_hw() Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Chris Wilson

[Intel-gfx] [PATCH v8 01/12] drm/i915: Park before resetting the submission backend

From: Chris Wilson As different backends may have different park/unpark callbacks, we should only ever switch backends (reset_default_submission on wedge recovery, or on enabling the guc) while parked. v2: Remove the assert from the guc code, as we are currently trying

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Extend partial vma coverage to check parallel creation

== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extend partial vma coverage to check parallel creation URL : https://patchwork.freedesktop.org/series/41359/ State : success == Summary == Series 41359v1 series starting with [1/2] drm/i915/selftests: Extend partial

Re: [Intel-gfx] [PATCH v3] drm/i915/execlists: Log fence context & seqno throughout GEM_TRACE

Quoting Tvrtko Ursulin (2018-04-06 13:35:14) > From: Tvrtko Ursulin > > Include fence context and seqno in low level tracing so it is easier to > follow flows of individual requests when things go bad. > > Also added tracing on the reset side of things. > > v2: >

Re: [Intel-gfx] [PATCH 3/7] drm/i915: Keep a count of requests submitted from userspace

Quoting Tvrtko Ursulin (2018-04-09 12:43:50) > > On 09/04/2018 11:51, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-04-09 11:40:08) > >> > >> On 09/04/2018 11:27, Chris Wilson wrote: > >>> Quoting Tvrtko Ursulin (2018-04-09 11:17:04) > > On 09/04/2018 10:25, Chris Wilson wrote: >

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