From: Anusha Srivatsa
Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
then Display Driver will access the additional instances of
FIA based on pre-assigned offset in GTTMADDR space.
Each Modular FIA instance has its own IOSF Sideband Port ID
and it houses only 2 Type-C
Tiger Lake has modular FIA bit indicating if we are using it, so add to
the device info.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index
https://patchwork.freedesktop.org/series/63175/
Changes:
- Add comment explaining mapping port <-> FIA
- Add commit to apply modular FIA on TGL
Anusha Srivatsa (1):
drm/i915: Add modular FIA
Lucas De Marchi (1):
drm/i915/tgl: add modular FIA to device info
On 12/07/2019 00:51, Summers, Stuart wrote:
On Thu, 2019-07-11 at 16:59 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
This is generally much more readable than the previous implementation,
thanks! Some minor comments below...
Two issues in this code:
1.
fls() usage is incorrect
== Series Details ==
Series: drm/i915: Drop extern qualifiers from header function prototypes (rev2)
URL : https://patchwork.freedesktop.org/series/63508/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6456_full -> Patchwork_13617_full
On 07/10, Ser, Simon wrote:
> On Wed, 2019-07-10 at 15:30 +, Ser, Simon wrote:
> > Mostly LGTM, here are a few nits.
> >
> > On Wed, 2019-06-12 at 23:17 -0300, Brian Starkey wrote:
> > > To use writeback buffers as a CRC source, we need to be able to hash
> > > them. Implement a simple FVA-1a
On 07/10, Ser, Simon wrote:
> Hi,
>
> Thanks for the patch! Here are a few comments.
>
> For bonus points, it would be nice to add igt_describe descriptions of
> each sub-test.
Hi Simon,
First of all, thanks for your feedback; I already applied most of your
suggestions. I just have some inline
== Series Details ==
Series: series starting with [v5,1/2] drm/i915: Add support for retrying hotplug
URL : https://patchwork.freedesktop.org/series/63597/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6467 -> Patchwork_13632
On Thu, 2019-07-11 at 13:55 -0700, Shane McKee wrote:
> On Thu, Jul 11, 2019 at 11:05:15PM +0300, Ville Syrjälä wrote:
> > On Wed, Jul 10, 2019 at 03:14:59PM -0700, José Roberto de Souza
> > wrote:
> > > From: Imre Deak
> > >
> > > There is some scenarios that we are aware that sink probe can
>
On Thu, 2019-07-11 at 23:05 +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 03:14:59PM -0700, José Roberto de Souza
> wrote:
> > From: Imre Deak
> >
> > There is some scenarios that we are aware that sink probe can fail,
> > so lets add the infrastructure to let hotplug() hook to request
>
Right now we are aware of two cases that needs another hotplug retry:
- Unpowered type-c dongles
- HDMI slow unplug
Both have a complete explanation in the code to schedule another run
of the hotplug handler.
It could have more checks to just trigger the retry in those two
specific cases but why
From: Imre Deak
There is some scenarios that we are aware that sink probe can fail,
so lets add the infrastructure to let hotplug() hook to request
another probe after some time.
v2: Handle shared HPD pins (Imre)
v3: Rebased
v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to keep
== Series Details ==
Series: series starting with [CI,01/21] drm/i915: Add 4th pipe and transcoder
URL : https://patchwork.freedesktop.org/series/63528/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6453_full -> Patchwork_13616_full
On Thu, 2019-07-11 at 16:49 -0700, Lucas De Marchi wrote:
> On Thu, Jul 11, 2019 at 04:15:42PM -0700, Summers, Stuart wrote:
> > On Thu, 2019-07-11 at 13:58 -0700, Lucas De Marchi wrote:
> > > From: Anusha Srivatsa
> > >
> > > Some platforms may have Modular FIA. If Modular FIA is used in
> > >
On Thu, 2019-07-11 at 16:59 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
This is generally much more readable than the previous implementation,
thanks! Some minor comments below...
>
> Two issues in this code:
>
> 1.
> fls() usage is incorrect causing off by one in subslice mask
On Thu, Jul 11, 2019 at 04:15:42PM -0700, Summers, Stuart wrote:
On Thu, 2019-07-11 at 13:58 -0700, Lucas De Marchi wrote:
From: Anusha Srivatsa
Some platforms may have Modular FIA. If Modular FIA is used in the
SOC,
then Display Driver will access the additional instances of
FIA based on
On Thu, 2019-07-11 at 23:28 +, Souza, Jose wrote:
> On Fri, 2019-07-12 at 01:03 +0200, Paul Bolle wrote:
> > James Bottomley schreef op do 11-07-2019 om 15:38 [-0700]:
> > > On Thu, 2019-07-11 at 22:26 +, Souza, Jose wrote:
> > > > It eventually comes back from screen freeze? Like moving
On Thu, 2019-07-11 at 13:58 -0700, Lucas De Marchi wrote:
> From: Anusha Srivatsa
>
> Some platforms may have Modular FIA. If Modular FIA is used in the
> SOC,
> then Display Driver will access the additional instances of
> FIA based on pre-assigned offset in GTTMADDR space.
>
> Each Modular
On Thu, Jul 11, 2019 at 01:38:41PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 02:39:50PM -0700, Manasi Navare wrote:
> > On ICL+, the vertical limits for the transcoders are increased to 8192 so
> > bump up
> > limits in intel_mode_valid()
> >
> > v3:
> > * Supported starting ICL
== Series Details ==
Series: drm/i915/gtt: Use shallow dma pages for scratch
URL : https://patchwork.freedesktop.org/series/63595/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6466 -> Patchwork_13631
Summary
---
James Bottomley schreef op do 11-07-2019 om 15:38 [-0700]:
> On Thu, 2019-07-11 at 22:26 +, Souza, Jose wrote:
> > It eventually comes back from screen freeze? Like moving the mouse or
> > typing brings it back?
>
> No, it seems to be frozen for all time (at least until I got bored
> waiting,
== Series Details ==
Series: drm/i915/gtt: Use shallow dma pages for scratch
URL : https://patchwork.freedesktop.org/series/63595/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f0b680cba1f4 drm/i915/gtt: Use shallow dma pages for scratch
-:540: CHECK:MACRO_ARG_REUSE: Macro
== Series Details ==
Series: Initial support for Tiger Lake (rev8)
URL : https://patchwork.freedesktop.org/series/62726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6466 -> Patchwork_13630
Summary
---
**SUCCESS**
== Series Details ==
Series: series starting with [v4,1/2] drm/i915: Add support for retrying hotplug
URL : https://patchwork.freedesktop.org/series/63523/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6453_full -> Patchwork_13613_full
On Thu, 2019-07-11 at 22:26 +, Souza, Jose wrote:
> On Thu, 2019-07-11 at 14:57 -0700, James Bottomley wrote:
> > On Thu, 2019-07-11 at 13:28 -0700, James Bottomley wrote:
> > > I've also updated to the released 5.2 kernel and am running with
> > > the
> > > debug parameters you requested ...
== Series Details ==
Series: Initial support for Tiger Lake (rev8)
URL : https://patchwork.freedesktop.org/series/62726/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d6bd962a2eb2 drm/i915: Add 4th pipe and transcoder
95c7ae28d487 drm/i915/tgl: add initial Tiger Lake
On Thu, 2019-07-11 at 14:57 -0700, James Bottomley wrote:
> On Thu, 2019-07-11 at 13:28 -0700, James Bottomley wrote:
> > I've also updated to the released 5.2 kernel and am running with
> > the
> > debug parameters you requested ... but so far no reproduction.
>
> OK, it's happened. I've
We only use the dma pages for scratch, and so do not need to allocate
the extra storage for the shadow page directory.
v2: Refrain from reintroducing I915_PDES
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 196
== Series Details ==
Series: Modular FIA (rev4)
URL : https://patchwork.freedesktop.org/series/63175/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6465 -> Patchwork_13629
Summary
---
**SUCCESS**
No regressions
On Thu, Jul 11, 2019 at 02:35:17PM -0700, Lucas De Marchi wrote:
> Add port C to workaround to cover Tiger Lake.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Lucas De Marchi
> Reviewed-by: Rodrigo Vivi
> Link:
>
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-22-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display_power.c | 12 +---
On Thu, Jul 11, 2019 at 01:52:13PM -0700, Matt Roper wrote:
On Thu, Jul 11, 2019 at 10:31:09AM -0700, Lucas De Marchi wrote:
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/display/icl: Bump up the
vdisplay to reflect higher transcoder vertical limits
URL : https://patchwork.freedesktop.org/series/63522/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6453_full ->
On Thu, Jul 11, 2019 at 10:31:01AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A.
>
> v2 (Lucas):
> - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
> - Use crtc->dev since
On Thu, Jul 11, 2019 at 10:31:12AM -0700, Lucas De Marchi wrote:
> Make the icl function generic so it is based on phy type and can be
> applied to tgl as well.
>
> I checked if this could not apply to EHL as well, but unfortunately
> there the HPD and DDC/GMBUS pins for DDI C are mapped to TypeC
From: Anusha Srivatsa
Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
then Display Driver will access the additional instances of
FIA based on pre-assigned offset in GTTMADDR space.
Each Modular FIA instance has its own IOSF Sideband Port ID
and it houses only 2 Type-C
https://patchwork.freedesktop.org/series/63175/
Changes:
- Remove already merged patches
- Move enum phy_fia to the header and use it
Anusha Srivatsa (1):
drm/i915: Add modular FIA
drivers/gpu/drm/i915/display/intel_display.h | 6 +++
drivers/gpu/drm/i915/display/intel_tc.c | 43
On Thu, Jul 11, 2019 at 11:05:15PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 03:14:59PM -0700, José Roberto de Souza wrote:
> > From: Imre Deak
> >
> > There is some scenarios that we are aware that sink probe can fail,
> > so lets add the infrastructure to let hotplug() hook to
On Thu, Jul 11, 2019 at 12:49:35PM -0700, Nathan Ciobanu wrote:
> On Wed, Jul 10, 2019 at 03:15:00PM -0700, José Roberto de Souza wrote:
> > Right now we are aware of two cases that needs another hotplug retry:
> > - Unpowered type-c dongles
> > - HDMI slow unplug
> >
> > Both have a complete
On Thu, Jul 11, 2019 at 10:31:09AM -0700, Lucas De Marchi wrote:
> Add port C to workaround to cover Tiger Lake.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Lucas De Marchi
> Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++
>
== Series Details ==
Series: drm/i915/gt: Drop the duplicate workaround
URL : https://patchwork.freedesktop.org/series/63520/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6453_full -> Patchwork_13611_full
Summary
---
On 7/11/19 1:45 PM, Daniele Ceraolo Spurio wrote:
--- a/drivers/gpu/drm/i915/selftests/i915_selftest.c
+++ b/drivers/gpu/drm/i915/selftests/i915_selftest.c
@@ -256,7 +256,7 @@ int __i915_live_setup(void *data)
{
struct drm_i915_private *i915 = data;
- return
On Thu, Jul 11, 2019 at 10:31:07AM -0700, Lucas De Marchi wrote:
> Tiger Lake has up to 3 combo phys and 6 TC phys. Extend the helper
> conversion functions from port to phy.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5
On Thu, Jul 11, 2019 at 10:31:06AM -0700, Lucas De Marchi wrote:
> From: Vandita Kulkarni
>
> There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a
> combophy port. This results in 6 typeC ports and 3 combophy ports.
> These 6 TC ports can be DP alternate mode, DP over
--- a/drivers/gpu/drm/i915/selftests/i915_selftest.c
+++ b/drivers/gpu/drm/i915/selftests/i915_selftest.c
@@ -256,7 +256,7 @@ int __i915_live_setup(void *data)
{
struct drm_i915_private *i915 = data;
- return i915_terminally_wedged(i915);
+ return
== Series Details ==
Series: Initial support for Tiger Lake (rev6)
URL : https://patchwork.freedesktop.org/series/62726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6453_full -> Patchwork_13610_full
Summary
---
On Thu, 2019-07-11 at 20:25 +, Souza, Jose wrote:
> On Thu, 2019-07-11 at 13:11 -0700, James Bottomley wrote:
> > On Thu, 2019-07-11 at 10:29 +0100, Chris Wilson wrote:
> > > Quoting James Bottomley (2019-06-29 19:56:52)
> > > > The symptoms are really weird: the screen image is locked in
> >
On Thu, 2019-07-11 at 13:11 -0700, James Bottomley wrote:
> On Thu, 2019-07-11 at 10:29 +0100, Chris Wilson wrote:
> > Quoting James Bottomley (2019-06-29 19:56:52)
> > > The symptoms are really weird: the screen image is locked in
> > > place. The machine is still functional and if I log in over
== Series Details ==
Series: Initial support for Tiger Lake (rev7)
URL : https://patchwork.freedesktop.org/series/62726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6462 -> Patchwork_13628
Summary
---
**SUCCESS**
On Thu, 2019-07-11 at 10:29 +0100, Chris Wilson wrote:
> Quoting James Bottomley (2019-06-29 19:56:52)
> > The symptoms are really weird: the screen image is locked in
> > place. The machine is still functional and if I log in over the
> > network can do anything I like, including killing the X
On Wed, Jul 10, 2019 at 03:14:59PM -0700, José Roberto de Souza wrote:
> From: Imre Deak
>
> There is some scenarios that we are aware that sink probe can fail,
> so lets add the infrastructure to let hotplug() hook to request
> another probe after some time.
>
> v2: Handle shared HPD pins
On Thu, Jul 11, 2019 at 04:49:06PM +, Mun, Gwan-gyeong wrote:
> On Wed, 2019-07-10 at 15:58 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > With 4:2:0 output the LS clock can be half of what it is with 4:4:4.
> > Make that happen.
> >
> > Cc: Gwan-gyeong Mun
> > Signed-off-by:
On Wed, Jul 10, 2019 at 08:12:30PM +0300, Ville Syrjala wrote:
> From: "Steven Rostedt (VMware)"
>
> Currently the intel_update_plane and intel_disable_plane tracepoints record
> the address of plane->name in the ring buffer, and then when reading the
> ring buffer uses %s to get the name. The
On Wed, Jul 10, 2019 at 03:15:00PM -0700, José Roberto de Souza wrote:
> Right now we are aware of two cases that needs another hotplug retry:
> - Unpowered type-c dongles
> - HDMI slow unplug
>
> Both have a complete explanation in the code to schedule another run
> of the hotplug handler.
>
>
On Wed, Jul 10, 2019 at 03:14:59PM -0700, José Roberto de Souza wrote:
> From: Imre Deak
>
> There is some scenarios that we are aware that sink probe can fail,
> so lets add the infrastructure to let hotplug() hook to request
> another probe after some time.
>
> v2: Handle shared HPD pins
On Thu, 2019-07-11 at 16:21 +0100, Chris Wilson wrote:
> Quoting Patchwork (2019-07-11 16:16:45)
> > Possible fixes
> >
> > * igt@kms_psr@cursor_plane_move:
> > - fi-whl-u: [FAIL][7] ([fdo#107383]) -> [PASS][8] +3
> > similar issues
> >[7]:
> >
Hi James and Paul
Could you share a dmesg output of your system after the bug occur with
this kernel parameters "drm.debug=0x1e log_buf_len=4M"? Also the output
of /sys/kernel/debug/dri/0/i915_edp_psr_status
Thanks
On Wed, 2019-07-10 at 15:18 -0700, James Bottomley wrote:
> On Wed, 2019-07-10
== Series Details ==
Series: drm/i915/guc: Drop redundant ctx param from kerenldoc
URL : https://patchwork.freedesktop.org/series/63578/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6461 -> Patchwork_13627
Summary
---
== Series Details ==
Series: MCR fixes (rev2)
URL : https://patchwork.freedesktop.org/series/63457/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6461 -> Patchwork_13626
Summary
---
**SUCCESS**
No regressions
== Series Details ==
Series: Initial support for Tiger Lake (rev7)
URL : https://patchwork.freedesktop.org/series/62726/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3b308280d186 drm/i915: Add 4th pipe and transcoder
22ff20d71578 drm/i915/tgl: add initial Tiger Lake
On Thu, Jul 11, 2019 at 01:38:41PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 02:39:50PM -0700, Manasi Navare wrote:
> > On ICL+, the vertical limits for the transcoders are increased to 8192 so
> > bump up
> > limits in intel_mode_valid()
> >
> > v3:
> > * Supported starting ICL
== Series Details ==
Series: drm/i915: Copy name string into ring buffer for
intel_update/disable_plane tracepoints (rev2)
URL : https://patchwork.freedesktop.org/series/63516/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6451_full -> Patchwork_13609_full
== Series Details ==
Series: series starting with [v3] drm/i915/oa: Reconfigure contexts on the fly
(rev4)
URL : https://patchwork.freedesktop.org/series/63362/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6460 -> Patchwork_13625
From: Rodrigo Vivi
Previously, the recommended B credit for all platforms was 24 / number
of pipes, which would give 6 for newer platforms with 4 pipes. However 6
is not enough and we need 12 on these cases.
We also need a different BW credit for these platforms.
Cc: Arthur J Runyan
From: Mahesh Kumar
Assume PCH_TGP when platform is TGL.
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
Add pipe D and transcoder D to prepare for platforms having them.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.h | 4
drivers/gpu/drm/i915/i915_reg.h
From: Vandita Kulkarni
Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL
changed, but most registers remained the same, like MGPLL5_ENABLE,
MGPLL6_ENABLE. So continue to use the name from ICL.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
From: Vandita Kulkarni
Add a new pll array for Tiger Lake. The TC pll functions for type C will
be covered in later patches after its phy is implemented.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
From: Radhakrishna Sripada
Add the enum additions to TGP.
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: David Weinehall
Cc: James Ausmus
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.c | 4
== Series Details ==
Series: Associate ddc adapters with connectors
URL : https://patchwork.freedesktop.org/series/63558/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6460 -> Patchwork_13624
Summary
---
**SUCCESS**
From: Imre Deak
The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:
- Transcoder#EDP removed from power well#1 (Transcoder#A used in
low-power mode instead)
- Transcoder#A is now
From: Mahesh Kumar
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by:
From: Mahesh Kumar
This patch initializes DDI PORT A, B & C for Tiger lake. Other
TC ports need to be initialized later once corresponding code is there.
Cc: Madhav Chauhan
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h| 4 +++-
2 files changed, 10 insertions(+), 1
From: José Roberto de Souza
On Tiger Lake there is one more pipe - check if it's fused.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
2 files
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
.../drm/i915/display/intel_display_power.c| 28 +--
From: Mahesh Kumar
Add VBT-value to DDC bus pin mapping for the same.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 17 -
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3
From: José Roberto de Souza
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++--
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
v2 (Lucas): Add TODO with about DPLL4 (requested by Ville)
Cc: Vandita Kulkarni
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
Make the icl function generic so it is based on phy type and can be
applied to tgl as well.
I checked if this could not apply to EHL as well, but unfortunately
there the HPD and DDC/GMBUS pins for DDI C are mapped to TypeC Port 1
even though it doesn't have TC phy.
v2: don't add a separate
Tiger Lake has up to 3 combo phys and 6 TC phys. Extend the helper
conversion functions from port to phy.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
drivers/gpu/drm/i915/display/intel_display.h | 3 +++
2 files changed, 7 insertions(+), 1
From: Vandita Kulkarni
There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a
combophy port. This results in 6 typeC ports and 3 combophy ports.
These 6 TC ports can be DP alternate mode, DP over thunderbolt, native
DP on legacy DP connector or native HDMI on legacy connector.
From: Daniele Ceraolo Spurio
Tiger Lake is a Intel® Processor containing Intel® HD Graphics.
This is just an initial Tiger Lake definition. PCI IDs, generic support
and new features coming in following patches.
v2 (Lucas):
- Remove modular FIA - feature will be re-introduced in future
Cc:
Current list of PCI IDs for Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 10 ++
2 files changed, 11 insertions(+)
diff --git
From: José Roberto de Souza
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A.
v2 (Lucas):
- Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
- Use crtc->dev since new_crtc_state->state may be NULL on atomic
commit (suggested by Maarten)
v3
v3 of https://patchwork.freedesktop.org/series/62726/ (with the
individual patch updates in v2).
This removes the patches that can't be applied right away because of
lack of reviews and rebase the series on the just introduced enum phy.
Patches that changed too much or are new got their R-b tags
== Series Details ==
Series: drm/i915/selftests: Ensure we don't clamp a random offset to 32b (rev2)
URL : https://patchwork.freedesktop.org/series/63506/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6451_full -> Patchwork_13608_full
== Series Details ==
Series: drm/i915: Fix wrong escape clock divisor init for GLK (rev2)
URL : https://patchwork.freedesktop.org/series/63505/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6460 -> Patchwork_13623
Summary
== Series Details ==
Series: drm/i915: Join quoted strings and align them with open parenthesis
URL : https://patchwork.freedesktop.org/series/63510/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6451_full -> Patchwork_13605_full
On 7/11/19 9:24 AM, Chris Wilson wrote:
drivers/gpu/drm/i915/intel_guc_submission.c:799: warning: Excess function
parameter 'ctx' description in 'guc_client_alloc'
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
---
Acked-by: Thomas Zimmermann
Am 11.07.19 um 13:26 schrieb Andrzej Pietrasiewicz:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
> ---
> drivers/gpu/drm/ast/ast_mode.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff
Acked-by: Thomas Zimmermann
Am 11.07.19 um 13:26 schrieb Andrzej Pietrasiewicz:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
> ---
> drivers/gpu/drm/mgag200/mgag200_mode.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
On Thu, Jul 11, 2019 at 04:47:17PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
> > DSC engine on ICL supports only 8 and 10 BPC as the input
> > BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
> > Add 12 BPC support for DSC while calculating
On Wed, 2019-07-10 at 15:58 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> With 4:2:0 output the LS clock can be half of what it is with 4:4:4.
> Make that happen.
>
> Cc: Gwan-gyeong Mun
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> 1 file
On Thu, Jul 11, 2019 at 01:44:01PM +0300, Stanislav Lisovskiy wrote:
> According to Bspec clock divisor registers in GeminiLake
> should be initialized by shifting 1(<<) to amount of correspondent
> divisor. While i915 was writing all this time that value as is.
>
> Surprisingly that it by
== Series Details ==
Series: drm/edid: Add new modes from CTA-861-G
URL : https://patchwork.freedesktop.org/series/63554/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6458 -> Patchwork_13622
Summary
---
**SUCCESS**
drivers/gpu/drm/i915/intel_guc_submission.c:799: warning: Excess function
parameter 'ctx' description in 'guc_client_alloc'
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_submission.c | 2 --
1 file changed, 2 deletions(-)
diff --git
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev9)
URL : https://patchwork.freedesktop.org/series/60916/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6458 -> Patchwork_13621
Summary
---
On Mon, Jul 01, 2019 at 07:15:34PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The PFI credit programming performed during cdclk change on vlv/chv
> requires access to a register in the disp2d power well. So far
> we've abused pipe-A power domain for this, but now we have the
> more
On Mon, Jul 01, 2019 at 07:05:45PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> wm.mutex does not protect the crtc state so no point in grabbing it
> to check crtc_state->wm.need_postvbl_update.
>
> Also do a bit of s/intel_crtc/crtc/ while at it.
>
> Signed-off-by: Ville Syrjälä
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