== Series Details ==
Series: mm/i915: i915_gemfs_init() NULL dereference (rev2)
URL : https://patchwork.freedesktop.org/series/63977/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6602_full -> Patchwork_13828_full
Summary
-
On 02.08.19 07:48, John Hubbard wrote:
On 8/1/19 9:36 PM, Juergen Gross wrote:
On 02.08.19 04:19, john.hubb...@gmail.com wrote:
From: John Hubbard
...
diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
index 2f5ce7230a43..29e461dbee2d 100644
--- a/drivers/xen/privcmd.c
+++ b/drivers/
== Series Details ==
Series: drm/i915: timeline semaphore support (rev3)
URL : https://patchwork.freedesktop.org/series/61032/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6602_full -> Patchwork_13827_full
Summary
---
On 02.08.19 04:19, john.hubb...@gmail.com wrote:
From: John Hubbard
For pages that were retained via get_user_pages*(), release those pages
via the new put_user_page*() routines, instead of via put_page() or
release_pages().
This is part a tree-wide conversion, as described in commit fc1d8e7cc
== Series Details ==
Series: drm/i915/pmu: Atomically acquire the gt_pm wakeref (rev4)
URL : https://patchwork.freedesktop.org/series/64543/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6610 -> Patchwork_13845
Summary
On Thu, 2019-08-01 at 17:41 -0700, Lucas De Marchi wrote:
> On Thu, Aug 01, 2019 at 04:28:11PM -0700, Jose Souza wrote:
> > When getting the pipes attached to encoder if it is not a eDP
> > encoder
> > it iterates over all pipes and read a transcoder register.
> > But it should not read a transcode
On Thu, 2019-08-01 at 17:50 -0700, Lucas De Marchi wrote:
> On Thu, Aug 01, 2019 at 04:28:12PM -0700, Jose Souza wrote:
> > On TGL this register do not map directly to port, it was already
> > handled when setting it(TGL_TRANS_DDI_SELECT_PORT()) but not when
> > reading it.
> >
> > Cc: Lucas De Ma
On Thu, Aug 01, 2019 at 04:28:12PM -0700, Jose Souza wrote:
On TGL this register do not map directly to port, it was already
handled when setting it(TGL_TRANS_DDI_SELECT_PORT()) but not when
reading it.
Cc: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/i
On Thu, Aug 01, 2019 at 04:28:11PM -0700, Jose Souza wrote:
When getting the pipes attached to encoder if it is not a eDP encoder
it iterates over all pipes and read a transcoder register.
But it should not read a transcoder register before get its power
domain.
It was not a issue in gens older
== Series Details ==
Series: series starting with [1/2] drm/i915: Get transcoder power domain before
reading its register
URL : https://patchwork.freedesktop.org/series/64571/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6608 -> Patchwork_13844
==
== Series Details ==
Series: series starting with [1/2] drm/i915: Get transcoder power domain before
reading its register
URL : https://patchwork.freedesktop.org/series/64571/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bfb6c8381b43 drm/i915: Get transcoder power domain befo
On Thu, Aug 01, 2019 at 05:07:48PM +0200, Maarten Lankhorst wrote:
> Op 01-08-2019 om 01:24 schreef Manasi Navare:
> > Thanks Maarten for your review comments, please see my responses/questions
> > below:
> >
> > On Tue, Jul 30, 2019 at 12:53:30PM +0200, Maarten Lankhorst wrote:
> >> Op 24-06-2019
Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can atomically test and acquire that wakeref instead.
v2: Take engine->wakeref for engine sampling
Signed-off-by: Chris Wilson
Cc: Tvrtko
On TGL this register do not map directly to port, it was already
handled when setting it(TGL_TRANS_DDI_SELECT_PORT()) but not when
reading it.
Cc: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
1 file changed, 8 insertions(
When getting the pipes attached to encoder if it is not a eDP encoder
it iterates over all pipes and read a transcoder register.
But it should not read a transcoder register before get its power
domain.
It was not a issue in gens older than 12 because if it only had
port A connected it would be at
== Series Details ==
Series: add more probe failures (rev5)
URL : https://patchwork.freedesktop.org/series/64390/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6607 -> Patchwork_13843
Summary
---
**FAILURE**
Serio
== Series Details ==
Series: series starting with [1/2] drm/i915/pmu: Atomically acquire the gt_pm
wakeref
URL : https://patchwork.freedesktop.org/series/64562/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6607 -> Patchwork_13842
=
On Tue, Jul 30, 2019 at 12:21:51PM +0100, Chris Wilson wrote:
> Recently discovered in commit bdae33b8b82b ("drm/i915: Use maximum write
> flush for pwrite_gtt") was that we needed to our full write barrier
> before changing the GGTT PTE to ensure that our indirect writes through
> the GTT landed b
== Series Details ==
Series: Force spin-batch to cause a hang as required
URL : https://patchwork.freedesktop.org/series/64495/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6590_full -> IGTPW_3311_full
Summary
---
*
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/pmu: Make more struct i915_pmu
centric
URL : https://patchwork.freedesktop.org/series/64557/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6606 -> Patchwork_13841
=
With i915 added to i915_inject_probe_failure we can use dedicated
printk when injecting artificial load failure.
Also make this function look like other i915 functions that return
error code and make it more flexible to return any provided error
code instead of previously assumed -ENODEV.
Signed-
v3: fix Gen9 issue discovered by the v2
v4: rebased
Michal Wajdeczko (3):
drm/i915: Add i915 to i915_inject_probe_failure
drm/i915/uc: Inject probe errors into intel_uc_init_hw
drm/i915/wopcm: Don't fail on WOPCM partitioning failure
.../gpu/drm/i915/display/intel_connector.c| 2 +-
d
We don't have to immediately fail on WOPCM partitioning, we can wait
until we will start programming WOPCM registers. This should give us
more options if we decide to restore fallback in case of GuC failures.
v3: rebased
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilso
Inject probe errors into intel_uc_init_hw to make sure we
correctly handle any uC initialization failure.
To avoid complains from CI about injected errors use
i915_probe_error to lower message level.
v2: _sanitize instead _reset to correctly handle Gen9 retries
Signed-off-by: Michal Wajdeczko
C
== Series Details ==
Series: add more probe failures (rev4)
URL : https://patchwork.freedesktop.org/series/64390/
State : failure
== Summary ==
Applying: drm/i915: Add i915 to i915_inject_probe_failure
Applying: drm/i915/uc: Inject probe errors into intel_uc_init_hw
Applying: drm/i915/wopcm: D
Quoting Patchwork (2019-08-01 22:22:58)
> == Series Details ==
>
> Series: series starting with [1/5] drm/i915/pmu: Make more struct i915_pmu
> centric (rev3)
> URL : https://patchwork.freedesktop.org/series/64550/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6605
== Series Details ==
Series: series starting with [1/5] drm/i915/pmu: Make more struct i915_pmu
centric (rev3)
URL : https://patchwork.freedesktop.org/series/64550/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13839
=
== Series Details ==
Series: drm/i915/pmu: Atomically acquire the gt_pm wakeref (rev3)
URL : https://patchwork.freedesktop.org/series/64543/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13838
Summary
== Series Details ==
Series: Don't sanitize enable_guc (rev4)
URL : https://patchwork.freedesktop.org/series/64446/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13837
Summary
---
**SUCCESS**
No
Quoting Kumar Valsan, Prathap (2019-08-01 21:33:44)
> On Tue, Jul 30, 2019 at 12:21:51PM +0100, Chris Wilson wrote:
> > Recently discovered in commit bdae33b8b82b ("drm/i915: Use maximum write
> > flush for pwrite_gtt") was that we needed to our full write barrier
> > before changing the GGTT PTE t
On Tue, Jul 30, 2019 at 12:21:51PM +0100, Chris Wilson wrote:
> Recently discovered in commit bdae33b8b82b ("drm/i915: Use maximum write
> flush for pwrite_gtt") was that we needed to our full write barrier
> before changing the GGTT PTE to ensure that our indirect writes through
> the GTT landed b
Hi Dave and Daniel,
Here goes the first pull request targeting 5.4.
It mostly comes with a lot of platform enabling patches and reworks
and simplification around locking mechanisms, ppgtt allocation, engines
and intel_gt in general.
There were 2 silent backmerges that should be transparent for y
== Series Details ==
Series: drm/i915: Drop the fudge warning on ring restart for ctg/elk
URL : https://patchwork.freedesktop.org/series/64546/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13836
Summary
-
Quoting Chris Wilson (2019-08-01 19:26:57)
> As we track when we put the GT device to sleep upon idling, we can use
> that callback to sample the current rc6 counters and record the
> timestamp for estimating samples after that point while asleep.
>
Bugzilla: https://bugs.freedesktop.org/show_bug
== Series Details ==
Series: Revert "drm/vgem: fix cache synchronization on arm/arm64"
URL : https://patchwork.freedesktop.org/series/64544/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13835
Summary
== Series Details ==
Series: drm/i915/selftests: Pass intel_context to igt_spinner (rev3)
URL : https://patchwork.freedesktop.org/series/64440/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6587_full -> Patchwork_13818_full
== Series Details ==
Series: Revert "drm/vgem: fix cache synchronization on arm/arm64"
URL : https://patchwork.freedesktop.org/series/64544/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
18f70bceaf5b Revert "drm/vgem: fix cache synchronization on arm/arm64"
-:52: CHECK:OPEN_END
== Series Details ==
Series: HDCP2.2 Phase II (rev14)
URL : https://patchwork.freedesktop.org/series/57232/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13834
Summary
---
**FAILURE**
Serious unk
Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can atomically test and acquire that wakeref instead.
v2: Take engine->wakeref for engine sampling
Signed-off-by: Chris Wilson
Cc: Tvrtko
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 ++-
On 2019-08-01 5:51 a.m., Pekka Paalanen wrote:
> On Tue, 16 Jul 2019 14:59:58 +
> "Li, Sun peng (Leo)" wrote:
>
>> On 2019-07-11 3:29 a.m., Pekka Paalanen wrote:
>>> Wait, one can write udev rules for connectors and stuff?
>>> How? What can they do?
>>
>> I was using it to generate user-f
== Series Details ==
Series: HDCP2.2 Phase II (rev14)
URL : https://patchwork.freedesktop.org/series/57232/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ce79e1d0d5a1 drm: Add Content protection type property
-:146: CHECK:LINE_SPACING: Please use a blank line after
function/st
Quoting Tvrtko Ursulin (2019-08-01 18:24:50)
>
> On 30/07/2019 12:21, Chris Wilson wrote:
> > @@ -224,8 +283,15 @@ int i915_active_ref(struct i915_active *ref,
> > goto out;
> > }
> >
> > - if (!i915_active_request_isset(active))
> > - atomic_inc(&ref->count)
Quoting Sergey Senozhatsky (2019-07-31 17:48:29)
> @@ -36,19 +38,35 @@ int i915_gemfs_init(struct drm_i915_private *i915)
> struct super_block *sb = gemfs->mnt_sb;
> /* FIXME: Disabled until we get W/A for read BW issue. */
> char options[] = "huge=ne
On 30/07/2019 12:21, Chris Wilson wrote:
By placing our idle-barriers in the i915_active fence tree, we expose
those for reuse by other components that are issuing requests along the
kernel_context. Reusing the proto-barrier active_node is perfectly fine
as the new request implies a context-swit
== Series Details ==
Series: drm/i915/icl: Remove DDI IO power domain from PG3 power domains
URL : https://patchwork.freedesktop.org/series/64465/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6586_full -> Patchwork_13816_full
==
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/gt: Move gt_cleanup_early out of
gem_cleanup_early
URL : https://patchwork.freedesktop.org/series/64522/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6603 -> Patchwork_13832
=
Quoting Tvrtko Ursulin (2019-08-01 17:22:27)
>
> On 01/08/2019 17:00, Chris Wilson wrote:
> Who kidnapped real Chris? :D We could merge the mask clearing and reduce
> pin to one conditional and one and, shift, or. :)
Don't worry in about 24 patches time, we can remove the branches.
-Chris
__
== Series Details ==
Series: series starting with [1/2] drm/i915: Compute has_drrs after compute
has_psr
URL : https://patchwork.freedesktop.org/series/64516/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6603 -> Patchwork_13831
===
From: Tvrtko Ursulin
RC6 is a GT state so make the function parameter reflect that.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/dr
From: Tvrtko Ursulin
Engines and frequencies are a GT thing so adjust sampling routines to
match.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 43 ++---
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a
From: Tvrtko Ursulin
Drops one macro using implicit dev_priv.
v2:
* Use ENGINE_READ_FW. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu
From: Tvrtko Ursulin
Just tidy the code a bit by removing a sea of overly verbose i915->pmu.*.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 194 +---
1 file changed, 104 insertions(+), 90 deletions(-)
diff --git a/d
On 01/08/2019 17:00, Chris Wilson wrote:
Quoting Chris Wilson (2019-08-01 16:48:33)
Quoting Tvrtko Ursulin (2019-08-01 16:29:53)
For instance Icelake engine dependent stuff sneaked into
intel_lrc.c/lrc_desriptors at some point, which is also against the
spirit of caching. If we were to move th
On Thu, 01 Aug 2019 17:27:22 +0200, Chris Wilson
wrote:
<7> [229.655762] [drm:intel_uc_fw_upload [i915]] HuC fw load
i915/kbl_huc_ver02_00_1810.bin
<7> [229.656489] [drm:intel_uc_fw_upload [i915]] HuC fw xfer completed
<6> [229.656490] [drm] HuC: Loaded firmware
i915/kbl_huc_ver02_00_181
With i915 added to i915_inject_probe_failure we can use dedicated
printk when injecting artificial load failure.
Also make this function look like other i915 functions that return
error code and make it more flexible to return any provided error
code instead of previously assumed -ENODEV.
Signed-
Inject probe errors into intel_uc_init_hw to make sure we
correctly handle any uC initialization failure.
To avoid complains from CI about injected errors use
i915_probe_error to lower message level.
v2: _sanitize instead _reset to correctly handle Gen9 retries
Signed-off-by: Michal Wajdeczko
C
v3: fix Gen9 issue discovered by the v2
Michal Wajdeczko (3):
drm/i915: Add i915 to i915_inject_probe_failure
drm/i915/uc: Inject probe errors into intel_uc_init_hw
drm/i915/wopcm: Don't fail on WOPCM partitioning failure
.../gpu/drm/i915/display/intel_connector.c| 2 +-
drivers/gpu/d
We don't have to immediately fail on WOPCM partitioning, we can wait
until we will start programming WOPCM registers. This should give us
more options if we decide to restore fallback in case of GuC failures.
v2: rebased
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilso
Quoting Chris Wilson (2019-08-01 16:48:33)
> Quoting Tvrtko Ursulin (2019-08-01 16:29:53)
> > For instance Icelake engine dependent stuff sneaked into
> > intel_lrc.c/lrc_desriptors at some point, which is also against the
> > spirit of caching. If we were to move the cached value in ce then we
From: Tvrtko Ursulin
With discrete graphics system can have both integrated and discrete GPU
handled by i915.
Currently we use a fixed name ("i915") when registering as the uncore PMU
provider which stops working in this case.
To fix this we add the PCI device name string to non-integrated devi
Quoting Tvrtko Ursulin (2019-08-01 16:29:53)
>
> On 01/08/2019 12:13, Chris Wilson wrote:
> > Quoting Chris Wilson (2019-08-01 11:57:06)
> >> Quoting Tvrtko Ursulin (2019-08-01 09:53:15)
> >>> We could store it in ce then. We already have well defined control
> >>> points for when vm changes when
Quoting Tvrtko Ursulin (2019-08-01 16:08:04)
> @@ -1095,6 +1113,9 @@ void i915_pmu_register(struct drm_i915_private *i915)
>
> err_unreg:
> perf_pmu_unregister(&pmu->base);
> +err_name:
> + if (!is_igp(i915->drm.pdev))
> + kfree_const(pmu->name);
With the kfree_const
On 01/08/2019 18:16, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-08-01 15:29:34)
On 31/07/2019 23:03, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-31 15:07:33)
...
I think I have convinced myself that with the split between wait before,
signal after combined with the rule th
On 01/08/2019 16:20, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-08-01 16:10:14)
On 01/08/2019 15:54, Chris Wilson wrote:
Works for me, I wonder what PeterZ will say...
In what sense?
Just wondering if he has a plan for hotpluggable pmu devices. I can
certainly imagine his surprise i
On 01/08/2019 12:13, Chris Wilson wrote:
Quoting Chris Wilson (2019-08-01 11:57:06)
Quoting Tvrtko Ursulin (2019-08-01 09:53:15)
We could store it in ce then. We already have well defined control
points for when vm changes when all are updated.
We are storing it in ce; it's not like we recom
Quoting Patchwork (2019-08-01 16:22:20)
> == Series Details ==
>
> Series: add more probe failures (rev3)
> URL : https://patchwork.freedesktop.org/series/64390/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6602 -> Patchwork_13830
> =
Quoting Tvrtko Ursulin (2019-08-01 15:55:29)
>
> On 01/08/2019 15:39, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-08-01 15:21:17)
> >> I guess I'll be rebasing mine, at some point. :)
> >
> > I anticipated you merging it at some point.
>
> This patch to my series or what?
Your series t
== Series Details ==
Series: add more probe failures (rev3)
URL : https://patchwork.freedesktop.org/series/64390/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6602 -> Patchwork_13830
Summary
---
**FAILURE**
Serio
Quoting Tvrtko Ursulin (2019-08-01 16:10:14)
>
> On 01/08/2019 15:54, Chris Wilson wrote:
> > Works for me, I wonder what PeterZ will say...
>
> In what sense?
Just wondering if he has a plan for hotpluggable pmu devices. I can
certainly imagine his surprise in the future when he finds an adhoc
Quoting Lionel Landwerlin (2019-08-01 15:29:34)
> On 31/07/2019 23:03, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2019-07-31 15:07:33)
> >> -static struct drm_syncobj **
> >> -get_fence_array(struct drm_i915_gem_execbuffer2 *args,
> >> - struct drm_file *file)
> >> +static str
== Series Details ==
Series: Initial TGL submission changes
URL : https://patchwork.freedesktop.org/series/64461/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6586_full -> Patchwork_13815_full
Summary
---
**SUCCESS*
On 01/08/2019 15:54, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-08-01 15:17:32)
From: Tvrtko Ursulin
With discrete graphics system can have both integrated and discrete GPU
handled by i915.
Currently we use a fixed name ("i915") when registering as the uncore PMU
provider which stops w
Pushed to dinq. Thanks Jose for the review.
Matt
On Thu, Aug 01, 2019 at 01:19:04PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ehl: Don't forget to handle port C's hotplug interrupts
> (rev2)
> URL : https://patchwork.freedesktop.org/series/64452/
> State : success
From: Tvrtko Ursulin
With discrete graphics system can have both integrated and discrete GPU
handled by i915.
Currently we use a fixed name ("i915") when registering as the uncore PMU
provider which stops working in this case.
To fix this we add the PCI device name string to non-integrated devi
Op 01-08-2019 om 01:24 schreef Manasi Navare:
> Thanks Maarten for your review comments, please see my responses/questions
> below:
>
> On Tue, Jul 30, 2019 at 12:53:30PM +0200, Maarten Lankhorst wrote:
>> Op 24-06-2019 om 23:08 schreef Manasi Navare:
>>> As per the display enable sequence, we nee
== Series Details ==
Series: mm/i915: i915_gemfs_init() NULL dereference (rev2)
URL : https://patchwork.freedesktop.org/series/63977/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6602 -> Patchwork_13828
Summary
---
On 01/08/2019 15:39, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-08-01 15:21:17)
On 01/08/2019 13:20, Chris Wilson wrote:
Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can ato
Quoting Tvrtko Ursulin (2019-08-01 15:17:32)
> From: Tvrtko Ursulin
>
> With discrete graphics system can have both integrated and discrete GPU
> handled by i915.
>
> Currently we use a fixed name ("i915") when registering as the uncore PMU
> provider which stops working in this case.
>
> To fi
== Series Details ==
Series: series starting with [01/13] drm/amdgpu: Provide ddc symlink in dm
connector's sysfs directory
URL : https://patchwork.freedesktop.org/series/64510/
State : failure
== Summary ==
Applying: drm/amdgpu: Provide ddc symlink in dm connector's sysfs directory
Applying:
Quoting Tvrtko Ursulin (2019-08-01 15:17:31)
> From: Tvrtko Ursulin
>
> RC6 is a GT state so make the function parameter reflect that.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_pmu.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git
Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can atomically test and acquire that wakeref instead.
v2: Take engine->wakeref for engine sampling
Signed-off-by: Chris Wilson
Cc: Tvrtko
Quoting Tvrtko Ursulin (2019-08-01 15:21:17)
>
> On 01/08/2019 13:20, Chris Wilson wrote:
> > Currently, we only sample if the intel_gt is awake, but we acquire our
> > own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
> > own wakeref, we can atomically test and acquire that
== Series Details ==
Series: drm/i915: timeline semaphore support (rev3)
URL : https://patchwork.freedesktop.org/series/61032/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6602 -> Patchwork_13827
Summary
---
**SUCCE
On 31/07/2019 23:03, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-31 15:07:33)
-static struct drm_syncobj **
-get_fence_array(struct drm_i915_gem_execbuffer2 *args,
- struct drm_file *file)
+static struct i915_eb_fences *
+get_timeline_fence_array(struct i915_execbuffer *
On 01/08/2019 13:20, Chris Wilson wrote:
Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can atomically test and acquire that wakeref instead.
Signed-off-by: Chris Wilson
Cc: Tvrtko U
Hi Matthew,
On Thu, Aug 01, 2019 at 01:16:34PM +0100, Matthew Nicholson wrote:
> [Resending as plain text email with attachments.]
>
> Hi,
> The kernel version testing I'm testing on is: v5.2.4-arch1
> I have disabled gmd, which seems to struggle with not being able to
> configure displays and b
From: Tvrtko Ursulin
Drops one macro using implicit dev_priv.
v2:
* Use ENGINE_READ_FW. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu
From: Tvrtko Ursulin
Just tidy the code a bit by removing a sea of overly verbose i915->pmu.*.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 194 +---
1 file changed, 104 insertions(+), 90 deletions(-)
diff --git a/d
From: Tvrtko Ursulin
RC6 is a GT state so make the function parameter reflect that.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu
From: Tvrtko Ursulin
Engines and frequencies are a GT thing so adjust sampling routines to
match.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 43 ++---
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a
From: Tvrtko Ursulin
With discrete graphics system can have both integrated and discrete GPU
handled by i915.
Currently we use a fixed name ("i915") when registering as the uncore PMU
provider which stops working in this case.
To fix this we add the PCI device name string to non-integrated devi
== Series Details ==
Series: series starting with [v7,1/4] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/64457/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6586_full -> Patchwork_13813_full
==
As we already track GuC/HuC uses by other means than modparam
there is no point in sanitizing it. Just scan modparam for
major discrepancies between what was requested vs actual.
v2: rebased, reworded info messages
v3: oops
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wi
== Series Details ==
Series: drm/i915/ehl: Don't forget to handle port C's hotplug interrupts (rev2)
URL : https://patchwork.freedesktop.org/series/64452/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6586_full -> Patchwork_13812_full
==
On Thu, 01 Aug 2019 00:33:21 +0200, Michal Wajdeczko
wrote:
+ if (i915_modparams.enable_guc & ~(ENABLE_GUC_SUBMISSION ||
+ ENABLE_GUC_LOAD_HUC))
oops, again
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Since we have already stopped the ring, cleared the ring, disabled the
ring (and verifying the ring is clear), a later debug message that the
ring is no longer clear serves no function. It appears it restarts
anyway, and we verify that the ring started correctly afterwards.
Signed-off-by: Chris Wi
commit 7e9e5ead55be ("drm/vgem: fix cache synchronization on arm/arm64")
broke all of the !llc i915-vgem coherency tests in CI, and left the HW
very, very unhappy (which is even more scary).
Fixes: 7e9e5ead55be ("drm/vgem: fix cache synchronization on arm/arm64")
Signed-off-by: Chris Wilson
Cc: D
Quoting Jani Nikula (2019-07-30 12:34:32)
> Update the generated files to make the headers self-contained, switch to
> the kernel preferred SPDX comment format, and update the copyright
> year. Also add the Makefile stanza to run header tests on the files.
>
> Other changes produced by gputop i915
Quoting Jani Nikula (2019-07-30 12:34:31)
> Add the SPDX headers.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/Makefile | 2 ++
> drivers/gpu/drm/i915/gem/Makefile | 2 ++
> drivers/gpu/drm/i915/gt/Makefile | 2 ++
> drivers/gpu/drm/i915/gt/uc/Makefile | 2 ++
>
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