On 8/23/22 5:12 AM, Kees Cook wrote:
On Tue, Aug 23, 2022 at 04:32:10AM +0900, Gwan-gyeong Mun wrote:
On 8/22/22 11:05 PM, Andrzej Hajda wrote:
On 18.08.2022 02:12, Kees Cook wrote:
On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
[...]
+#define safe_conversion(ptr, value) ({
== Series Details ==
Series: drm/i915/combo_phy: Set DCC_MODE to one time update mode
URL : https://patchwork.freedesktop.org/series/107551/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12009_full -> Patchwork_107551v1_full
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12009_full -> Patchwork_107550v1_full
OA reports in the OA buffer contain an OA timestamp field that helps
user calculate delta between 2 OA reports. The calculation relies on the
CS timestamp frequency to convert the timestamp value to nanoseconds.
The CS timestamp frequency is a function of the CTC_SHIFT value in
RPM_CONFIG0.
In
From: Vinay Belgaumkar
There is a w/a to reset RCS/CCS before it goes into RC6. This breaks
OA. Fix it by disabling RC6.
Signed-off-by: Vinay Belgaumkar
---
.../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 9
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 45 +++
Disable Clock gating in EU when gathering the events so that EU events
are not lost.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/i915_perf.c| 23 +++
2 files changed, 24 insertions(+)
diff --git
Now that OA formats come in flavor of 64 bit reports, the report header
has 64 bit report-id, timestamp, context-id and gpu-ticks fields. When
filtering these reports, use the right width for these fields.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 109
User passes uabi engine class and instance to the perf OA interface. Use
gt corresponding to the engine to pin the buffers to the right ggtt.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
DG2 introduces 64 bit counters and OA reports that have 64 bit values
for fields in the report header - report_id, timestamp, context_id and
gpu ticks. i915 uses report_id, timestamp and context_id to check for
valid reports.
In some DG2 variants, only the lower dwords for timestamp, report_id
DG2 introduces OA reports with 64 bit report header fields. Perf OA
would need more information about the OA format in order to process such
reports. Store all OA format info in oa_buffer instead of just the size
and format-id.
Signed-off-by: Umesh Nerlige Ramappa
---
If a drm client is killed, then hw contexts used by the client are reset
immediately. This reset clears the EU flex counter configuration. If an
OA use case is running in parallel, it would start seeing zeroed eu
counter values following the reset even if the drm client is restarted.
Save/restore
Make perf part of gt as the OAG buffer is specific to a gt. The refactor
eventually simplifies programming the right OA buffer and the right HW
registers when supporting multiple gts.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
XEHPSDV and DG2 provide a way to configure bytes per clock vs commands
per clock reporting. Enable command per clock setting on enabling OA.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_pci.c | 1 +
With multi-gt, user can access multiple OA buffers concurrently. Use
stream->lock instead of gt->perf.lock to serialize file operations.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 31 --
drivers/gpu/drm/i915/i915_perf_types.h | 5
DG2 has a new feature to supports OA buffer sizes up to 128Mb by
toggling a bit in OA_DEBUG. This would eventually be a user configurable
parameter. Use OA buffer vma size in all calculations with some helpers.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 47
On DG2 A0, the OAR report format is buggy. Workaround is to not use it
for A0. For A0, remove the OAR format from the bitmask of supported
formats.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 5 +
1 file changed, 5 insertions(+)
diff --git
Predication for batch buffer commands changed in XEHPSDV.
MI_BATCH_BUFFER_START predicates based on MI_SET_PREDICATE_RESULT
register. The MI_SET_PREDICATE_RESULT register can only be modified
with MI_SET_PREDICATE command. When configured, the MI_SET_PREDICATE
command sets MI_SET_PREDICATE_RESULT
Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 149 ++-
drivers/gpu/drm/i915/i915_perf_oa_regs.h | 2 +-
2 files
Add OA format support for DG2 and various fixes for DG2.
The below 2 patches have uapi changes:
drm/i915/perf: Add OA formats for DG2
drm/i915/perf: Apply Wa_18013179988
Test-with: 20220822235657.280702-1-umesh.nerlige.rama...@intel.com
Signed-off-by: Umesh Nerlige Ramappa
Umesh Nerlige
With GuC mode of submission, GuC is in control of defining the context id field
that is part of the OA reports. To filter reports, UMD and KMD must know what sw
context id was chosen by GuC. There is not interface between KMD and GuC to
determine this, so read the upper-dword of EXECLIST_STATUS to
Add new OA formats for DG2. Some of the newer OA formats are not
multples of 64 bytes and are not powers of 2. For those formats, adjust
hw_tail accordingly when checking for new reports.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 63
On 2022.08.22 17:50:33 +, Sean Christopherson wrote:
> +GVT folks
>
> On Sun, Aug 21, 2022, bugzilla-dae...@kernel.org wrote:
> > https://bugzilla.kernel.org/show_bug.cgi?id=216388
> >
> > Bug ID: 216388
> >Summary: On Host, kernel errors in KVM, on guests, it shows
== Series Details ==
Series: Add DP MST DSC support to i915 (rev7)
URL : https://patchwork.freedesktop.org/series/101492/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12009_full -> Patchwork_101492v7_full
Summary
---
On Tue, Feb 01, 2022 at 04:33:54PM +0100, Lukasz Bartosik wrote:
> From: Łukasz Bartosik
>
> Asus chromebook CX550 crashes during boot on v5.17-rc1 kernel.
> The root cause is null pointer defeference of bi_next
> in tgl_get_bw_info() in drivers/gpu/drm/i915/display/intel_bw.c.
>
> BUG: kernel
On Tue, Aug 23, 2022 at 04:32:10AM +0900, Gwan-gyeong Mun wrote:
> On 8/22/22 11:05 PM, Andrzej Hajda wrote:
> > On 18.08.2022 02:12, Kees Cook wrote:
> > > On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
> > > > [...]
> > > > > +#define safe_conversion(ptr, value) ({ \
> > > > > +
== Series Details ==
Series: Enable Pipewriteback Framework
URL : https://patchwork.freedesktop.org/series/107573/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12012 -> Patchwork_107573v1
Summary
---
**SUCCESS**
On 8/22/22 11:05 PM, Andrzej Hajda wrote:
On 18.08.2022 02:12, Kees Cook wrote:
On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
Hi Kees,
would you mind taking a look at this patch?
Hi! Thanks for the heads-up!
Thanks,
Andi
On Tue, Aug 16, 2022 at 06:35:18PM +0900,
From: Suraj Kandpal
Adding WD Types, WD transcoder to enum list and WD Transcoder offsets.
Adding i915 register definitions related to WD transcoder
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 6 +
.../drm/i915/display/intel_display_types.h| 1 +
From: Suraj Kandpal
Adding support for writeback transcoder to start capturing frames using
interrupt mechanism
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
From: Suraj Kandpal
Changing intel_connector iterators as with writeback introduction
not all drm_connector will be embedded within intel_connector.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 7 ++---
.../drm/i915/display/intel_display_types.h| 26
A patch series was floated in the drm mailing list which aimed to change
the drm_connector and drm_encoder fields to pointer in the
drm_connector_writeback structure, this received a huge pushback from
the community but since i915 expects each connector present in the
drm_device list to be a
On Mon, Aug 22, 2022 at 11:12:15AM +0800, Zhenyu Wang wrote:
>
> (resend after fixing sign-off after rebase)
>
> Hi,
>
> Here's one gvt-fixes pull for 6.0-rc. Major one is Cometlake
> regression fix for mmio table rework, and others are left kernel doc
> fixes not pushed yet.
Pulled, thanks!
== Series Details ==
Series: drm/i915/guc/slpc: Allow SLPC to use efficient frequency (rev5)
URL : https://patchwork.freedesktop.org/series/107101/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12011 -> Patchwork_107101v5
On Fri, Jul 22, 2022 at 02:51:42PM +0200, Andrzej Hajda wrote:
> HPD events during driver removal can be generated by hardware and
> software frameworks - drm_dp_mst, the former we can avoid by disabling
> interrupts, the latter can be triggered by any drm_dp_mst transaction,
> and this is too
On Fri, Jul 22, 2022 at 02:51:41PM +0200, Andrzej Hajda wrote:
> HPD event after fbdev unregistration can cause registration of deferred
> fbdev which will not be unregistered later, causing use-after-free.
> To avoid it HPD handling should be suspended before fbdev unregistration.
>
> It should
On Fri, Jul 22, 2022 at 02:51:40PM +0200, Andrzej Hajda wrote:
> i915->hotplug.dig_port_work can be queued from intel_hpd_irq_handler
> called by IRQ handler or by intel_hpd_trigger_irq called from dp_mst.
> Since dp_mst is suspended after irq handler uninstall, a cleaner approach
> is to cancel
== Series Details ==
Series: drm/i915/backlight: Disable pps power hook for aux based backlight
URL : https://patchwork.freedesktop.org/series/107555/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12011 -> Patchwork_107555v1
On 22.08.2022 16:05, Andrzej Hajda wrote:
On 18.08.2022 02:12, Kees Cook wrote:
On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
Hi Kees,
would you mind taking a look at this patch?
Hi! Thanks for the heads-up!
Thanks,
Andi
On Tue, Aug 16, 2022 at 06:35:18PM +0900,
Pps power hook seems to be problematic for backlight controlled via
aux channel. Disable it for such cases.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3657
Signed-off-by: Jouni Högander
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_backlight.c | 11
On 18.08.2022 02:12, Kees Cook wrote:
On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
Hi Kees,
would you mind taking a look at this patch?
Hi! Thanks for the heads-up!
Thanks,
Andi
On Tue, Aug 16, 2022 at 06:35:18PM +0900, Gwan-gyeong Mun wrote:
It moves overflows_type
== Series Details ==
Series: drm/i915/combo_phy: Set DCC_MODE to one time update mode
URL : https://patchwork.freedesktop.org/series/107551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12009 -> Patchwork_107551v1
Summary
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12009 -> Patchwork_107550v1
== Series Details ==
Series: Add DP MST DSC support to i915 (rev7)
URL : https://patchwork.freedesktop.org/series/101492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12009 -> Patchwork_101492v7
Summary
---
In a kexec quick reboot path, the dying cpus are still on
cpu_online_mask. During the teardown of cpu, a subsystem needs to
migrate its broker to a real online cpu.
This patch replaces cpumask_any_but(cpu_online_mask, cpu) in a teardown
procedure with cpumask_not_dying_but(cpu_online_mask, cpu).
As per Bspec:49291 update, the DCC Mode select is to be set to one time
update mode, instead of continuous DCC calibration mode for Display > 12
combo phy.
This change is required to avoid glitches that occur, during on the fly
updates to DCC code, with continuous mode, resulting in flickers seen
The Bspec:49291 is now changed to reflect that for all platforms the
DCC_MODE will be programmed to DCC_MODE_SELECT_ONCE,
rather than DCC_MODE_SELECT_CONTINUOUSLY.
I will send new patch for the same.
Regards,
Ankit
On 8/10/2022 8:26 PM, Ankit Nautiyal wrote:
Wa_22012718247 : When Display
On Wed, 17 Aug 2022, Kees Cook wrote:
> On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
>> Hi Kees,
>>
>> would you mind taking a look at this patch?
>
> Hi! Thanks for the heads-up!
Thanks for your review. This actually reaffirms my belief that we need
to get these macros out of
During FRL bandwidth check for downstream HDMI2.1 sink,
the min BPC supported is incorrectly taken for DP, and the check does
not consider ybcr420 only modes.
This patch fixes the bandwidth calculation similar to the TMDS case, by
taking min 8Bpc and considering Ycbcr420 only modes.
For cases where DP has HDMI2.1 sink and FRL Link issues are detected,
reset the flag to state FRL trained status before restarting FRL
training.
Fixes: 9488a030ac91 ("drm/i915: Add support for enabling link status and
recovery")
Cc: Swati Sharma
Cc: Ankit Nautiyal
Cc: Uma Shankar (v2)
Cc:
Currently we use the highest input BPC supported by DP sink while using
DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports
DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same
input BPC that is used between Source and the PCON without DSC, which
might not
Add helper function to check if Downstream HDMI 2.1 sink supports
DSC1.2.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch:
-uses the members of intel_dp->dfp to only store the
format conversion capabilities of the DP device.
-adds new members to crtc_state to help configure the DFP
output related
This series fixes issues faced when HDMI2.1 sink connected via HDMI2.1
PCON does not support DSC, and other minor HDMI2.1 PCON
fixes/refactoring.
Patch 1 Adds helper to check HDMI2.1 DSC1.2
Patch 2 resets 'frl trained' flag before restarting FRL training.
Patch 3 Pulls the decision making to use
On Mon, 22 Aug 2022, "Nautiyal, Ankit K" wrote:
> On 8/22/2022 3:32 PM, Jani Nikula wrote:
>> On Mon, 22 Aug 2022, "Nautiyal, Ankit K" wrote:
>>> LGTM.
>>>
>>> Reviewed-by: Ankit Nautiyal
>> Thanks; does this apply to both patches?
>
> I have given RB on the other patch separately.
Thanks,
On 8/22/2022 3:32 PM, Jani Nikula wrote:
On Mon, 22 Aug 2022, "Nautiyal, Ankit K" wrote:
LGTM.
Reviewed-by: Ankit Nautiyal
Thanks; does this apply to both patches?
I have given RB on the other patch separately.
Regards,
Ankit
BR,
Jani.
On 8/17/2022 6:15 PM, Jani Nikula wrote:
LGTM.
Reviewed-by: Ankit Nautiyal
On 8/17/2022 6:15 PM, Jani Nikula wrote:
From: Vandita Kulkarni
DSC 1.2 is supported from MTL, hence program ICH accordingly.
Cc: Ankit Nautiyal
Signed-off-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vdsc.c |
On Mon, 22 Aug 2022, "Nautiyal, Ankit K" wrote:
> LGTM.
>
> Reviewed-by: Ankit Nautiyal
Thanks; does this apply to both patches?
BR,
Jani.
>
> On 8/17/2022 6:15 PM, Jani Nikula wrote:
>> From: Vandita Kulkarni
>>
>> From MTL onwards we support DSC1.2, since there is hardcoding
>> to minor
LGTM.
Reviewed-by: Ankit Nautiyal
On 8/17/2022 6:15 PM, Jani Nikula wrote:
From: Vandita Kulkarni
From MTL onwards we support DSC1.2, since there is hardcoding
to minor version 1, update it.
Cc: Ankit Nautiyal
Signed-off-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
v3: -
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
---
include/drm/display/drm_dp.h
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/i915/display/intel_dp.c | 73 -
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
On Mon, 08 Aug 2022, Arun R Murthy wrote:
> The patch with commit 20f85ef89d94 ("drm/i915/backlight: use unique
> backlight device names") already adds support for dual panel backlight
> but with error prints. Since the patch tried to create the backlight
> device with the same name and upon
From: Suraj Kandpal
Adding WD Types, WD transcoder to enum list and WD Transcoder offsets.
Adding i915 register definitions related to WD transcoder
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 6 +
.../drm/i915/display/intel_display_types.h| 1 +
From: Suraj Kandpal
Changing intel_connector iterators as with writeback introduction
not all drm_connector will be embedded within intel_connector.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 7 ++---
.../drm/i915/display/intel_display_types.h| 26
A patch series was floated in the drm mailing list which aimed to change
the drm_connector and drm_encoder fields to pointer in the
drm_connector_writeback structure, this received a huge pushback from
the community but since i915 expects each connector present in the
drm_device list to be a
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