== Series Details ==
Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev4)
URL : https://patchwork.freedesktop.org/series/131700/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14520 -> Patchwork_131700v4
== Series Details ==
Series: Enable Aux Based EDP HDR
URL : https://patchwork.freedesktop.org/series/132009/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14522 -> Patchwork_132009v1
Summary
---
**SUCCESS**
No reg
== Series Details ==
Series: Enable Aux Based EDP HDR
URL : https://patchwork.freedesktop.org/series/132009/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: u
Limit minimum brightness to 20 when using aux based brightness
control to avoid letting the screen going completely blank.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/in
Write panel override luminance values which helps the TCON decide
if tone mapping needs to be enabled or not.
Signed-off-by: Suraj Kandpal
---
.../drm/i915/display/intel_dp_aux_backlight.c | 25 +++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel
As of now whenerver HDR is switched on we use the PWM to change the
backlight as opposed to AUX based backlight changes in terms of nits.
This patch writes to the appropriate DPCD registers to enable aux
based backlight using values in nits.
--v2
-Fix max_cll and max_fall assignment [Jani]
-Fix th
Change comments from Pre-TGL+ to Pre-ICL as mentioned in specs
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i
Change INTEL_EDP_HDR_TCON_SDP_COLORIMETRY enable to
INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX as this bit is tells TCON to
ignore DPCD colorimetry values and take the one's sent through
SDP.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 2 +-
1 file changed,
Add checks to see the HDR capability of TCON panel.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display_types.h| 5 +
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 10 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/displ
Make has_gamut_metadata_dip() non static so it can also be used to
at other places eg in intel_dp_aux_backlight.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
d
This series enables Aux based EDP HDR and backlight controls.
The DPCD written to are intel proprietary and are filled
based on the specs that were provided to TCON vendors.
Signed-off-by: Suraj Kandpal
Suraj Kandpal (7):
drm/i915/dp: Make has_gamut_metadata_dip() non static
drm/i915/dp: Add
Hi John,
On Fri, Mar 29, 2024 at 04:53:05PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The previous fix for the circlular lock splat about the busyness
> worker wasn't quite complete. Even though the reset-in-progress flag
> is cleared at the start of intel_uc_reset_finish
On Wed, Apr 03, 2024 at 04:52:47PM +0530, Balasubramani Vivekanandan wrote:
> From: José Roberto de Souza
>
> Xe2_HPD doesn't have DBOX BW credits, so here programing it with
> zero.
>
> BSpec: 49213
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
>
On Wed, Apr 03, 2024 at 04:52:41PM +0530, Balasubramani Vivekanandan wrote:
> From: Lucas De Marchi
>
> Add initial display info for xe2hpd. It is similar to xelpd, but with no
> PORT_B.
>
> Bspec: 67066
> Signed-off-by: Lucas De Marchi
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> .
On Wed, Apr 03, 2024 at 04:52:42PM +0530, Balasubramani Vivekanandan wrote:
> From: Anusha Srivatsa
>
> Add step 9 from initialize display sequence.
>
> Bpsec: 49189
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Balasubramani Vivekanandan
>
I think the title here is misleading since "mis
On Wed, Apr 03, 2024 at 04:52:40PM +0530, Balasubramani Vivekanandan wrote:
> From: Ravi Kumar Vodapalli
>
> DP/eDP and HDMI pll values are updated for Xe2_HPD platform
>
> Bspec: 74165
> Signed-off-by: Ravi Kumar Vodapalli
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/dr
On Wed, Apr 03, 2024 at 04:52:39PM +0530, Balasubramani Vivekanandan wrote:
> Tables for eDP PHY PLL configuration for different link rates added for
> Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas
> Xe2_HPD has C20 PHY.
>
> Bpsec: 64568
I think 74165 would be more accurate?
On Wed, Apr 03, 2024 at 04:52:37PM +0530, Balasubramani Vivekanandan wrote:
> From: José Roberto de Souza
>
> Xe2_HPD has a different value to power down port A.
>
> BSpec: 65450
> CC: Matt Roper
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Balasubramani Vivekanandan
>
Reviewed-b
On Wed, Apr 03, 2024 at 04:52:36PM +0530, Balasubramani Vivekanandan wrote:
> From: Radhakrishna Sripada
>
> Discrete cards use the Port numbers TC1-4 for the offsets. The regular
> flow for type-c subsystem port initialization can be skipped. This check
> is present in DG2. Extend this to future
On Wed, Apr 03, 2024 at 04:52:35PM +0530, Balasubramani Vivekanandan wrote:
> From: Ankit Nautiyal
>
> This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f.
> For BMG it seems that the VBT to DDI mapping does not follow DG1, and
> DG2, but follows ADLP mapping given in Bspec:20124.
>
> S
On Wed, Apr 03, 2024 at 04:52:34PM +0530, Balasubramani Vivekanandan wrote:
> From: Clint Taylor
>
> Add Xe2_HPD specific CDCLK table and use MTL Funcs.
>
> Bspec: 65243
> Cc: Matt Roper
> CC: Lucas De Marchi
> Signed-off-by: Clint Taylor
> Signed-off-by: Balasubramani Vivekanandan
>
Revie
On Wed, Apr 03, 2024 at 04:52:33PM +0530, Balasubramani Vivekanandan wrote:
> Xe2 platforms doesn't support Aux CCS and the Flat CCS is enabled
> through PAT. No CCS modifiers required for Xe2 platforms.
The change looks correct, but you might want to elaborate on this
description a bit to help cl
On Wed, Apr 03, 2024 at 03:39:19PM +, Murthy, Arun R wrote:
> Gentle Reminder!
Thanks for your patch. I'm convinced we really need something like this.
At least to shout the static analyzers.
Or this or using the mul_u32_u32 or casting one of the right operands,
otherwise the
result of the m
On Fri, Mar 29, 2024 at 07:38:11PM +0300, Dan Carpenter wrote:
> On Fri, Mar 29, 2024 at 08:09:38AM +0100, Andi Shyti wrote:
> > Hi Rodrigo,
> >
> > On Thu, Mar 28, 2024 at 09:39:17PM -0400, Rodrigo Vivi wrote:
> > > On Thu, Mar 28, 2024 at 10:41:55PM +0100, Andi Shyti wrote:
> > > > On Thu, Mar 2
On Wed, Apr 03, 2024 at 04:52:32PM +0530, Balasubramani Vivekanandan wrote:
> Display code uses IS_BATTLEMAGE macro but the platform support doesn't
> still exist in i915. So fake IS_BATTLEMAGE macro defined to enable
I'd drop the "still" here since that wording would incorrectly imply
that i915 h
On Wed, Apr 03, 2024 at 04:52:31PM +0530, Balasubramani Vivekanandan wrote:
> Common display code requires IS_BATTLEMAGE macro. Defined the macro.
>
> Signed-off-by: Balasubramani Vivekanandan
>
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 +
> 1 file
On Wed, Apr 03, 2024 at 04:52:46PM +0530, Balasubramani Vivekanandan wrote:
> From: Mitul Golani
>
> Enable RM timeout interrupt to detect any hang during display engine
> register access. This interrupt is supported only on Display version 14.
This doesn't seem to be true. Bit 29 of the IIR re
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 727900b675b749c40ba1f6669c7ae5eb7eb8e837 Add linux-next specific
files for 20240403
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202404031246.aq5yr5ko-...@intel.com
https
On Fri, Mar 29, 2024 at 12:29:09PM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjala (2024-03-27 14:45:32-03:00)
> >From: Ville Syrjälä
> >
> >Currently we always reprogram CDCLK from the
> >intel_set_cdclk_pre_plane_update() when using squahs/crawl.
> >The code only works correctly for the cd2x
== Series Details ==
Series: drm/xe/display: check for error on drmm_mutex_init (rev4)
URL : https://patchwork.freedesktop.org/series/131301/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14521 -> Patchwork_131301v4
Summary
Gentle Reminder!
Thanks and Regards,
Arun R Murthy
> -Original Message-
> From: Intel-gfx On Behalf Of Murthy,
> Arun R
> Sent: Thursday, March 28, 2024 10:34 AM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: RE: [PATCH] drm/xe/displ
On Thu, Mar 28, 2024 at 12:33:09PM +0200, Jani Nikula wrote:
On Thu, 28 Mar 2024, Andi Shyti wrote:
Hi Arun,
...
- drmm_mutex_init(&xe->drm, &xe->sb_lock);
- drmm_mutex_init(&xe->drm, &xe->display.backlight.lock);
- drmm_mutex_init(&xe->drm, &xe->display.audio.mutex);
-
Check return value for drmm_mutex_init as it can fail and return on
failure.
v2: Removed nested if (Lucas)
v3: Revert back to nested if (Andi)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 30 -
1 file changed, 24 insertions(+), 6 deletions(-
== Series Details ==
Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev4)
URL : https://patchwork.freedesktop.org/series/131700/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Wed, Apr 03, 2024 at 04:52:30PM +0530, Balasubramani Vivekanandan wrote:
diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h
index c7fc288dacee..73d972a8aca1 100644
--- a/include/drm/xe_pciids.h
+++ b/include/drm/xe_pciids.h
@@ -208,4 +208,11 @@
MACRO__(0x64A0, ## __VA_ARGS_
The pipes that can be used for eDP MSO are limited to pipe A (and
sometimes also pipe B) only for display version 20 and below.
Modify the function that returns the pipe mask for eDP MSO so that
these limitations only apply to version 20 and below, enabling all
pipes otherwise.
Bspec: 68923
Cc: J
Hi Bala,
On 4/3/2024 1:22 PM, Balasubramani Vivekanandan wrote:
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence to
e
+Jouni
On 4/3/2024 1:22 PM, Balasubramani Vivekanandan wrote:
From: Matthew Auld
Perform manual transient cache flush prior to flip and at the end of
frontbuffer_flush. This is needed to ensure display engine doesn't see
garbage if the surface is L3:XD dirty.
Testcase: igt@xe-pat@display-vs-w
On Thu, 28 Mar 2024, Imre Deak wrote:
> On Wed, Mar 20, 2024 at 10:11:41PM +0200, Imre Deak wrote:
>> Fix the calculation of the DSC line buffer depth. This is limited both
>> by the source's and sink's maximum line buffer depth, but the former one
>> was not taken into account. On all Intel platf
On 4/3/2024 1:22 PM, Balasubramani Vivekanandan wrote:
From: Matthew Auld
Needed in an upcoming patch, where we want GT level print, but only
which to trigger once to avoid flooding dmesg.
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Nirmoy Das
---
On Wed, 03 Apr 2024, Balasubramani Vivekanandan
wrote:
> Xe2_HPD has different address for C20 PLL registers. Enable the support
> to use the right PLL register address based on display version.
>
> Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e.
> MTL's display). According
On Wed, 03 Apr 2024, Balasubramani Vivekanandan
wrote:
> From: Mitul Golani
>
> Enable RM timeout interrupt to detect any hang during display engine
> register access. This interrupt is supported only on Display version 14.
> Current default timeout is 2ms.
>
> WA: 14012195489
Please don't inve
== Series Details ==
Series: Enable dislay support for Battlemage (rev2)
URL : https://patchwork.freedesktop.org/series/131984/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14520 -> Patchwork_131984v2
Summary
---
**
On Wed, 03 Apr 2024, Balasubramani Vivekanandan
wrote:
> Defined a new DRAM type to be used in the following patches.
> The following patch first makes use of this new type in the i915
> display. So without this define, build would fail when the shared
> display code is built for Xe.
Just make i
On Wed, 03 Apr 2024, Balasubramani Vivekanandan
wrote:
> From: Clint Taylor
>
> Write both CX0 Lanes for Context Toggle for all except TC pin assignment D.
Seems like a fix that should be the first patch in the series, no?
> BSPEC: 64539
The spelling is "Bspec".
> Signed-off-by: Clint Taylor
== Series Details ==
Series: Enable dislay support for Battlemage (rev2)
URL : https://patchwork.freedesktop.org/series/131984/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Enable dislay support for Battlemage (rev2)
URL : https://patchwork.freedesktop.org/series/131984/
State : warning
== Summary ==
Error: dim checkpatch failed
240c4657f7c1 drm/i915/display: Prepare to handle new C20 PLL register address
-:75: WARNING:LONG_LINE: line
On Wed, 03 Apr 2024, Balasubramani Vivekanandan
wrote:
> New platforms have different addresses for C20 PLL registers. This patch
> prepares the driver to work with different register addresses.
> New structure `struct intel_c20pll_reg` is created to hold the register
> addresses for each platfor
Enable the display support for Battlemage
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index b3158053baee..835c18ec8fb9 100644
--- a/drivers/gpu/drm/xe/xe_pc
From: Matthew Auld
Perform manual transient cache flush prior to flip and at the end of
frontbuffer_flush. This is needed to ensure display engine doesn't see
garbage if the surface is L3:XD dirty.
Testcase: igt@xe-pat@display-vs-wb-transient
Signed-off-by: Matthew Auld
Signed-off-by: Balasubra
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence to
ensure all transient data in L3 cache is flushed to memory. Add a
ro
From: Matthew Auld
Needed in an upcoming patch, where we want GT level print, but only
which to trigger once to avoid flooding dmesg.
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++
1 file changed, 3 insertions(+)
diff --gi
Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate
to it.
Bspec: 67066
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i91
From: Matt Roper
Battlemage's south display is the same as Meteor Lake's, including the
need to invert the HPD pins, which Lunar Lake does not need.
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/soc/intel_pch.c | 4 ++--
1 file changed, 2 inserti
From: José Roberto de Souza
Xe2_HPD doesn't have DBOX BW credits, so here programing it with
zero.
BSpec: 49213
Signed-off-by: José Roberto de Souza
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Mitul Golani
Enable RM timeout interrupt to detect any hang during display engine
register access. This interrupt is supported only on Display version 14.
Current default timeout is 2ms.
WA: 14012195489
Bspec: 50110
CC: Suraj Kandpal
Signed-off-by: Mitul Golani
Signed-off-by: Balasubram
From: Matt Roper
Unlike DG2, Xe2_HPD does support multiple GV points with different
maximum memory bandwidths, but uses a much simpler algorithm than igpu
platforms use.
Bspec: 64631
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_bw.
Defined a new DRAM type to be used in the following patches.
The following patch first makes use of this new type in the i915
display. So without this define, build would fail when the shared
display code is built for Xe.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_device
From: Clint Taylor
Write both CX0 Lanes for Context Toggle for all except TC pin assignment D.
BSPEC: 64539
Signed-off-by: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
From: Anusha Srivatsa
Add step 9 from initialize display sequence.
Bpsec: 49189
Signed-off-by: Anusha Srivatsa
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files changed,
From: Lucas De Marchi
Add initial display info for xe2hpd. It is similar to xelpd, but with no
PORT_B.
Bspec: 67066
Signed-off-by: Lucas De Marchi
Signed-off-by: Balasubramani Vivekanandan
---
.../gpu/drm/i915/display/intel_display_device.c | 16
1 file changed, 16 insertion
From: Ravi Kumar Vodapalli
DP/eDP and HDMI pll values are updated for Xe2_HPD platform
Bspec: 74165
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 47 +++-
1 file changed, 45 insertions(+), 2 del
Tables for eDP PHY PLL configuration for different link rates added for
Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas
Xe2_HPD has C20 PHY.
Bpsec: 64568
CC: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147 ++
Xe2_HPD has different address for C20 PLL registers. Enable the support
to use the right PLL register address based on display version.
Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e.
MTL's display). According to the BSpec, currently, only Xe2_HPD has
different offsets, so m
From: José Roberto de Souza
Xe2_HPD has a different value to power down port A.
BSpec: 65450
CC: Matt Roper
Signed-off-by: José Roberto de Souza
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++---
1 file changed, 14 insertions(+)
From: Radhakrishna Sripada
Discrete cards use the Port numbers TC1-4 for the offsets. The regular
flow for type-c subsystem port initialization can be skipped. This check
is present in DG2. Extend this to future discrete products.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Balasubramani
From: Ankit Nautiyal
This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f.
For BMG it seems that the VBT to DDI mapping does not follow DG1, and
DG2, but follows ADLP mapping given in Bspec:20124.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/
From: Clint Taylor
Add Xe2_HPD specific CDCLK table and use MTL Funcs.
Bspec: 65243
Cc: Matt Roper
CC: Lucas De Marchi
Signed-off-by: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++
1 file changed, 11 insertions(+)
dif
Xe2 platforms doesn't support Aux CCS and the Flat CCS is enabled
through PAT. No CCS modifiers required for Xe2 platforms.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_fb.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/dr
Display code uses IS_BATTLEMAGE macro but the platform support doesn't
still exist in i915. So fake IS_BATTLEMAGE macro defined to enable
building i915 code. We should make sure the macro parameter is used in
the always-false expression so that we don't run into "unused variable"
warnings from i91
Common display code requires IS_BATTLEMAGE macro. Defined the macro.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
b/drivers/gpu/drm/xe/compat-
From: Matt Roper
BMG is a discrete GPU based on the Xe2 architecture.
Bspec: 68090
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_pci.c| 7 +++
drivers/gpu/drm/xe/xe_platform_types.h | 1 +
include/drm/xe_pciids.h|
New platforms have different addresses for C20 PLL registers. This patch
prepares the driver to work with different register addresses.
New structure `struct intel_c20pll_reg` is created to hold the register
addresses for each platform with different register address.
CC: Clint Taylor
Signed-off-
Adds display support for Battlemage.
Reuses the patch "drm/xe/bmg: Add BMG platform definition" from the
patch series to help build this series. So that review on this
series can continue without blocking on .
v2: Rebased on latest drm-tip
Ankit Nautiyal (1):
Revert "drm/i915/dgfx: DGFX uses d
== Series Details ==
Series: Enable dislay support for Battlemage
URL : https://patchwork.freedesktop.org/series/131984/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/131984/revisions/1/mbox/ not
applied
Applying: drm/i915/display: Prepare to han
There is new fixup patch(PR#630) which modifies this patch. Could you
please bring that in as well.
Regards,
Nirmoy
On 4/3/2024 12:51 PM, Balasubramani Vivekanandan wrote:
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index mo
Enable the display support for Battlemage
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index b3158053baee..835c18ec8fb9 100644
--- a/drivers/gpu/drm/xe/xe_pc
From: Matthew Auld
Perform manual transient cache flush prior to flip and at the end of
frontbuffer_flush. This is needed to ensure display engine doesn't see
garbage if the surface is L3:XD dirty.
Testcase: igt@xe-pat@display-vs-wb-transient
Signed-off-by: Matthew Auld
Signed-off-by: Balasubra
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence to
ensure all transient data in L3 cache is flushed to memory. Add a
ro
From: Matthew Auld
Needed in an upcoming patch, where we want GT level print, but only
which to trigger once to avoid flooding dmesg.
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++
1 file changed, 3 insertions(+)
diff --gi
Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate
to it.
Bspec: 67066
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i91
From: Matt Roper
Battlemage's south display is the same as Meteor Lake's, including the
need to invert the HPD pins, which Lunar Lake does not need.
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/soc/intel_pch.c | 4 ++--
1 file changed, 2 inserti
From: José Roberto de Souza
Xe2_HPD doesn't have DBOX BW credits, so here programing it with
zero.
BSpec: 49213
Signed-off-by: José Roberto de Souza
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Clint Taylor
Write both CX0 Lanes for Context Toggle for all except TC pin assignment D.
BSPEC: 64539
Signed-off-by: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
From: Mitul Golani
Enable RM timeout interrupt to detect any hang during display engine
register access. This interrupt is supported only on Display version 14.
Current default timeout is 2ms.
WA: 14012195489
Bspec: 50110
CC: Suraj Kandpal
Signed-off-by: Mitul Golani
Signed-off-by: Balasubram
From: Matt Roper
Unlike DG2, Xe2_HPD does support multiple GV points with different
maximum memory bandwidths, but uses a much simpler algorithm than igpu
platforms use.
Bspec: 64631
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_bw.
Defined a new DRAM type to be used in the following patches.
The following patch first makes use of this new type in the i915
display. So without this define, build would fail when the shared
display code is built for Xe.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_device
From: Radhakrishna Sripada
Discrete cards use the Port numbers TC1-4 for the offsets. The regular
flow for type-c subsystem port initialization can be skipped. This check
is present in DG2. Extend this to future discrete products.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Balasubramani
From: Ravi Kumar Vodapalli
DP/eDP and HDMI pll values are updated for Xe2_HPD platform
Bspec: 74165
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 47 +++-
1 file changed, 45 insertions(+), 2 del
From: Anusha Srivatsa
Add step 9 from initialize display sequence.
Bpsec: 49189
Signed-off-by: Anusha Srivatsa
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files changed,
From: José Roberto de Souza
Xe2_HPD has a different value to power down port A.
BSpec: 65450
CC: Matt Roper
Signed-off-by: José Roberto de Souza
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++---
1 file changed, 14 insertions(+)
From: Lucas De Marchi
Add initial display info for xe2hpd. It is similar to xelpd, but with no
PORT_B.
Bspec: 67066
Signed-off-by: Lucas De Marchi
Signed-off-by: Balasubramani Vivekanandan
---
.../gpu/drm/i915/display/intel_display_device.c | 16
1 file changed, 16 insertion
Xe2_HPD has different address for C20 PLL registers. Enable the support
to use the right PLL register address based on display version.
Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e.
MTL's display). According to the BSpec, currently, only Xe2_HPD has
different offsets, so m
From: Ankit Nautiyal
This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f.
For BMG it seems that the VBT to DDI mapping does not follow DG1, and
DG2, but follows ADLP mapping given in Bspec:20124.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/
Tables for eDP PHY PLL configuration for different link rates added for
Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas
Xe2_HPD has C20 PHY.
Bpsec: 64568
CC: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147 ++
Xe2 platforms doesn't support Aux CCS and the Flat CCS is enabled
through PAT. No CCS modifiers required for Xe2 platforms.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_fb.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/dr
From: Clint Taylor
Add Xe2_HPD specific CDCLK table and use MTL Funcs.
Bspec: 65243
Cc: Matt Roper
CC: Lucas De Marchi
Signed-off-by: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++
1 file changed, 11 insertions(+)
dif
Common display code requires IS_BATTLEMAGE macro. Defined the macro.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
b/drivers/gpu/drm/xe/compat-
Display code uses IS_BATTLEMAGE macro but the platform support doesn't
still exist in i915. So fake IS_BATTLEMAGE macro defined to enable
building i915 code. We should make sure the macro parameter is used in
the always-false expression so that we don't run into "unused variable"
warnings from i91
From: Matt Roper
BMG is a discrete GPU based on the Xe2 architecture.
Bspec: 68090
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_pci.c| 7 +++
drivers/gpu/drm/xe/xe_platform_types.h | 1 +
include/drm/xe_pciids.h|
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