Current GuC firmwares identify response message in a different way.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Kelvin Gardiner
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_ct.c | 2 +-
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 ++
2 files changed, 3 insertions
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal
Gen11 GuC firmware expects H2G command messages to be sent over CTB
(command transport buffers).
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
New GuC firmwares (for SKL, BXT, KBL, ICL) with updated ABI interface.
v2: only HuC authentication is supported
Michal Wajdeczko (20):
drm/i915/guc: Change platform default GuC mode
drm/i915/guc: Don't allow GuC submission
drm/i915/guc: Simplify preparation of GuC parameter block
drm
New GuC firmwares use different action code value for this command.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
With newer GuC firmware it is always ok to ask GuC to update power
domain states. Make it an unconditional initialization step.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_submission.c | 4
drivers/gpu/drm/i915
Some CI systems might be configured to run with no longer supported
configuration "enable_guc=3" or "enable_guc=1". Hack that ;)
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_uc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/d
On Wed, 10 Apr 2019 12:59:18 +0200, Mika Kuoppala
wrote:
On gen11 the recommended rc6 threshold differs from previous
gens, apply it. Move the write to a correct spot in sequence.
v2: do write in 2b, fix bspec ref (Michal)
Bspec: 33149
Cc: Michal Wajdeczko
Signed-off-by: Mika Kuoppala
On Tue, 09 Apr 2019 18:13:04 +0200, Mika Kuoppala
wrote:
[snip]
+
+ /*
+* 2c: Program Coarse Power Gating Policies.
+*
+* Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
+* use instead is a more conservative estimate for the maximum
On Tue, 09 Apr 2019 18:13:05 +0200, Mika Kuoppala
wrote:
On gen11 the recommended rc6 threshold differs from previous
gens, apply it.
References: bspec#52070
Is this correct number? I found it at 33149
And note that we are using different tag:
Bspec: 33149
Signed-off-by: Mika Kuoppala
On Sat, 30 Mar 2019 11:03:49 +0100, Chris Wilson
wrote:
As we only set ctx->file_priv on registering the GEM context after
construction, it is invalid to try and use it in the middle for setting
Other option would be to set ctx->file_priv ahead of gem_context_register
and use
From: Oscar Mateo
The GuC interrupts now get their own interrupt vector (instead of
sharing a register with the PM interrupts) so handle appropriately.
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
---
drivers
must insert a
special wq item called resume-parsing and wait until the queue_engine_error
field is updated.
Co-Developed-by: Michel Thierry
Co-Developed-by: Michal Wajdeczko
Signed-off-by: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Vinay Belgaumkar
Cc: Michal
in the driver, so disable it.
Bspec: 12609
Bspec: 10800
Bspec: 10932
Bspec: 10934
Bspec: 9517
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Michal Winiarski
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915
From: Oscar Mateo
Controlling and handling of the GuC interrupts is Gen specific.
Create virtual functions to avoid redundant runtime Gen checks.
Gen-specific versions of these functions will follow.
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Tvrtko
-by: Michal Wajdeczko
Cc: Michal Winiarski
Cc: Tomasz Lis
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_engine_cs.c | 3 ++-
drivers/gpu/drm/i915/intel_guc_fwif.h | 19 +++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Lionel Landwerlin
Cc: Michal Winiarski
Cc: Tomasz Lis
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h| 9 -
drivers/gpu/drm/i915/i915_gem_context.c| 6 +-
drivers/gpu
GuC sends ENGINE_RESET_COMPLETE message as an follow-up answer
to earlier ENGINE_RESET request from the host. Once this message
is received, clear engine reset flag to unblock our reset process.
Credits-to: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Vinay
Gen11 GuC firmware expects H2G command messages to be sent over CTB
(command transport buffers).
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal
From: Oscar Mateo
Current GuC firmwares identify response message in a different way.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Kelvin Gardiner
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_ct.c | 2 +-
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 ++
2 files
This patch adds the support to load HuC on ICL.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Anusha Srivatsa
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal
GuC firmware changed its release version numbering schema and now it
also includes patch version. Update our GuC firmware path definitions
to match new pattern:
_guc_...bin
While here, reorder platform checks and start from the latest.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
GuC stores some data in there, which might be stale after a reset.
Reinitialize whole ADS in case any part of it was corrupted during
previous GuC run.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: MichaĹ Winiarski
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_guc.h | 2
New GuC firmwares use different action code value for this command.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
Define GuC firmware version for Icelake.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915
Signed-off-by: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Vinay Belgaumkar
Cc: Michal Winiarski
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_guc.c | 73 +++-
drivers/gpu/drm/i915/intel_guc.h | 6 +++
2 files changed, 69 insertions
Work queue items definitions were updated.
To simplify the scheduling logic in the GuC firmware,
only out-of-order mode of scheduling is now supported.
Credits-to: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Michał
the unpinning steps. However, the unpining steps
perform extra correctness check so better keep them until we're sure
that the flow is solid.
Based on an initial patch by Oscar Mateo.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Michal Wajdeczko
Cc: Michal Winiarski
Cc: Tomasz Lis
For now, we only want to test "enable_guc=2" configuration.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/d
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: John Spotswood
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915
Some Gen9 CI systems are still prepared to run no longer supported
configuration "enable_guc=3"
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_uc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_
Definition of the parameters block passed to GuC is about to change.
Slightly refactor code now to make upcoming patch smaller.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: John Spotswood
Reviewed-by: John Spotswood
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915
New GuC firmwares use updated definitions for the Additional Data
Structures (ADS).
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Fernando Pacheco
Cc: Joonas Lahtinen
Cc: John Spotswood
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_engine_cs.c | 5
There are few minor changes in the CSS header related to the version
numbering in new GuC firmwares. Update our definition and start using
common tools for extracting bitfields.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
Cc: Jeff Mcgee
With newer GuC firmware it is always ok to ask GuC to update power
domain states. Make it an unconditional initialization step.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_submission.c | 4
drivers/gpu/drm/i915
There is no fallback to execlists, but instead of aborting whole
driver load, just mark it as wedged.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/intel_uc.c | 6 ++
2
New GuC firmwares use updated sleep status definitions.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
New GuC firmwares require updated boot parameters.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc.c | 36 +
drivers/gpu/drm/i915/intel_guc_fwif.h | 39
Due to the GuC interface changes, new firmware releases will
stop support GuC submission mode for pre-Gen11 platforms.
Sanitize the enable_guc option so that only HuC authentication
would be possible.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo
-guc/igt@gem_exec_susp...@basic-s3.html
[2]
https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4030/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html
Daniele Ceraolo Spurio (2):
drm/i915/guc: New GuC IDs based on engine class and instance
drm/i915/guc: New GuC stage descriptors
Michal Wajdeczko (23
On Mon, 25 Mar 2019 22:49:33 +0100, Daniele Ceraolo Spurio
wrote:
We have several cases where we don't have forcewake (older gens, GVT and
planned display-only uncore), so, instead of checking every time against
the various condition, save the info in a flag and use that.
Note that this
-by: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_device_info.c | 15 ---
drivers/gpu/drm/i915/intel_device_info.h | 4
3 files changed, 14 insertions(+), 11
GuC may send notification messages with payload larger than
single u32. Prepare driver to accept longer messages.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Vinay Belgaumkar
Cc: Michal Winiarski
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_guc.c| 14
Make things look a bit nicer by passing dev_priv to
In other places we are changing naming from dev_priv to i915.
Can we do the same here ?
~Michal
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-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Sujaritha Sundaresan
---
Reviewed-by: Michal Wajdeczko
~Michal
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On Wed, 06 Mar 2019 09:45:17 +0100, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-03-06 08:41:20)
On Wed, 06 Mar 2019 01:30:11 +0100, Sujaritha Sundaresan
wrote:
> Replacing the -E2BIG error code return for WOPCM
> initialization with -ENODEV. This will prevent the pci from
s/
in i915_pci_probe() to ENODEV
instead of the specific wopcm change. - Daniele
s/wopcm/WOPCM
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
On Thu, 28 Feb 2019 11:24:53 +0100, Jani Nikula
wrote:
On Thu, 28 Feb 2019, Michal Wajdeczko wrote:
On Wed, 27 Feb 2019 18:02:38 +0100, Jani Nikula
wrote:
@@ -108,9 +108,9 @@
* #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A,
_FOO_B)
* #define FOO_ENABLE
On Thu, 28 Feb 2019 11:12:43 +0100, Chris Wilson
wrote:
But I think the central tenant is that we want to use the common naming
scheme so that we can trivially go from GENMASK to REG_GENMASK/GENMASK32
and that other people reading our code already know the language (plus
we want these to be
On Wed, 27 Feb 2019 18:02:38 +0100, Jani Nikula
wrote:
@@ -108,9 +108,9 @@
* #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
* #define FOO_ENABLEREG_BIT(31)
* #define FOO_MODE_MASK REG_GENMASK(19, 16)
- * #define FOO_MODE_BAR
On Wed, 27 Feb 2019 18:02:36 +0100, Jani Nikula
wrote:
@@ -116,6 +116,34 @@
* #define GEN8_BAR_MMIO(0xb888)
*/
+/**
+ * REG_BIT() - Prepare a u32 bit value
+ * @__n: 0-based bit number
+ *
+ * Local wrapper for BIT() to force u32, with compile time checks.
+ *
+ *
On Fri, 15 Feb 2019 05:32:14 +0100, Srivatsa, Anusha
wrote:
Resending this again, didn’t get Delivered the last time I sent.
Sending PR for latest Guc v31.3.0 for ICL and Gen9 platforms.
The following changes since commit
710963fe53ee3f227556d36839df3858daf6e232:
Merge
_uc_fw_fetch.
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
---
Reviewed-by: Michal Wajdeczko
Thanks,
Michal
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typo in title
On Tue, 08 Jan 2019 11:11:45 +0100, Chris Wilson
wrote:
If we haven't shipped and enabled firmware for a particular platform,
there is nothing the user can do about it. Don't scare the user with an
unactionable, unindentifiable warning!
Did you mean: unidentifiable ?
<6>
On Fri, 21 Dec 2018 14:31:38 +0100, Jani Nikula
wrote:
/snip/
diff --git a/drivers/gpu/drm/i915/intel_uc.h
b/drivers/gpu/drm/i915/intel_uc.h
index 25d73ada74ae..24990ade4fb8 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -41,19 +41,19 @@ void
On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio
wrote:
/snip/
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 8382d591c784..1a853cc627e3 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++
On Tue, 06 Nov 2018 17:47:27 +0100, Tomasz Lis
wrote:
[snip]
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+ GEN11_MOCS_ENTRIES
+ [16] = {
+ /* Reserved - For future use */
+ .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_PAGETABLE,
+
Wilson
Cc: sta...@vger.kernel.org
---
Reviewed-by: Michal Wajdeczko
Michal
drivers/gpu/drm/i915/i915_gem_gtt.h | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index
On Fri, 02 Nov 2018 17:32:06 +0100, Lionel Landwerlin
wrote:
On 02/11/2018 15:47, Sergii Romantsov wrote:
Operating with gtt-addresses has to be done with 64b variables.
CC: Kenneth Graunke
CC: Chris Wilson
Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT
systems.)
), drop guc_doorbell_qw since it just
duplicates guc_doorbell_info
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
Reviewed-by: Michal Wajdeczko
Thanks,
Michal
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GuC is disabled by default. Enable it.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers
an 8-element array to store the H2G message,
so we may reduce our send array to just 8 registers (Daniele)
v3: use explicit define
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_guc.c | 3 ++-
drivers/gpu/drm/i915/intel_guc_fwif.h
GuC is disabled by default. Enable it.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers
On Thu, 18 Oct 2018 20:18:53 +0200, Daniele Ceraolo Spurio
wrote:
On 18/10/18 02:13, Chris Wilson wrote:
Quoting Michal Wajdeczko (2018-10-18 00:22:43)
On Thu, 18 Oct 2018 01:09:19 +0200, Daniele Ceraolo Spurio
wrote:
On 17/10/18 13:29, Chris Wilson wrote:
Propagate the timeout
by the platform.
Cc: Michal Wajdeczko
Cc: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
Reviewed-by: Michal Wajdeczko
Thanks,
Michal
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the doorbell is in an unexpected
state)
- Move the checking of doorbell valid bit to a common helper.
v2: add more cleanups (move defs, use GUC_NUM_DOORBELLS, don't stop in
guc_verify_doorbells) (Michal)
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915
validation, so it isn't really worth
tweaking the driver for it and we're better off dropping it instead.
Testing the driver running out of doorbells is already covered by
igt_guc_doorbells
Suggested-by: Michal Wajdeczko
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
Reviewed-by: Michal
the xfer and didn't get a timeout
out of guc_wait_ucode? that'd be quite weird
Anyway, definitely better and cleaner than before:
Reviewed-by: Daniele Ceraolo Spurio
small nitpick below
Testcase: igt/drv_selftest/live_hangcheck
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo
GuC is disabled by default. Enable it.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers
an 8-element array to store the H2G message,
so we may reduce our send array to just 8 registers (Daniele)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_guc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
will start to use Gen9 value.
v2: use bool for implicit conversion (Chris)
Signed-off-by: Michal Wajdeczko
Cc: Michal Winiarski
Cc: Joonas Lahtinen
Cc: Haihao Xiang
Reviewed-by: Michał Winiarski #1
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_huc.c | 7 ---
1 file changed, 4
: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Acked-by: Chris Wilson
---
Reviewed-by: Michal Wajdeczko
Michal
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: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_submission.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index
On Wed, 17 Oct 2018 02:17:16 +0200, Daniele Ceraolo Spurio
wrote:
Cacheline selection is only needed if we actually manage to reserve a
doorbell.
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
Reviewed-by: Michal Wajdeczko
On Wed, 17 Oct 2018 02:17:15 +0200, Daniele Ceraolo Spurio
wrote:
The 2 functions don't create or destroy anything, they just update the
doorbell state in memory. Use init and fini instead for clarity.
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
Reviewed-by: Michal
On Tue, 16 Oct 2018 19:15:19 +0200, Daniele Ceraolo Spurio
wrote:
On 10/16/2018 2:21 AM, Daniel Vetter wrote:
On Tue, Oct 16, 2018 at 1:44 AM Daniele Ceraolo Spurio
wrote:
On 15/10/18 15:47, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: fix
On Tue, 16 Oct 2018 14:16:48 +0200, Patchwork
wrote:
== Series Details ==
Series: drm/i915/huc: Normalize HuC status returned by I915_PARAM_HAS_HUC
URL : https://patchwork.freedesktop.org/series/51060/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4985 ->
will start to use Gen9 value.
Signed-off-by: Michal Wajdeczko
Cc: Michal Winiarski
Cc: Joonas Lahtinen
Cc: Haihao Xiang
---
drivers/gpu/drm/i915/intel_huc.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915
we can poll on that. Note that GuC does not ensure that the value
in the register is different from 0 while the action is in progress
so we need to take care of that ourselves as well.
Cc: Chris Wilson
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915
We wrongly assumed that GuC is only using last scratch register
for G2H messages, but in fact it is also using register [14] to
report sleep state status. Remove that register from our H2G
send registers pool.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers
On Tue, 16 Oct 2018 10:49:54 +0200, Chris Wilson
wrote:
Quoting Daniele Ceraolo Spurio (2018-10-16 00:43:59)
...
>
> igt@drv_selftest@live_hangcheck:
>fi-skl-gvtdvm: PASS -> DMESG-FAIL
>
<7> [464.966238] [drm:guc_fw_xfer [i915]] GuC status 0x20
<3> [464.966361]
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers
v_selftest@live_hangcheck
Reported-by: Daniele Ceraolo Spurio
References: commit 4502e9ec820d ("drm/i915/uc: Unify firmware loading")
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_uc.c | 2 +-
1 file changed, 1 insertion(+),
In function i915_gem_init_hw we are initializing some uC code that
requires some cleanup. Then during unwind we call this uC cleanup
function directly which breaks symmetry and layering. Fix that by
adding i915_gem_fini_hw for symmetry with i915_gem_init_hw.
Signed-off-by: Michal Wajdeczko
Cc
We need extra load failure point to better test error path in
i915_driver_init_mmio.
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915
In case of the error we missed to call i915_mmio_cleanup
that matches earlier call to i915_mmio_setup.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
1 file changed, 1
In case of the error we missed to call i915_mmio_cleanup
that matches earlier call to i915_mmio_setup.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b
On Wed, 10 Oct 2018 14:01:40 +0200, Jani Nikula
wrote:
On Tue, 09 Oct 2018, Nick Desaulniers wrote:
On Tue, Oct 9, 2018 at 10:14 AM Nathan Chancellor
wrote:
When building the kernel with Clang with defconfig and CONFIG_64BIT
disabled, vmlinux fails to link because of the BUILD_BUG in
ichal)
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
Reviewed-by: Michal Wajdeczko
Michal
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, always memset and init the descriptors from scratch
after GuC is loaded.
The code is also reorganized so that the above operations and the
doorbell creation are grouped as "client enabling"
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gp
at it while the doorbell is inactive
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
With fixed typo in patch title,
Reviewed-by: Michal Wajdeczko
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On Thu, 27 Sep 2018 11:40:19 +0200, Jani Nikula
wrote:
This is an RFC to get input on how people feel about moving towards
using and macros for register field
definitions and manipulation:
* BIT()
* GENMASK()
BIT/GENMASK macros assumes 'unsigned long' type (64b) while our registers
(and
On Tue, 25 Sep 2018 10:26:57 +0200, Chris Wilson
wrote:
Quoting Chris Wilson (2018-09-25 09:01:06)
Quoting Tvrtko Ursulin (2018-09-24 11:29:52)
>
> On 19/09/2018 20:55, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_scheduler.h
b/drivers/gpu/drm/i915/i915_scheduler.h
> >
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_uc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index b1b3e81..ad659c1 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
We should update GuC power domain states also when GuC submission
is disabled, otherwise GuC might complain or ignore our requests.
This seems to be required for all currently released GuC firmwares.
v2: it is only needed by pre-Gen11 firmwares
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
This will let the driver decide where GuC can be used
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm
We should update GuC power domain states also when GuC submission
is disabled, otherwise GuC might complain or ignore our requests.
This seems to be required for all currently released GuC firmwares.
v2: it is only needed by pre-Gen11 firmwares
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
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