hannel
Signed-off-by: Josh Soref <2119212+jso...@users.noreply.github.com>
Acked-by: Ralf Ramsauer
Thanks,
Ralf
---
README.md | 4
1 file changed, 4 deletions(-)
diff --git a/README.md b/README.md
index dc2c3af..ad7aa76 100644
--- a/README.md
+++ b/README.md
@@ -43,10 +43,6 @
<https://patchwork.kernel.org/project/linux-rockchip/patch/20170206233000.3021-1-diand...@chromium.org/>
[2]https://groups.google.com/g/linux-sunxi/c/4iYuzbWt79k/m/IFEarUoMDAAJ
<https://groups.google.com/g/linux-sunxi/c/4iYuzbWt79k/m/IFEarUoMDAAJ>
On Thu, May 23, 2024 at 6:58 PM Ra
Hi,
On 23/05/2024 09:43, Ke Li wrote:
Hi, Ralf,
I've taken your advice and do the following:
1. Revert the change on JAILHOUSE_BASE to 0xc020. (btw, I got
the idea of modifying it from the talk "Tutorial: Bootstrapping the
Partitioning Hypervisor Jailhouse"
system.
Ralf
On Fri, May 3, 2024 at 5:31 PM Ralf Ramsauer
<mailto:ralf.ramsa...@oth-regensburg.de>> wrote:
Hi,
On 02/05/2024 15:45, Syed Aftab Rashid wrote:
[snip]
> > I just wanted to understand what is the best possible
jitter that
>
Hi,
On 02/05/2024 15:45, Syed Aftab Rashid wrote:
[snip]
> I just wanted to understand what is the best possible jitter that
I can
> get with Jailhouse. We are working on a project that needs cycle
times
> between 1-2 microseconds. The bare metal implementation of a
On 18/02/2024 12:03, Jan Kiszka wrote:
On 16.02.24 20:36, Ralf Ramsauer wrote:
Devices slightly changed with recent Qemu versions. Adapt changes of
device topology.
Signed-off-by: Ralf Ramsauer
---
Tested with jailhouse enable, create, disable + apic demo.
README.md | 2
Devices slightly changed with recent Qemu versions. Adapt changes of
device topology.
Signed-off-by: Ralf Ramsauer
---
Tested with jailhouse enable, create, disable + apic demo.
README.md | 2 +-
configs/x86/qemu-x86.c | 80 +-
2 files
On 01/02/2024 11:32, Syed Aftab Rashid wrote:
Hi all,
I am trying to install Jailhouse on a Ubuntu VM running using VMware
inside a Windows 10 host system. I am following the instruction provided
here
Don't do it. Use Qemu/KVM with Linux as host, as described in the
README. For building
of the config. It has
to come *after* struct pio_regions and before pci_caps. Position is
important for the internal parsing.
In your case, it the parser will hit some bogus data.
Ralf
Thanks,
Michele
Il giorno mercoledì 17 gennaio 2024 alle 11:52:18 UTC+1 Ralf Ramsauer ha
scritto:
Hi
VSHMEM_NET is enabled in
both the root and non root kernel config, I also enabled
CONFIG_PCI_HOST_GENERIC in the root linux as suggested in one of the
conversations on this site.
Thanks,
Michele
Il giorno domenica 14 gennaio 2024 alle 15:49:40 UTC+1 Ralf Ramsauer ha
scritto:
Hi Mic
2024 alle 21:09:28 UTC+1 Ralf Ramsauer ha
scritto:
Hi Michele,
On 13/01/2024 18:08, Michele Pescapè wrote:
> Hi,
>
> The problem was that the ram regions in the non root configuration
> weren't detected as such because of the missing JAILHOUSE_MEM_
on those ivshmem net devices.
If you need ivshmem, then this would be the next step.
Ralf
Thanks,
Michele
Il giorno sabato 13 gennaio 2024 alle 15:13:12 UTC+1 Ralf Ramsauer ha
scritto:
Hi,
On 13/01/2024 12:28, Michele Pescapè wrote:
> Hi,
>
> You are rig
sabato 13 gennaio 2024 alle 00:05:43 UTC+1 Ralf Ramsauer ha
scritto:
Hi Michele,
On 12/01/2024 14:07, Michele Pescapè wrote:
> jailhouse cell load linux-2 linux-loader.bin -a 0x0
> ../buildroot-2023.11/output/images/bzImage -a 0xffbe00 parameters
-a 0x1000
Hi Michele,
On 12/01/2024 14:07, Michele Pescapè wrote:
jailhouse cell load linux-2 linux-loader.bin -a 0x0
../buildroot-2023.11/output/images/bzImage -a 0xffbe00 parameters -a 0x1000
jailhouse cell start linux-2
I take it the kernel is loaded at 0xffbe00 which is right at the edge of
the
Hi,
On 12/01/2024 14:07, Michele Pescapè wrote:
I'll attach again the non root config, however it isn't much different
than the other I sent, i only fixed the weird alignment and changed a
bit the start addresses of the comm region and the high ram region.
ah, and btw, just had a look at it:
bit the start addresses of the comm region and the high ram region.
Thanks,
Michele
Il giorno giovedì 11 gennaio 2024 alle 21:55:47 UTC+1 Ralf Ramsauer ha
scritto:
Hi,
On 11/01/2024 13:57, Michele Pescapè wrote:
> Hi,
>
> after changing the virt_start to
ew MBs. With a kernel of that size, you might want to play
around with jailhouse-cell-linux -k.
Ralf
Thanks,
Michele
Il giorno mercoledì 10 gennaio 2024 alle 20:58:03 UTC+1 Ralf Ramsauer ha
scritto:
Hi Michele,
On 10/01/2024 17:40, Michele Pescapè wrote:
> Hi,
>
UTC+1 Ralf Ramsauer ha
scritto:
Hi,
On 09/01/2024 19:58, Michele Pescapè wrote:
> Hi,
>
> Just an update, I was able to get the following output by adding -c
> "earlyprintk=ttyS0,115200" to the command line:
>
regions out I no longer get that freeze. CONFIG_JAILHOUSE_GUEST and
CONFIG_JAILHOUSE_DBCON were already set in the kernel
configuration I'm using for the non root linux; still, I
recompiled it just in case.
Michele
Il giorno martedì 9 gennaio 2024 alle 14:14:
Hi,
On 08/01/2024 23:56, Michele Pescapè wrote:
Hi all,
I have an AMD Ryzen 2600 on a b450 motherboard. My goal is to run two
non root linux cells, however, as of right now, I'm not able to start
any non root linux cells.
First of all I don't receive an output from the cell (I do get output
, January 8, 2024 at 7:12:46 PM UTC+8 Ralf Ramsauer wrote:
Hi,
On 08/01/2024 09:26, wheatfox wrote:
> I'm using OK8MP board with i.MX8MP CPU. I have already
started jailhouse
> with imx8mp.cell configuration, and the example gic-demo
work
...)
The current full output log is attached as attachment.
On Monday, January 8, 2024 at 7:12:46 PM UTC+8 Ralf Ramsauer wrote:
Hi,
On 08/01/2024 09:26, wheatfox wrote:
> I'm using OK8MP board with i.MX8MP CPU. I have already started
jailhouse
> with imx8mp.cell configu
Hi,
On 08/01/2024 09:26, wheatfox wrote:
I'm using OK8MP board with i.MX8MP CPU. I have already started jailhouse
with imx8mp.cell configuration, and the example gic-demo works fine.
However, when I try to start a linux inmate using
imx8mp-linux-demo.cell, the jailhouse's load progress seems
Hi Benoit,
On 02/01/2024 17:03, Benoit wrote:
Hello,
I have an Odroid H3+ (Intel N6005 - 4 cores) with 8GB RAM.
I successfully recompiled the kernel (5.10) with jailhouse support and
installed jailhouse
Loading the kernel module works fine but the following steps make my
system unstable and
On 04/01/2024 11:27, Dave Marples wrote:
The patch is pretty straightforward and attached to the message above,
but in case you're having trouble getting it here it is as text;
```diff --git a/mm/vmalloc.c b/mm/vmalloc.c index
52f50fe7db83..7fbfad571968 100644 --- a/mm/vmalloc.c +++
On 25/11/2023 07:57, 杨竣轶 wrote:
I'm using a OKMX8MQ-C which from imx8, now i can boot the root cell and
some simple demp such as gic-demo. But when boot the non-root linux
cell, i face some problem.
I only use initramfs to boot non-root linux. Furthermore, my initramfs
only contains a
any new suggestions or hypotheses ?
One further thought, see below.
Thanks in advance,
Le mercredi 22 novembre 2023 à 16:34:10 UTC+1, Ralf Ramsauer a écrit :
Hi,
On 22/11/2023 16:14, Laurent Corbin wrote:
> Hi all,
>
> I'm trying to run jailhouse on LX2160
Hi,
On 23/11/2023 05:25, xin zhang wrote:
In none root cell, start command is :
jailhouse cell linux -i /home/file/rootfs.cpio -d
configs/arm64/dts/AMA0.dtb configs/arm64/linux.cell /home/file/Image -c
"console=ttyAMA0,115200 root=/dev/ram0 ramdisk_size=0x100
earlycon=pl011,0x2800"
On 23/11/2023 04:33, '张平' via Jailhouse wrote:
>On 22/11/2023 06:53, '张平' via Jailhouse wrote:
>> I am trying to transplant jailhouse on the A55 core, but now I have
>> encountered some problems. After I execute the following command, the
>> system will freeze.
>> $ jailhouse enable
Hi,
On 22/11/2023 16:14, Laurent Corbin wrote:
Hi all,
I'm trying to run jailhouse on LX2160ardb (NXP board). To do that,
1. I wrote a cell file for my root cell.
2. I built a Linux 6.1 and a jailhouse (branch lf-6.1.36_2.1.0 from nxp
mirror) with yocto.
3. I loaded the jailhouse driver as a
On 22/11/2023 07:25, xin zhang wrote:
when I run linux image on jailhouse, guset serial port print follow
errors: where I can get ways to sovle it？
Please provide more context. Does this happen in the root or non-root cell?
Ralf
[ 0.069576][ 0] [ T0] Mount-cache hash table
On 22/11/2023 06:53, '张平' via Jailhouse wrote:
I am trying to transplant jailhouse on the A55 core, but now I have
encountered some problems. After I execute the following command, the
system will freeze.
$ jailhouse enable renesas-r9a07g044l2.cell
No error log? Is the debug console
Hi Paresh,
On 21/11/2023 05:30, Paresh Bhagat wrote:
Update. Got the jailhouse enabled but still getting the pci error.
nitializing Jailhouse hypervisor v0.12 (324-ge57d1eff-dirty) on CPU 3
Code location: 0xc0200800
Page pool usage after early setup: mem 39/993, remap 0/131072
Hi Chris,
On 20/11/2023 14:37, Chris Paterson wrote:
Hello Jailhouse maintainers,
I was just looking at Jailhouse GitHub repo [0] and it looks like the master
branch hasn't been updated for a while (10 months).
Is this project still active?
Yes, we're currently still working on the RISC-V
web visit
https://groups.google.com/d/msgid/jailhouse-dev/89d7ee90-8781-4db0-ad76-b045f1844eb2n%40googlegroups.com <https://groups.google.com/d/msgid/jailhouse-dev/89d7ee90-8781-4db0-ad76-b045f1844eb2n%40googlegroups.com?utm_medium=email_source=footer>.
--
Ralf Ramsauer
PGP: 0xC85252CC
--
You receive
On 14/11/2023 07:31, xin zhang wrote:
What is the reason for the following error printed when using Jailhouse
to start Linux in Linux? Replacing the image is also not feasible
the error log as follows：
[ 0.092570][ 0] Unable to handle kernel paging request at virtual
address
Hi Tony,
On 06/11/2023 12:06, Tony wrote:
Hello everyone.
I am trying to load a binary as a non-root cell of Jailhouse and run it
on the Ultrascale ZCU104. Within this binary there are serial prints
executed via xil_printf that I do not see in output when I run the
binary on jailhouse. I
Nallathambi
On Wednesday, 11 October 2023 at 01:26:19 UTC+5:30 Ralf Ramsauer wrote:
On 10/10/2023 17:17, Bharathiraja Nallathambi wrote:
> Hi,
>
> I was trying jailhouse with a linux inmate on an imx8mp-evk board. I
> have created a yocto build with jailhouse an
On 17/10/2023 19:22, Dave Marples wrote:
Grr, my build suffered User Error. Once I built it properly everthing
starts to work much better. Thanks for the help!!
Ah - just wanted to mention to make sure that you booted the right
kernel. Excellent, good to hear!
Ralf
# jailhouse
On 17/10/2023 15:04, Dave Marples wrote:
On 17/10/2023 09:48, Dave Marples wrote:
I'm building jailhouse on a arm64 linux 6.1 Debian bookworm system
(imx8m, if it matters) using gcc 12.2.0...or, more specfically,
failing to build. I get to the module install stage and then get;
ERROR:
On 10/10/2023 17:17, Bharathiraja Nallathambi wrote:
Hi,
I was trying jailhouse with a linux inmate on an imx8mp-evk board. I
have created a yocto build with jailhouse and linux kernel 6.1.22-rt8
which is having the patches for real time linux.
Booted the board with running run
Hi Sara,
On 05/10/2023 11:50, Sara Alonso wrote:
Hi!
I want to create an inmate where I generate a periodic interrupt with a
TTC timer (I am using a zynq zcu102 board). The address of the TTC is
0xFF12 and the interrupt number is 71. I am writing the c code for
the inmate and I have
day, September 9, 2023 at 7:38:59 PM UTC+8 Ralf Ramsauer wrote:
On 09/09/2023 08:04, bot crack wrote:
> Hi, everybody
>
> I encountered some problems when using ivshmem-demo. How should I
set
> the value of pci_mmconfig_base?
Set it to a region where it
On 09/09/2023 08:04, bot crack wrote:
Hi, everybody
I encountered some problems when using ivshmem-demo. How should I set
the value of pci_mmconfig_base?
Set it to a region where it does physically not collide with any other
IO/Memory.
my rootcell:
/.platform_info = {
s://github.com/bminor/binutils-gdb/blob/33a0b291058120c1294e90b53a5299c3ec62bad9/opcodes/aarch64-opc.c#L4944
Ralf
On Wednesday, September 6, 2023 at 10:14:30 PM UTC+8 Ralf Ramsauer wrote:
On 06/09/2023 03:40, bot crack wrote:
> Hi
>
> 1. I want to add some registe
On 06/09/2023 03:40, bot crack wrote:
Hi
1. I want to add some register definitions.
2. I want to know why #define CNTPCT_EL0 SYSREG_64(0, c14) in arm64
*has only two arguments*, but it can be expanded into assembly "MRS
X0, #3, c14, c0, #1"
oh yeah, that's finest macro magic!
f5-6ca0cc93fcb2n%40googlegroups.com <https://groups.google.com/d/msgid/jailhouse-dev/a5a7147d-750d-4000-87f5-6ca0cc93fcb2n%40googlegroups.com?utm_medium=email_source=footer>.
--
Mit freundlichen Grüßen
Dr. Ralf Ramsauer
Labor für Digitalisierung
Fakultät für Informatik und Mathematik
Ostbayerische
On 04/09/2023 10:11, bot crack wrote:
The jailhouse system hangs when running on the 4*A55 board
jailhouse-config-check:
/Reading configuration set:
Architecture: arm64
Root cell: RootCell (a55-main.cell)
Overlapping memory regions inside cell: None
Overlapping memory regions with
r/arch/x86/paging.c#L134C4-L134C35
Besides 4k pages, you also have 2M and 1G pages. However, 1G pages
require, that the physical and virtual address are 1G-aligned.
Ralf
Thanks
Jan.
Ralf Ramsauer schrieb am Mittwoch, 26. Juli 2023 um 15:48:44 UTC+2:
On 26/07/2023 14:41, Jan-Marc St
must map tons of 4k-Pages to cover that
memory region. Mapping those pages requires memory for page tables, and
apparently, 6MiB weren't sufficient.
Thanks
Ralf
Jan-Marc.
Ralf Ramsauer schrieb am Mittwoch, 26. Juli 2023 um 13:12:02 UTC+2:
On 26/07/2023 12:56, Jan-Marc Stranz wrote:
On 26/07/2023 12:56, Jan-Marc Stranz wrote:
Of course, I checked the configuration for the root cell with "jailhouse
config check".
However, this is not changed at all while I change the configuration for
the guest cells.
Also, everything is fine as long as I don't set the size for the
On 26/07/2023 10:14, Jan-Marc Stranz wrote:
I have a HW target with Intel core i5 (11th generation) and 32 GB RAM.
In the hypervisor configuration for the root cell, 1 GiB (1024 MiB) is
reserved for guest cells:
/* MemRegion: 11060-1505f : guest cells (1024 MiB) */
Hi,
On 13/07/2023 16:42, Jan-Marc Stranz wrote:
Is there a way and the corresponding rules to simplify the hypervisor
configuration for the root cell?
I have a hypervisor configuration for the root cell with 99 entries for
"MemRegion".
I am now trying to merge these regions together.
My
images. There,
are required patches and config tweaks are included out of the box.
Ralf
JAILHOUSE_ENABLE: Invalid argument*
ubuntu@ubuntu:~/jailhouse$
I am getting the above error.
Regards,
Sai Krishna
On Monday, June 19, 2023 at 8:09:37 PM UTC+5:30 Ralf Ramsauer wrote:
On 19/06/2023
sue to get the
installation success.
Regards,
Sai Krishna
On Monday, June 19, 2023 at 4:25:09 PM UTC+5:30 Ralf Ramsauer wrote:
On 19/06/2023 12:23, sai krishna Allu wrote:
> Hi Ralf,
>
> I have attached the hypervisor.o and I have taken the dump of
that which
jailhouse,
and see if the error still occurs there?
Thanks,
Ralf
Regards,
Sai Krishna
On Saturday, June 17, 2023 at 8:59:56 PM UTC+5:30 Ralf Ramsauer wrote:
Hi,
On 15/06/2023 10:11, sai krishna Allu wrote:
> Hi Team,
>
> I have Raspberry Pi 4, which is insta
Hi,
On 15/06/2023 10:11, sai krishna Allu wrote:
Hi Team,
I have Raspberry Pi 4, which is installed with Ubuntu 20.04.5 LTS 64 bit.
after loading the jailhouse.ko file, when I gave following command I am
getting the exception.
ubuntu@ubuntu:~/jailhouse$ sudo jailhouse enable
Hi Peng,
On 16/06/2023 03:50, Peng Fan wrote:
NXP adoption of jailhouse hypervisor
https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/harpoon-rtos-on-cortex-a:HARPOON
Uh, very nice! Thanks for the pointer and for the work!
FYI: We just successfully enabled
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/include/asm/csr64.h | 1 +
hypervisor/arch/riscv/setup.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hypervisor/arch/riscv/include/asm/csr64.h
b/hypervisor/arch/riscv/include/asm/csr64.h
index
If an IMSIC is available, i.e., when a valid VS-mode File is set in the
configuration, then migrate corresponding CSR registers over to the
target VS-mode file. Undo it, when disabling jailhouse.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/control.c| 5 ++
hypervisor
At least on Qemu, we might have the case that external interrupts stuck
pending in hip when enabling the hypervisor. This happens, if a IRQ is
set pending before it got migrated to the guest. This might be a
misbehaviour in Qemu.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/setup.c
architectures.
Signed-off-by: Ralf Ramsauer
---
hypervisor/control.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hypervisor/control.c b/hypervisor/control.c
index 7a5304a0..38b9086c 100644
--- a/hypervisor/control.c
+++ b/hypervisor/control.c
@@ -368,10 +368,10 @@ static
jailhouse is disabled.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/pci.c | 86 ++---
1 file changed, 80 insertions(+), 6 deletions(-)
diff --git a/hypervisor/arch/riscv/pci.c b/hypervisor/arch/riscv/pci.c
index 067a7651..39e1e4cb 100644
--- a/hypervisor/arch
trap
is required: for sending the IRQ.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/aplic.c | 202 ++--
hypervisor/arch/riscv/include/asm/cell.h| 1 +
hypervisor/arch/riscv/include/asm/irqchip.h | 1 +
hypervisor/arch/riscv/irqchip.c
Idea is as follows: Specify the target VS-file in the configuration, and
use simple memory regions to overlay the S-Mode file.
Signed-off-by: Ralf Ramsauer
---
.../dts/qemu-linux-inmate-aplic-imsic.dts | 124 ++
configs/riscv/qemu-aplic-imsic-mc.c | 5 +
configs
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/aplic.c | 147 -
hypervisor/arch/riscv/include/asm/cell.h | 12 ++
hypervisor/arch/riscv/include/asm/percpu.h | 1 +
3 files changed, 159 insertions(+), 1 deletion(-)
diff --git a/hypervisor/arch/riscv
For demonstration purposes only.
Signed-off-by: Ralf Ramsauer
---
configs/riscv/qemu-aplic-mc.c | 1 +
configs/riscv/qemu-aplic-uc.c | 1 +
configs/riscv/qemu-layout.h | 1 -
configs/riscv/qemu-linux-demo-aplic.c | 1 +
configs/riscv/qemu-linux-demo-plic.c | 1
wired IRQs as MSIs, and also
supports 'virtual MSIs' that can for example be used to model IPIs.
With the IMSIC, situation will get better for us.
Signed-off-by: Ralf Ramsauer
[since v2: inline single-caller functions, add shadow registers for
enabled, target and sourcecfg]
---
hypervisor/arch
For demonstration purposes only.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/control.c | 2 +
hypervisor/arch/riscv/include/asm/cell.h| 3 +
hypervisor/arch/riscv/include/asm/irqchip.h | 16 +++
hypervisor/arch/riscv/include/asm/ivshmem.h | 1 +
hypervisor/arch
This bug went away with linux 6.0
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/plic.c | 32 ++--
1 file changed, 6 insertions(+), 26 deletions(-)
diff --git a/hypervisor/arch/riscv/plic.c b/hypervisor/arch/riscv/plic.c
index a65de82c..4f4b64fc 100644
From: Stefan Huber
With this, introduce the APLIC irqchip type in cell-config.h.
Signed-off-by: Ralf Ramsauer
---
configs/riscv/dts/qemu-linux-inmate-aplic.dts | 111 ++
configs/riscv/qemu-aplic-mc.c | 3 +
configs/riscv/qemu-aplic-uc.c | 3
For demonstration purposes only.
Signed-off-by: Ralf Ramsauer
---
driver/pci.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/driver/pci.c b/driver/pci.c
index da516479..4f52eba8 100644
--- a/driver/pci.c
+++ b/driver/pci.c
@@ -292,19
From: Stefan Huber
add necessary files for developing tiny-demo inmate. Consists of
modified copies from x86/arm.
Signed-off-by: Stefan Huber
Signed-off-by: Ralf Ramsauer
---
.gitignore | 1 +
inmates/demos/riscv/Makefile| 19
inmates/demos/riscv/tiny
://drive.google.com/file/d/1f4DyxZMzl3yH7KGKXJFZ_iUY_AU9az_K/view
Signed-off-by: Ralf Ramsauer
[since RFC v2: If we have STCE, no need to forward the SBI call to
firmware. Simply 'inject' the timer to our guest via stimecmp. Add QEMU
workaround.]
---
hypervisor/arch/riscv/include/asm/csr64.h | 4
Signed-off-by: Ralf Ramsauer
---
configs/riscv/qemu-layout.h | 22
configs/riscv/qemu-plic-mc.c | 2 +
configs/riscv/qemu-plic-uc.c | 2 +
configs/riscv/qemu-riscv64.c | 65 --
configs/riscv/qemu.h | 244 +++
5 files changed, 270
Signed-off-by: Ralf Ramsauer
---
configs/riscv/qemu-inmate-demo.c | 1 +
configs/riscv/qemu-inmate-demo.h | 65
configs/riscv/qemu-layout.h | 6 +++
3 files changed, 72 insertions(+)
create mode 100644 configs/riscv/qemu-inmate-demo.c
create mode 100644
Same demo as for other architectures.
Signed-off-by: Ralf Ramsauer
---
inmates/demos/riscv/Makefile | 3 +-
inmates/demos/riscv/timer-demo.c | 57 +++
inmates/lib/riscv/Makefile | 2 +-
inmates/lib/riscv/header.S | 29
inmates/lib/riscv/include
The boot protocol is simple:
- a0 hold the hart id
- a1 hold the DTB
That's it.
Signed-off-by: Ralf Ramsauer
---
inmates/tools/riscv/Makefile | 19 +++
inmates/tools/riscv/linux-loader.c | 25 +
2 files changed, 44 insertions(+)
create mode
Signed-off-by: Ralf Ramsauer
[RFC v2: fix typo]
---
configs/riscv/dts/qemu-linux-inmate-plic.dts | 112 +++
configs/riscv/qemu-layout.h | 6 +
configs/riscv/qemu-linux-demo-plic.c | 2 +
configs/riscv/qemu-linux-demo.h | 103
Signed-off-by: Ralf Ramsauer
[since RFC v1: Add more fine granular SBI accounting, simplify usage of hlvx]
[since RFC v2: inline single-caller functions, improve rfence handler]
---
hypervisor/arch/riscv/traps.c | 793 +-
1 file changed, 788 insertions(+), 5
We will need the hartid for the linux-loader later.
Signed-off-by: Ralf Ramsauer
---
inmates/lib/riscv/header.S | 3 +++
inmates/lib/riscv/include/inmate.h | 2 ++
inmates/lib/riscv/setup.c | 2 ++
3 files changed, 7 insertions(+)
diff --git a/inmates/lib/riscv/header.S b
imed and acknowledged the IRQ.
After the guest acknowledged the IRQ, reenable IRQs in S-Mode again.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/Kbuild| 2 +-
hypervisor/arch/riscv/irqchip.c | 7 +-
hypervisor/arch/riscv/plic.c| 392
3 f
Later, we will add support for PLIC and APLIC. This irqchip layer adds a
level of abstraction for both irqchips, and will hold code that is
shared between both.
With this commit, fill irqchip.c with life, and and the common code for
both.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv
And do some heavy liftig.
Signed-off-by: Ralf Ramsauer
[RFC v2: allow access to cycle counter]
[RFC v2: get vmm deactivation under control (didn't work with -O2)]
---
hypervisor/arch/riscv/entry.S | 65 ++
hypervisor/arch/riscv/include/asm/csr64.h | 1 +
hypervisor/arch
We need this for RISC-V. Makes life easier.
Signed-off-by: Ralf Ramsauer
---
driver/main.c | 1 +
hypervisor/include/jailhouse/header.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/driver/main.c b/driver/main.c
index 51be11e2..373b77b2 100644
--- a/driver
Specifically on RISC-V, and fix some typos.
Signed-off-by: Ralf Ramsauer
---
Documentation/hypervisor-interfaces.txt | 16 ++--
Documentation/memory-layout.txt | 20
2 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/Documentation
Signed-off-by: Ralf Ramsauer
[since RFC v1: fix incorrect hsm state on cell reset]
[since RFC v2: fix parking state]
---
hypervisor/arch/riscv/control.c | 200 ++--
hypervisor/arch/riscv/include/asm/control.h | 13 ++
2 files changed, 196 insertions(+), 17 deletions
Which will contained shared definitions that are used by both, PLIC and
APLIC. The irqchip abstraction layer provides abstraction for both irq
controller variants.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/include/asm/irqchip.h | 87 +
1 file changed, 87
,
and we forward the IPI call to the SBI. Before, we set the cause to
IPI_CAUSE_GUEST.
Follow the same logic for management IPIs accordingly.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/control.c | 33 +
1 file changed, 33 insertions(+)
diff --git
euse them when disabling the hypervisor, or when errors occur during
startup.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/Kbuild | 4 +-
hypervisor/arch/riscv/entry.S | 349 +-
hypervisor/arch/riscv/exception.S | 91 +
unlikely
that we need a GP address that is very very high. Independant of the
G-Stage paging, the guest may use any available paging method that it
wants. This means, Linux may enable SV57 paging on top of a SV39
G-stage.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/paging.c| 261
Signed-off-by: Ralf Ramsauer
[RFC v2: fix incorrect asm specifiers]
---
hypervisor/arch/riscv/include/asm/spinlock.h | 52 +++-
1 file changed, 50 insertions(+), 2 deletions(-)
diff --git a/hypervisor/arch/riscv/include/asm/spinlock.h
b/hypervisor/arch/riscv/include/asm
We need this macro on RISC-V.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/arm-common/irqchip.c | 5 -
hypervisor/include/jailhouse/control.h | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hypervisor/arch/arm-common/irqchip.c
b/hypervisor/arch/arm-common
s, use FID = 'JHOU' and EID shall represent the hypercall
number.
Signed-off-by: Ralf Ramsauer
---
include/arch/riscv/asm/jailhouse_hypercall.h | 61
1 file changed, 49 insertions(+), 12 deletions(-)
diff --git a/include/arch/riscv/asm/jailhouse_hypercall.h
b/include/arch
Export offsets that we will later need in assembly.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/asm-defines.c| 27 ++
hypervisor/include/jailhouse/gen-defines.h | 8 ++-
2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/hypervisor/arch
is
allowed to manage.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/include/asm/cell.h | 11 +++
hypervisor/arch/riscv/include/asm/types.h | 1 +
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/hypervisor/arch/riscv/include/asm/cell.h
b/hypervisor/arch/riscv/include
On RISC-V, the logical CPU ID should be the same as Linux's ID. A
logical CPU ID is mapped to a HART, the physical ID (phys_id).
All communication with the SBI interface require specification of
physical HART IDs.
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/control.c | 7
and reuse the
stack, while the hypervisor is active.
So if we're trapping the hypervisor, we will later end up in
arch_handle_trap. If we get a fault while we're inside the hypervisor,
we will end up in arch_handle_fault.
These routines will be called from assembly.
Signed-off-by: Ralf Ramsauer
Signed-off-by: Ralf Ramsauer
---
hypervisor/arch/riscv/include/asm/paging.h| 106 --
.../arch/riscv/include/asm/paging_modes.h | 18 +++
hypervisor/include/jailhouse/header.h | 5 +
3 files changed, 118 insertions(+), 11 deletions(-)
diff --git a/hypervisor
(a) to discover it and (b) statically patch the instruction to the
routine. Simply don't use it for those reasons...
Signed-off-by: Ralf Ramsauer
[since RFC v1: use div for cpu_relax()]
[since RFC v2: add interrupt control routines]
---
hypervisor/arch/riscv/include/asm/processor.h | 71
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