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Branch: refs/heads/master
Home: https://github.com/jallib/jallib
Commit: 0a6bd3637b9046eb5ea1d7e787be8e0b1e0ba1b5
https://github.com/jallib/jallib/commit/0a6bd3637b9046eb5ea1d7e787be8e0b1e0ba1b5
Author: Rob Jansen <12682653+robjanse...@users.noreply.github.com>
Date:
Hi Vasili,
On 01/10/2021 13.11, vsurducan wrote:
Hi Rob and Rob, :)
I've tried with or without ISR, with AND IOCAP reset or normal IOCAP
reset. This IOC is erratic and has a lot of latency. The RDY_IN signal
is 20ms square 50% duty cycle, the RDY_OUT signal has a latency most
of the
Hi!
That's something else, I think it's called "fast interrupt" or the like. It's
not such an easy thing, as it restricts a project to have only *one* ISR
(=Interrupt Service Routine), which, e.g. with the serial_hw_int_cts library is
not possible as that library uses interrupts transparently
Hi Rob, Kiste,
I'm not sure on the actual compiler, but one of old pragma interrupt
versions allows you to save, restore all registers and retfie manually at
your need.
I still believe it was a great option.
On Fri, Oct 1, 2021 at 8:46 PM Rob Hamerling wrote:
>
> Hello Kiste,
>
> On 01/10/2021
