[Kicad-developers] [PATCH] Avoid initialization from non-constexpr

2017-07-26 Thread Simon Richter
In-class initializers for "static const" class members must be constexpr, however std::string is only "static const" itself and cannot be used without compiler extensions. --- include/utf8.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/utf8.h b/include/utf8.h

Re: [Kicad-developers] Netclass and clearance

2017-07-26 Thread Tomasz Wlostowski
On 26.07.2017 22:01, Wayne Stambaugh wrote: > On 7/26/2017 9:47 AM, hauptmech wrote: >> This is a nice concept. A more generic constraint system. >> >> What I'll be doing and was asking if there was others needing, is the >> pre-net-class approach of a single clearance that is easily adjusted >>

Re: [Kicad-developers] Netclass and clearance

2017-07-26 Thread Marcos Chaparro
A couple of examples of extra clearance options requested https://bugs.launchpad.net/kicad/+bug/1510742 And the following one really bugs me for high power igbt drivers https://bugs.launchpad.net/kicad/+bug/983230 This board would benefit from this.

Re: [Kicad-developers] Netclass and clearance

2017-07-26 Thread Wayne Stambaugh
On 7/26/2017 9:47 AM, hauptmech wrote: > This is a nice concept. A more generic constraint system. > > What I'll be doing and was asking if there was others needing, is the > pre-net-class approach of a single clearance that is easily adjusted > while laying tracks. What you want is a change to

[Kicad-developers] UTF8 class.

2017-07-26 Thread Wayne Stambaugh
I just pushed a patch set from Dick to fix the UTF8 class issue that Chris fixed by replacing it with the effective but rather ugly FROM_UTF8 macro. This bug was really nasty. It appears that the change to c++11 was the culprit by causing wxString(std::string) to be called in certain

Re: [Kicad-developers] Netclass and clearance

2017-07-26 Thread hauptmech
This is a nice concept. A more generic constraint system. What I'll be doing and was asking if there was others needing, is the pre-net-class approach of a single clearance that is easily adjusted while laying tracks. I think this used to be there. Having it would not affect netclass

Re: [Kicad-developers] Netclass and clearance

2017-07-26 Thread Wayne Stambaugh
I would not be opposed to adding more complex constraints to net classes but I would ask that the DRC changes to test any new constraints be added at the same time. Users (myself included) will expect the DRC to validate these constraints. On 7/26/2017 9:17 AM, Maciej Sumiński wrote: > Hi

Re: [Kicad-developers] Netclass and clearance

2017-07-26 Thread Maciej Sumiński
Hi hauptmech, I am sure there are many users who would benefit from the suggested DRC improvements, so I would say it is an interesting idea. There is a plan to upgrade it, but I am afraid you will have you board finished before this happens. It is not entirely clear to me what do you propose.

Re: [Kicad-developers] Performance issues in pcbnew

2017-07-26 Thread hauptmech
Could you test this patch, and see if it changes something in performance issues in pcbnew? Thanks. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe :

Re: [Kicad-developers] Performance issues in pcbnew

2017-07-26 Thread hauptmech
On 26/07/17 20:11, jp charras wrote: Could you test this patch, and see if it changes something in performance issues in pcbnew? Thanks. -- Jean-Pierre CHARRAS Wow! Night and day. For pan and zoom my frame rate is now interactive. Subjectively it was somewhere between 0.5 and 2 frames per

Re: [Kicad-developers] Performance issues in pcbnew

2017-07-26 Thread jp charras
Le 25/07/2017 à 05:09, hauptmech a écrit : > > This would be a demo for testing only. I'll have to obfuscate and sabatoge > parts. Still useful? > > > On 25/07/17 02:07, Wayne Stambaugh wrote: >> I would accept a patch for a more complex demo for performance testing >> purposes. >> >> On

[Kicad-developers] Netclass and clearance

2017-07-26 Thread hauptmech
I have nets that have different clearance requirements depending on where they are. There are two situations that are in my designs: 1) Technical/Manufacturing limitations: Trace and space limitations depend on layer copper thickness and whether it's an inner layer or outer layer. For