On Wed, Nov 28, 2012 at 8:11 AM, Will Deacon wrote:
> On Sat, Nov 10, 2012 at 03:44:51PM +, Christoffer Dall wrote:
>> User space defines the model to emulate to a guest and should therefore
>> decide which addresses are used for both the virtual CPU interface
>> directly mapped in the guest p
[...]
>> diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
>> index 2fb7319..665af96 100644
>> --- a/virt/kvm/kvm_main.c
>> +++ b/virt/kvm/kvm_main.c
>> @@ -1880,12 +1880,13 @@ static long kvm_vcpu_ioctl(struct file *filp,
>> if (vcpu->kvm->mm != current->mm)
>> return -EI
On Fri, Nov 23, 2012 at 11:31 AM, Will Deacon wrote:
> On Sat, Nov 10, 2012 at 03:46:32PM +, Christoffer Dall wrote:
>> From: Marc Zyngier
>>
>> It is now possible to select CONFIG_KVM_ARM_TIMER to enable the
>> KVM architected timer support.
>>
>> Signed-off-by: Marc Zyngier
>> Signed-off-b
On Fri, Nov 23, 2012 at 12:04 PM, Marc Zyngier wrote:
> On 23/11/12 16:30, Will Deacon wrote:
>> On Sat, Nov 10, 2012 at 03:46:25PM +, Christoffer Dall wrote:
>>> From: Marc Zyngier
>>>
>>> Do the necessary save/restore dance for the timers in the world
>>> switch code. In the process, allow
On Fri, Nov 23, 2012 at 12:11 PM, Marc Zyngier wrote:
> On 23/11/12 17:00, Will Deacon wrote:
>> On Fri, Nov 23, 2012 at 04:52:12PM +, Marc Zyngier wrote:
>>> On 23/11/12 16:17, Will Deacon wrote:
> diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c
> index b80256b..7463f5b 10064
On Wed, Nov 28, 2012 at 7:47 AM, Will Deacon wrote:
> Just a bunch of typos in this one :)
>
> On Sat, Nov 10, 2012 at 03:44:30PM +, Christoffer Dall wrote:
>> From: Marc Zyngier
>>
>> When an interrupt occurs for the guest, it is sometimes necessary
>> to find out which vcpu was running at t
On Fri, Nov 23, 2012 at 10:23 AM, Will Deacon wrote:
> On Sat, Nov 10, 2012 at 03:46:12PM +, Christoffer Dall wrote:
>> From: Marc Zyngier
>>
>> Add some very minimal architected timer related infrastructure.
>> For the moment, we just provide empty structures, and enable/disable
>> access to
On Mon, Nov 19, 2012 at 10:07 AM, Will Deacon wrote:
> On Sat, Nov 10, 2012 at 03:43:42PM +, Christoffer Dall wrote:
>> Handles the guest faults in KVM by mapping in corresponding user pages
>> in the 2nd stage page tables.
>>
>> We invalidate the instruction cache by MVA whenever we map a pag
Thanks Marcelo!
> -Original Message-
> From: Marcelo Tosatti [mailto:mtosa...@redhat.com]
> Sent: Friday, November 30, 2012 12:40 PM
> To: Auld, Will
> Cc: qemu-devel; Gleb; Andreas Farber; kvm@vger.kernel.org; Dugger,
> Donald D; Liu, Jinsong; Zhang, Xiantao; a...@redhat.com
> Subject: Re
On Fri, Nov 30, 2012 at 10:36:43AM +0900, Yoshihiro YUNOMAE wrote:
> Hi Marcelo,
>
> >>>Can you please write a succint but complete description of the method
> >>>so it can be verified?
> >>
> >>Sure.
> >>
> >>- Prerequisite
> >>1. the host TSC is synchronized and stable.
> >>2. kvm_write_tsc_offs
On Mon, Nov 26, 2012 at 09:32:18PM -0800, Will Auld wrote:
> CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
>
> Basic design is to emulate the MSR by allowing reads and writes to the
> hypervisor vcpu specific locations to store the value of the emulated MSRs.
> In this way the
On Wed, Nov 28, 2012 at 08:54:14PM +0800, Xiao Guangrong wrote:
> vmcs->cpu indicates whether it exists on the target cpu, -1 means the vmcs
> does not exist on any vcpu
>
> If vcpu load vmcs with vmcs.cpu = -1, it can be directly added to cpu's percpu
> list. The list can be corrupted if the cpu
On Thu, Nov 29, 2012 at 02:07:59PM -0700, Alex Williamson wrote:
> Prior to memory slot sorting this loop compared all of the user memory
> slots for overlap with new entries. With memory slot sorting, we're
> just checking some number of entries in the array that may or may not
> be user slots.
On Thu, Nov 29, 2012 at 12:41:19PM -0800, Will Auld wrote:
> I have re-based this patch set version (V6) to kvm.git's queue branch.
>
> Will Auld (2):
> Add code to track call origin for msr assignment.
> Enabling IA32_TSC_ADJUST for KVM guest VM support
Applied, thanks.
--
To unsubscribe
On Mon, Nov 19, 2012 at 10:01 AM, Will Deacon wrote:
> On Sat, Nov 10, 2012 at 03:43:13PM +, Christoffer Dall wrote:
>> Adds a new important function in the main KVM/ARM code called
>> handle_exit() which is called from kvm_arch_vcpu_ioctl_run() on returns
>> from guest execution. This functio
kvm_irqchip_in_kernel() has an architecture specific meaning, so
we shouldn't be using it to determine whether to enabled KVM INTx
bypass. kvm_irqfds_enabled() seems most appropriate. Also use this
to protect our other call to kvm_check_extension() as that explodes
when KVM isn't enabled. Post 1
On Fri, Nov 30, 2012 at 12:14 PM, Will Deacon wrote:
> On Fri, Nov 30, 2012 at 04:47:40PM +, Christoffer Dall wrote:
>> On Fri, Nov 30, 2012 at 10:15 AM, Will Deacon wrote:
>> > At this point, VM1 is running and VM0:VCPU1 is running. VM0:VCPU0 is not
>> > running because physical CPU0 is hand
On Fri, 2012-11-30 at 18:57 +, Peter Maydell wrote:
> On 27 November 2012 19:45, Alex Williamson wrote:
> > kvm_check_extension() explodes when KVM isn't enabled so we need to
> > first test whether KVM is enabled. Use kvm_irqchip_in_kernel() for
> > this since it matches the test we do befor
On 27 November 2012 19:45, Alex Williamson wrote:
> kvm_check_extension() explodes when KVM isn't enabled so we need to
> first test whether KVM is enabled. Use kvm_irqchip_in_kernel() for
> this since it matches the test we do before using this result.
> --- a/hw/vfio_pci.c
> +++ b/hw/vfio_pci.
On Fri, Nov 30, 2012 at 04:47:40PM +, Christoffer Dall wrote:
> On Fri, Nov 30, 2012 at 10:15 AM, Will Deacon wrote:
> > At this point, VM1 is running and VM0:VCPU1 is running. VM0:VCPU0 is not
> > running because physical CPU0 is handling an interrupt. The problem is that
> > when VCPU0 *is*
On Fri, Nov 30, 2012 at 10:15 AM, Will Deacon wrote:
> On Fri, Nov 30, 2012 at 06:37:04AM +, Christoffer Dall wrote:
>> On Mon, Nov 19, 2012 at 9:57 AM, Will Deacon wrote:
>> >
>> > I must be missing something here: how do you ensure that a guest running
>> > on multiple CPUs continues to hav
On Fri, Nov 30, 2012 at 5:58 AM, Will Deacon wrote:
> On Thu, Nov 29, 2012 at 06:59:07PM +, Christoffer Dall wrote:
>> On Mon, Nov 19, 2012 at 9:16 AM, Will Deacon wrote:
>> >
>> > I also think it might be cleaner to declare the hyp_pgd next to the
>> > idmap_pgd then add the hyp_idmap_setup
On Fri, Nov 30, 2012 at 6:46 AM, Will Deacon wrote:
> On Thu, Nov 29, 2012 at 03:57:00PM +, Christoffer Dall wrote:
>> On Mon, Nov 19, 2012 at 9:14 AM, Will Deacon wrote:
>> > On Sat, Nov 10, 2012 at 03:42:17PM +, Christoffer Dall wrote:
>> >>
>> >> +#ifdef CONFIG_ARM_LPAE
>> >> +#define
On Fri, Nov 30, 2012 at 5:21 AM, Will Deacon wrote:
> On Thu, Nov 29, 2012 at 09:38:46PM +, Christoffer Dall wrote:
>> On Mon, Nov 19, 2012 at 9:21 AM, Will Deacon wrote:
>> > On Sat, Nov 10, 2012 at 03:42:31PM +, Christoffer Dall wrote:
>> >> Decoding the implementor and part number of t
On Fri, Nov 30, 2012 at 02:51:28PM +, Marc Zyngier wrote:
> A bug in the KVM GIC init code set the priority mask to the
> highest possible value, while the reset value should be zero.
>
> Now that the kernel bug is fixed, kvm-tool must properly configure
> its GIC CPU interface in order to rec
On Fri, Nov 30, 2012 at 06:37:04AM +, Christoffer Dall wrote:
> On Mon, Nov 19, 2012 at 9:57 AM, Will Deacon wrote:
> >
> > I must be missing something here: how do you ensure that a guest running
> > on multiple CPUs continues to have the same VMID across them after a
> > rollover?
> >
>
> w
A bug in the KVM GIC init code set the priority mask to the
highest possible value, while the reset value should be zero.
Now that the kernel bug is fixed, kvm-tool must properly configure
its GIC CPU interface in order to receive the boot IPI. Just set
the GICC_PMR register to the maximum value
On Mon, Nov 19, 2012 at 03:09:24PM +, Will Deacon wrote:
> On Sat, Nov 10, 2012 at 03:43:49PM +, Christoffer Dall wrote:
> > When the guest accesses I/O memory this will create data abort
> > exceptions and they are handled by decoding the HSR information
> > (physical address, read/write,
Am 27.11.2012 06:32, schrieb Will Auld:
> CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
>
> Basic design is to emulate the MSR by allowing reads and writes to the
> hypervisor vcpu specific locations to store the value of the emulated MSRs.
> In this way the IA32_TSC_ADJUST va
On Thu, Nov 29, 2012 at 03:57:00PM +, Christoffer Dall wrote:
> On Mon, Nov 19, 2012 at 9:14 AM, Will Deacon wrote:
> > On Sat, Nov 10, 2012 at 03:42:17PM +, Christoffer Dall wrote:
> >>
> >> +#ifdef CONFIG_ARM_LPAE
> >> +#define s2_policy(policy)policy
> >> +#else
> >> +#define s2_pol
On Thu, Nov 29, 2012 at 06:59:07PM +, Christoffer Dall wrote:
> On Mon, Nov 19, 2012 at 9:16 AM, Will Deacon wrote:
> >
> > I also think it might be cleaner to declare the hyp_pgd next to the
> > idmap_pgd then add the hyp_idmap_setup code to init_static_idmap, so
> > that we don't add new ent
On Thu, Nov 29, 2012 at 09:38:46PM +, Christoffer Dall wrote:
> On Mon, Nov 19, 2012 at 9:21 AM, Will Deacon wrote:
> > On Sat, Nov 10, 2012 at 03:42:31PM +, Christoffer Dall wrote:
> >> Decoding the implementor and part number of the CPU id in the CPU ID
> >> register is needed by KVM, so
On Thu, 29 Nov 2012, Marc Zyngier wrote:
> init.c is not very kind with processes that get reparented when
> their own parent die, leaving them hanging around. Looking at the
> code, it only seem to care about its own flesh and blood. Bad init.
>
> Teach it some basic zombie reaping skills.
>
> C
On Wed, 28 Nov 2012, Matt Evans wrote:
> On 2012-11-27 13:00, Will Deacon wrote:
> > Commit 8d35d32d0148 ("kvm tools: add generic device registration
> > mechanism") introduced a tree-based device lookup-by-bus mechanism as
> > well as iterators to enumerate the devices on a particular bus.
> >
>
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