[PATCH] Fix sysenter migration issue on AMD CPUs

. This worked fine for cross-vendor migration in compat mode, but did not work in pure legacy mode. To fix this we always intercept the SYSENTER MSRs and store the values both in the VMCB and the external variables. This works for all cases. Signed-off-by: Andre Przywara andre.przyw...@amd.com

Re: [PATCH] introduce kvm64 CPU

Glauber Costa wrote: On Fri, Aug 21, 2009 at 12:41 PM, Avi Kivitya...@redhat.com wrote: On 08/21/2009 12:34 AM, Andre Przywara wrote: In addition to the TCG based qemu64 type let's introduce a kvm64 CPU type, which is the least common denominator of all KVM-capable x86-CPUs (based on Intel

Re: [PATCH] introduce kvm64 CPU

Avi Kivity wrote: On 08/21/2009 12:34 AM, Andre Przywara wrote: In addition to the TCG based qemu64 type let's introduce a kvm64 CPU type, which is the least common denominator of all KVM-capable x86-CPUs (based on Intel Pentium 4 Prescott). It can be used as a base type for migration

[PATCH] introduce kvm64 CPU

In addition to the TCG based qemu64 type let's introduce a kvm64 CPU type, which is the least common denominator of all KVM-capable x86-CPUs (based on Intel Pentium 4 Prescott). It can be used as a base type for migration. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386

Re: Windows guest CPU socket/core recognition

is working fine, but I still have troubles with the Intel part and threads vs. cores (in the guest). I hope I can fix this still this week. Regards, Andre. -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message

Re: This combination of AMDprocessors is not suitable for SMP?

applies to non-KVM capable processors and has no meaning for virtual SMP anyway. If you like this warning to disappear, you can use -cpu host (and probably loose migration capability) or wait for the new safe64 CPU type, which will use family 15 instead of 6. Regards, Andre. -- Andre Przywara

[PATCH v2] add KVM module parameters documentation

Signed-off-by: Andre Przywara andre.przyw...@amd.com --- Documentation/kernel-parameters.txt | 39 +++ 1 files changed, 39 insertions(+), 0 deletions(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index d77fbd8

[PATCH] qemu-kvm: remove KVM misreports CPUID hack

This should be no longer necessary. Effectively reverts 143eb2bd043e82bcf353cf82d33c127f06411d82. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- kvm/libkvm/libkvm-x86.c |9 - qemu-kvm-x86.c |9 - 2 files changed, 0 insertions(+), 18 deletions(-) Hi Avi

[PATCH] handle AMD microcode MSR

Windows 7 tries to update the CPU's microcode on some processors, so we ignore the MSR write here. The patchlevel register is already handled (returning 0), because the MSR number is the same as Intel's. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86.c |1 + 1

[RFC] allow multi-core guests: introduce cores= option to -cpu

host,cores=8 with WindowsXP Pro. Regards, Andre. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpu.h|1 + target-i386/helper.c | 26 -- 2 files changed, 25 insertions(+), 2

Re: [RFC] allow multi-core guests: introduce cores= option to -cpu

Brian Jackson wrote: Andre Przywara wrote: currently SMP guests happen to see n vCPUs as n different sockets. Some guests (Windows comes to mind) have license restrictions and refuse to run on multi-socket machines. So lets introduce a cores= parameter to the -cpu option to let the user specify

Re: [Qemu-devel] [RFC] allow multi-core guests: introduce cores= option to -cpu

Samuel Thibault wrote: Andre Przywara, le Fri 03 Jul 2009 16:41:56 +0200, a écrit : -smp 16 -cpu host,cores=8 That means 8 cores with 2 threads each, thus 16 threads? No, that meant: 16 vCPUs total with 8 cores per physical packages. I don't have any notion for threads in the current code

Re: [Qemu-devel] [RFC] allow multi-core guests: introduce cores= option to -cpu

to specify a dual core guest. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 488-3567-12 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http

target-i386/kvm.c vs. qemu-kvm-x86.c

is not triggered. What is the future of these two files? Will one vanish? Will they be merged? Where to put new features in? Thanks and regards, Andre. -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord

[PATCH] fix MMIO_CONF_BASE MSR access

Some Windows versions check whether the BIOS has setup MMI/O for config space accesses on AMD Fam10h CPUs, we say no by returning 0 on reads and only allow disabling of MMI/O CfgSpace setup by igoring 0 writes. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86.c

[PATCH] qemu-kvm: preserve the hypervisor bit while KVM trims the CPUID bits

in qemu-kvm-x86.c, too. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- qemu-kvm-x86.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/qemu-kvm-x86.c b/qemu-kvm-x86.c index d6735c1..b02e604 100644 --- a/qemu-kvm-x86.c +++ b/qemu-kvm-x86.c @@ -1211,8 +1211,13

[PATCH v2] qemu-kvm: preserve the hypervisor bit while KVM trims the CPUID bits

in qemu-kvm-x86.c, too. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- qemu-kvm-x86.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) The last patch had a typo (and I compile tested the wrong branch), so here is the correct version. Regards, Andre. diff --git a/qemu-kvm

[PATCH] qemu-kvm: remove CPUID host hacks

KVM provides an in-kernel feature to disable CPUID bits that are not present in the current host. So there is no need here to duplicate this work. Additionally allows 3DNow! on capable processors, since the restriction seems to apply to QEMU/TCG only. Signed-off-by: Andre Przywara andre.przyw

[PATCH] add KVM module parameters documentation

Signed-off-by: Andre Przywara andre.przyw...@amd.com --- Documentation/kernel-parameters.txt | 38 +++ 1 files changed, 38 insertions(+), 0 deletions(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index d77fbd8

[Qemu-devel] KVMs default CPU type (was: allow sysenter on 32bit guests running on vmx host)

. You do not want to use -cpu host if you plan to migrate, another safer CPU type should be used then (the aforementioned -cpu migrate). Although preserving the boot CPU's vendor/family/model/stepping is something that one can think about... Regards, Andre. -- Andre Przywara AMD-OSRC (Dresden

[PATCH] introduce module parameter for ignoring unknown MSRs accesses

will return 0, while MSR writes are simply dropped. In both cases we print a message to dmesg to inform the user about that. You can change the behaviour at any time by saying: # echo 1 /sys/modules/kvm/parameters/ignore_msrs Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86.c

[PATCH] qemu-kvm: fix KVMs GET_SUPPORTED_CPUID feature usage

on the host and helps to use -cpu host. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- qemu-kvm-x86.c | 21 +++-- 1 files changed, 11 insertions(+), 10 deletions(-) Hi, this is a port of patch 4/6 of my -cpu host series for QEMU. The bug is similar, although the fix

[PATCH 2/4] ignore reads from AMDs C1E enabled MSR

If the Linux kernel detects an C1E capable AMD processor (K8 RevF and higher), it will access a certain MSR on every attempt to go to halt. Explicitly handle this read and return 0 to let KVM run a Linux guest with the native AMD host CPU propagated to the guest. Signed-off-by: Andre Przywara

[PATCH 3/4] ignore PCI ECS I/O enablement

Linux guests will try to enable access to the extended PCI config space via the I/O ports 0xCF8/0xCFC on AMD Fam10h CPU. Since we (currently?) don't use ECS, simply ignore this write attempt. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86.c |2 ++ 1 files changed

[PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e6e61ee..6ad0f93 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1415,7 +1415,7

[PATCH 1/4] ignore AMDs HWCR register access to set the FFDIS bit

Linux tries to disable the flush filter on all AMD K8 CPUs. Since KVM does not handle the needed MSR, the injected #GP will panic the Linux kernel. Ignore setting of the HWCR.FFDIS bit in this MSR to let Linux boot with an AMD K8 family guest CPU. Signed-off-by: Andre Przywara andre.przyw

Re: [PATCH 2/2] introduce -cpu host target

Avi Kivity wrote: On 06/23/2009 12:47 AM, Andre Przywara wrote: Should we ignore unhandled MSRs like QEMU or Xen do? Ignoring unhandled msrs is dangerous. If a write has some effect the guest depends on, and we're not emulating that effect, the guest will fail. Similarly if you don't

Re: [PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

Avi Kivity wrote: On 06/24/2009 01:44 PM, Andre Przywara wrote: Signed-off-by: Andre Przywaraandre.przyw...@amd.com --- arch/x86/kvm/x86.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e6e61ee..6ad0f93 100644

Re: [PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

Andre Przywara wrote: Avi Kivity wrote: --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1415,7 +1415,7 @@ static void do_cpuid_ent(struct -0 /* Reserved, XSAVE, OSXSAVE */; +0 /* Reserved, XSAVE, OSXSAVE */ | F(HYPERVISOR); I think this should be handled in qemu, since

[PATCH 1/2 v2] allow hypervisor CPUID bit to be overriden

disable it by using: -cpu qemu64,-hypervisor Fix some whitespace damage on the way. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/helper.c | 23 +++ 1 files changed, 11 insertions(+), 12 deletions(-) diff --git a/target-i386/helper.c b/target-i386

[PATCH 1/2] allow hypervisor CPUID bit to be overriden

. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/helper.c | 25 + 1 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index 8a76abd..529f962 100644 --- a/target-i386/helper.c +++ b/target-i386

[PATCH 2/2] introduce -cpu host target

will propagate the host's CPUID bits to the guest. Problematic bits can still be turned off by using the existing syntax (-cpu host,-skinit) Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/helper.c | 65 + 1 files changed, 59 insertions

[PATCH 1/2] ignore AMDs HWCR register access to set the FFDIS bit

Linux tries to disable the flush filter on all AMD K8 CPUs. Since KVM does not handle the needed MSR, the injected #GP will panic the Linux kernel. Ignore setting of the HWCR.FFDIS bit in this MSR to let Linux boot with an AMD K8 family guest CPU. Signed-off-by: Andre Przywara andre.przyw

[PATCH 2/2] ignore reads from AMDs C1E enabled MSR

If the Linux kernel detects an C1E capable AMD processor (K8 RevF and higher), it will access a certain MSR on every attempt to go to halt. Explicitly handle this read and return 0 to let KVM run a Linux guest with the native AMD host CPU propagated to the guest. Signed-off-by: Andre Przywara

[PATCH 4/6 v2] add syscall emulation

-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86_emulate.c | 82 +++- 1 files changed, 81 insertions(+), 1 deletions(-) Avi, these are the new versions of patch 4-6/6. If you need delta patches, tell me. Thanks, Andre. diff --git a/arch

[PATCH 6/6 v2] add sysexit emulation

...@redhat.com Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86_emulate.c | 72 +++- 1 files changed, 71 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c index fdf75f6..6849868 100644

[PATCH] fix renamed MSR_K8_HWCR name

The definition of MSR_K8_HWCR was removed upstream in favor of MSR_K7_HWCR. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/svm.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index c283201..481010c 100644

Re: [PATCH] add sysenter/syscall emulation for 32bit compat mode

Amit Shah wrote: Hi Andre, On (Tue) Jun 16 2009 [15:25:13], Andre Przywara wrote: sysenter/sysexit are not supported on AMD's 32bit compat mode, whereas syscall is not supported on Intel's 32bit compat mode. To allow cross vendor migration we emulate the missing instructions by setting up

[PATCH 0/6] add sysenter/syscall emulation for 32bit compat mode

, it was completed, debugged, syscall added and made-to-work by Christoph Egger and polished up by Andre Przywara. Please note that sysret does not need to be emulated, because it will be exectued in 64bit mode and returning to 32bit compat mode works on Intel. This has been tested with GETPIDs

[PATCH 1/6] allow emulation of syscalls instructions on #UD

Add the opcodes for syscall, sysenter and sysexit to the list of instructions handled by the undefined opcode handler. Signed-off-by: Christoph Egger christoph.eg...@amd.com Signed-off-by: Amit Shah amit.s...@redhat.com Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86.c

[PATCH 2/6] add missing EFLAGS bit definitions

Signed-off-by: Christoph Egger christoph.eg...@amd.com Signed-off-by: Amit Shah amit.s...@redhat.com Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86_emulate.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86

[PATCH 3/6] prepare for emulation of syscall instructions

Add the flags needed for syscall, sysenter and sysexit to the opcode table. Catch (but for now ignore) the opcodes in the emulation switch/case. Signed-off-by: Andre Przywara andre.przyw...@amd.com Signed-off-by: Amit Shah amit.s...@redhat.com Signed-off-by: Christoph Egger christoph.eg

[PATCH 5/6] add sysenter emulation

-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86_emulate.c | 72 +++- 1 files changed, 71 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c index 89bd53e..2f62aaa 100644 --- a/arch/x86/kvm

[PATCH 4/6] add syscall emulation

-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86_emulate.c | 89 +++- 1 files changed, 88 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c index 328ccba..89bd53e 100644 --- a/arch/x86/kvm

[PATCH 6/6] add sysexit emulation

...@redhat.com Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86_emulate.c | 79 +++- 1 files changed, 78 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c index 2f62aaa..7df05cc 100644

[PATCH] add sysenter/syscall emulation for 32bit compat mode

, it was completed, debugged, syscall added and made-to-work by Christoph Egger and polished up by Andre Przywara. Please note that sysret does not need to be emulated, because it will be exectued in 64bit mode and returning to 32bit compat mode works on Intel. Signed-off-by: Amit Shah amit.s

[PATCH] move performance counter MSR access interception to generic x86 KVM path

is something we perfectly emulate ;-), so don't print out a warning to dmesg in this case. This fixes booting a 64bit Windows guest with an AMD CPUID on an Intel host. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/svm.c | 16 arch/x86/kvm/vmx.c | 12

Re: [PATCH 2/2] add sysenter/syscall emulation for 32bit compat mode

functions. Ok, will do. Thanks for the review! Renewed patch will follow. Regards, Andre. -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http

[PATCH 1/2] use explicit 64bit storage for sysenter values

Since AMD does not support sysenter in 64bit mode, the VMCB fields storing the MSRs are truncated to 32bit upon VMRUN/#VMEXIT. So store the values in a separate 64bit storage to avoid truncation. Signed-off-by: Christoph Egger christoph.eg...@amd.com --- arch/x86/kvm/kvm_svm.h |4

[PATCH 2/2] add sysenter/syscall emulation for 32bit compat mode

by Amit Shah, it was completed, debugged, syscall added and made-to-work by Christoph Egger and polished up by Andre Przywara. Please note that sysret does not need to be emulated, because it will be exectued in 64bit mode and returning to 32bit compat mode works on Intel. Signed-off-by: Amit

[PATCH] allow CPUID vendor override

KVM will always report the vendor ID of the physical CPU it is running on. Allow to override this if explicitly requested on the command line. It will not suffice to name a CPU type (like -cpu phenom), but you have to explicitly set the vendor: -cpu phenom,vendor=AuthenticAMD Signed-off-by: Andre

[PATCH 1/2] Fix cross vendor migration issue with unusable bit

AMDs VMCB does not have an explicit unusable segment descriptor field, so we emulate it by using not present. This has to be setup before the fixups, because this field is used there. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/svm.c |7 +-- 1 files changed, 5

[PATCH] [resend] set accessed bit for VMCB segment selectors

this bit in the AMD path to enable cross vendor migration. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/svm.c | 23 +-- 1 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 22e88a4..dc5d88f 100644

Re: Running KVM on a Laptop

regarding to NPT nor the BIOS needs to handle NPT in a special way. 3. If you're running KVM on your laptop, could you share the information? Does your laptop's BIOS support AMD-V or VT-x? We use hardware virtualization on a MSI MegaBook S271 (TurionX2). Regards, Andre. -- Andre Przywara

Re: Fast/Quiet Boot

] for the QEMU interface side (functions here are prefixed with fw_cfg_). So define a new channel and send your data over. Be sure to consider qemu-devel if you want to send patches. Hope that helps, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49

[PATCH] kvm: set accessed bit for VMCB segment selectors

In the segment descriptor _cache_ the accessed bit is always set (although it can be cleared in the descriptor itself). Since Intel checks for this condition on a VMENTRY, set this bit in the AMD path to enable cross vendor migration. Signed-off-by: Andre Przywara andre.przyw...@amd.com Acked

[PATCH] kvm: always set accessed bit in VMCS segment selectors

one. If someone has an explanation which justifies a move, I am happy to do this. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/vmx.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 9b56d21..d19e39c

Re: [PATCH] qemu: fix configuring kvm probe when using --kerneldir

/x86/include ; then +kvm_cflags=$kvm_cflags -I$kerneldir/arch/x86/include +elif test -d $kerneldir/arch/$cpu/include ; then +kvm_cflags=$kvm_cflags -I$kerneldir/arch/$cpu/include + fi else kvm_cflags= fi -- Andre Przywara AMD-OSRC (Dresden) Tel

[PATCH] set accessed bit for VMCB segment selectors

In the segment descriptor _cache_ the accessed bit is always set (although it can be cleared in the descriptor itself). Since Intel checks for this condition on a VMENTRY, set this bit in the AMD path to enable cross vendor migration. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch

[PATCH] KVM-userspace: allow CPUID vendor override

Hi, currently KVM always propagates the host CPU vendor ID to the guest. This patch allows to override this behavior by explicitly specifying a vendor ID with -cpu qemu64,vendor=KVMKVMKVMKVM. This proved to be useful for cross vendor migration tests. Regards, Andre. Andre Przywara AMD-Operating

Re: [PATCH] CPUID Masking MSRs

almost everything you probably need: http://xenbits.xensource.com/xen-unstable.hg?rev/be20b11656bb Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: Advanced Micro Devices GmbH

[PATCH] kvm-userspace: Fix a compiler warning

The following small patch fixes a compiler warning in KVM's vl.c Signed-off-by: Andre Przywara [EMAIL PROTECTED] --- diff --git a/qemu/vl.c b/qemu/vl.c index 7b58605..b489acd 100644 --- a/qemu/vl.c +++ b/qemu/vl.c @@ -4611,7 +4611,7 @@ static int gethugepagesize(void) { int ret, fd

[PATCH 0/3] v2: KVM-userspace: add NUMA support for guests

, a possible command line looks like: -numa 3,mem:1024M;512M;512M,cpu:0-1;2;3 Please note that you have to quote the semicolons on the shell. The monitor command is left out for now and will be send later. Please apply. Regards, Andre. Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre

[PATCH 1/3] v2: KVM-userspace: introduce -numa command line option

The attached patch parses the command line options given at -numa and passes it on to lower levels (namely qemu-kvm.c) Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European

[PATCH 2/3] v2: KVM-userspace: allocate guest resources from different host nodes

actually faults in). The presence of libnuma will be auto-detected. Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability

[PATCH 3/3] v2: KVM-userspace: generate a SRAT table to describe the guests NUMA topology

. Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company Co. KG, Wilschdorfer Landstr. 101, 01109 Dresden, Germany

Re: [PATCH 0/3] v2: KVM-userspace: add NUMA support for guests

of the first three if needed. Sounds like a plan. I will start with this and hope for some advice on the BOCHS BIOS issue. Thanks for your ideas! Regards, Andre. Andre Przywara wrote: Hi, this patch series introduces multiple NUMA nodes support within KVM guests. This is the second try

Re: [PATCH 0/3] KVM-userspace: add NUMA support for guests

Avi Kivity wrote: Andre Przywara wrote: The user (or better: management application) specifies the host nodes the guest should use: -nodes 2,3 would create a two node guest mapped to node 2 and 3 on the host. These numbers are handed over to libnuma: VCPUs are pinned to the nodes

[PATCH 0/3] KVM-userspace: add NUMA support for guests

SRAT ACPI table Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company Co. KG, Wilschdorfer Landstr. 101, 01109

[PATCH 1/3] KVM-userspace: introduce -nodes command line option

The attached patch parses a list of host nodes given on the command line and passes it on to lower levels (namely qemu-kvm.c) Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy

[PATCH 2/3] KVM-userspace: allocate guest resources from different host nodes

actually faults in). Since libnuma is not that widespread (in default installations), I chose 'enable via configure' by now: --enable-numa will compile the parts in. Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel

[PATCH 3/3] KVM-userspace: generate a SRAT table to describe the guests NUMA topology

-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company Co. KG, Wilschdorfer Landstr. 101, 01109 Dresden, Germany Register Court

[PATCH] x86 CPUID extended family/model

qemu64,family=16,model=4,stepping=2 Attached patch introduces support for specifying those bits on the command line and passing them to the guest. (Patch applies against qemu-svn and kvm-userspace) Signed-off-by: Andre Przywara [EMAIL PROTECTED] Regards, Andre. P.S. I heard of a way to propagate

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