On Wed, Dec 19, 2012 at 10:59:36PM -0200, Marcelo Tosatti wrote:
On Mon, Dec 17, 2012 at 01:30:49PM +0800, Yang Zhang wrote:
From: Yang Zhang yang.z.zh...@intel.com
Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
manually, which is fully taken care of by the hardware
elapsed;
}
Reviewed-by: Marcelo Tosatti mtosa...@redhat.com
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On Wed, Dec 12, 2012 at 12:39:02AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-10:
According to Intel SDM Volume 3 Section 10.8.1 Interrupt Handling with
the Pentium 4 and Intel Xeon Processors and Section 10.8.2 Interrupt
Handling with the P6 Family and Pentium Processors
On Mon, Dec 10, 2012 at 11:44:35AM +0200, Gleb Natapov wrote:
Add test for aad instruction emulation.
Signed-off-by: Gleb Natapov g...@redhat.com
Applied, thanks.
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More
Raghavendra,
Please get this integrate through x86 tree (Ingo CC'ed).
On Mon, Nov 26, 2012 at 05:37:54PM +0530, Raghavendra K T wrote:
From: Peter Zijlstra pet...@infradead.org
In case of undercomitted scenarios, especially in large guests
yield_to overhead is significantly high. when run
On Mon, Dec 10, 2012 at 10:32:39AM -0700, Alex Williamson wrote:
v2: Update 02/10 to not check userspace_addr when slot is removed.
Yoshikawa-san withdrew objection to increase slot_bitmap prior
to his series to remove slot_bitmap.
This series does away with any kind of complicated
On Fri, Dec 14, 2012 at 12:50:09PM +0800, Xiao Guangrong wrote:
program a timer interrupt and #GP?
Could you please explain the detail?
Before the instruction which writes continuously to the pagetable, arm
say lapic timer. #GP on the interrupt handler and test with failure.
On Thu, Dec 13, 2012 at 09:43:23PM -0800, Andy Lutomirski wrote:
On 3.7.0 + irrelevant patches, I get this on boot. I've seen it on
and off on earlier kernels, I think (although I'm not currently
getting it on 3.5).
[ 10.230054] PERCPU: allocation failed, size=304 align=32, alloc
from
On Thu, Dec 13, 2012 at 02:24:18PM +0200, Gleb Natapov wrote:
On Thu, Dec 13, 2012 at 01:11:55PM +0100, Paolo Bonzini wrote:
MOV immediate instruction (opcodes 0xB8-0xBF) may take 64-bit operand.
Some hypervisor implementations assumed the operand is 32-bit. This
should never happen
On Thu, Dec 13, 2012 at 01:11:55PM +0100, Paolo Bonzini wrote:
MOV immediate instruction (opcodes 0xB8-0xBF) may take 64-bit operand.
Some hypervisor implementations assumed the operand is 32-bit. This
should never happen because the instruction has no memory operand, but
(like the existing
On Thu, Dec 13, 2012 at 03:29:21AM +0800, Xiao Guangrong wrote:
On 12/12/2012 09:09 AM, Marcelo Tosatti wrote:
On Mon, Dec 10, 2012 at 05:14:47PM +0800, Xiao Guangrong wrote:
The current reexecute_instruction can not well detect the failed
instruction
emulation. It allows guest to retry
On Thu, Dec 13, 2012 at 04:05:55AM +0800, Xiao Guangrong wrote:
On 12/12/2012 07:36 AM, Marcelo Tosatti wrote:
On Mon, Dec 10, 2012 at 05:11:35PM +0800, Xiao Guangrong wrote:
Changelog:
There are some changes from Marcelo and Gleb's review, thank you all!
- access indirect_shadow_pages
On Thu, Dec 13, 2012 at 03:23:26AM +0800, Xiao Guangrong wrote:
On 12/12/2012 08:57 AM, Marcelo Tosatti wrote:
On Mon, Dec 10, 2012 at 05:13:03PM +0800, Xiao Guangrong wrote:
We have two issues in current code:
- if target gfn is used as its page table, guest will refault then kvm
On Tue, Dec 11, 2012 at 05:11:34PM +0800, Zhang Yanfei wrote:
This removes the sparse warning:
arch/x86/kernel/crash.c:49:32: sparse: incompatible types in comparison
expression (different address spaces)
Reported-by: kbuild test robot fengguang...@intel.com
Signed-off-by: Zhang Yanfei
On Mon, Dec 10, 2012 at 05:13:03PM +0800, Xiao Guangrong wrote:
We have two issues in current code:
- if target gfn is used as its page table, guest will refault then kvm will
use
small page size to map it. We need two #PF to fix its shadow page table
- sometimes, say a exception is
, compiled on ia64, powerpc, and s390.
Thanks,
Alex
Reviewed-by: Marcelo Tosatti mtosa...@redhat.com
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On Tue, Dec 11, 2012 at 11:29:09PM -0200, Marcelo Tosatti wrote:
On Mon, Dec 10, 2012 at 10:32:45AM -0700, Alex Williamson wrote:
The API documentation states:
When changing an existing slot, it may be moved in the guest
physical memory space, or its flags may be modified
On Tue, Dec 11, 2012 at 03:14:13PM +0200, Gleb Natapov wrote:
VMX without unrestricted mode cannot virtualize real mode, so if
emulate_invalid_guest_state=0 kvm uses vm86 mode to approximate
it. Sometimes, when guest moves from protected mode to real mode, it
leaves segment descriptors in a
On Mon, Dec 10, 2012 at 05:12:20PM +0800, Xiao Guangrong wrote:
Then, no mmu specified code exists in the common function and drop two
parameters in set_spte
Signed-off-by: Xiao Guangrong xiaoguangr...@linux.vnet.ibm.com
---
arch/x86/kvm/mmu.c | 47
On Mon, Dec 10, 2012 at 05:14:47PM +0800, Xiao Guangrong wrote:
The current reexecute_instruction can not well detect the failed instruction
emulation. It allows guest to retry all the instructions except it accesses
on error pfn
For example, some cases are nested-write-protect - if the page
On Mon, Dec 10, 2012 at 05:11:35PM +0800, Xiao Guangrong wrote:
Changelog:
There are some changes from Marcelo and Gleb's review, thank you all!
- access indirect_shadow_pages in the protection of mmu-lock
- fix the issue when unhandleable instruction access on large page
- add a new test
On Mon, Dec 10, 2012 at 10:32:45AM -0700, Alex Williamson wrote:
The API documentation states:
When changing an existing slot, it may be moved in the guest
physical memory space, or its flags may be modified.
An existing slot requires a non-zero npages (memory_size). The only
On Thu, Dec 06, 2012 at 02:44:59PM -0700, Alex Williamson wrote:
Typo for the next pointer means we're walking random data here.
Signed-off-by: Alex Williamson alex.william...@redhat.com
Cc: sta...@vger.kernel.org [3.7]
---
Not sure if this will make 3.7, so preemptively adding the stable
On Fri, Dec 07, 2012 at 01:40:56PM +0800, Zhang Yanfei wrote:
This removes the sparse warning:
arch/x86/kernel/crash.c:49:32: sparse: incompatible types in comparison
expression (different address spaces)
Reported-by: kbuild test robot fengguang...@intel.com
Signed-off-by: Zhang Yanfei
On Thu, Dec 06, 2012 at 01:40:49AM +0100, Alexander Graf wrote:
Hi Marcelo / Gleb,
This is my current patch queue for ppc. Please pull.
Major changes this time around include:
- Book3S PR: Multiple fixes for POWER7 hosts
- Book3S HV: Prepare for full state exposure (live migration)
On Thu, Dec 06, 2012 at 01:40:49AM +0100, Alexander Graf wrote:
Hi Marcelo / Gleb,
This is my current patch queue for ppc. Please pull.
Major changes this time around include:
- Book3S PR: Multiple fixes for POWER7 hosts
- Book3S HV: Prepare for full state exposure (live migration)
On Thu, Dec 06, 2012 at 12:29:02PM +0530, Raghavendra K T wrote:
On 12/04/2012 01:26 AM, Marcelo Tosatti wrote:
On Wed, Nov 28, 2012 at 10:40:56AM +0530, Raghavendra K T wrote:
On 11/28/2012 06:42 AM, Marcelo Tosatti wrote:
Don't understand the reasoning behind why 3 is a good choice
On Thu, Dec 06, 2012 at 08:36:52AM +0200, Gleb Natapov wrote:
On Thu, Dec 06, 2012 at 05:02:15AM +, Zhang, Yang Z wrote:
Zhang, Yang Z wrote on 2012-12-06:
Marcelo Tosatti wrote on 2012-12-06:
On Mon, Dec 03, 2012 at 03:01:03PM +0800, Yang Zhang wrote:
Virtual interrupt delivery
-by: Marcelo Tosatti mtosa...@redhat.com
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 39171cb..6fec09c 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -43,7 +43,7 @@
#define OpCL 9ull /* CL register (for shifts) */
#define OpImmByte 10ull
On Wed, Dec 05, 2012 at 08:51:37PM -0700, Alex Williamson wrote:
id_to_memslot seems like a good place to catch all the users since
that's the only way to get a slot from a slot id after the array is
sorted. We need to check both is the slot in bounds (EINVAL), but also
is it
On Thu, Dec 06, 2012 at 09:58:48PM -0200, Marcelo Tosatti wrote:
On Wed, Dec 05, 2012 at 08:51:37PM -0700, Alex Williamson wrote:
id_to_memslot seems like a good place to catch all the users since
that's the only way to get a slot from a slot id after the array is
sorted. We need
On Tue, Dec 04, 2012 at 07:17:11AM +0800, Xiao Guangrong wrote:
There are two cases we need to adjust page size in set_spte:
1): the one is other vcpu creates new sp in the window between mapping_level()
and acquiring mmu-lock.
2): the another case is the new sp is created by itself
On Mon, Dec 03, 2012 at 04:39:30PM -0700, Alex Williamson wrote:
In order to make the memslots array grow on demand, move the private
slots to the lower indexes of the array. The private slots are
assumed likely to be in use, so if we didn't do this we'd end up
allocating the full memslots
On Mon, Dec 03, 2012 at 04:39:36PM -0700, Alex Williamson wrote:
struct kvm_memory_slot is currently 52 bytes (LP64), not counting the
arch data. On x86 this means the memslot array to support a tiny 32+3
entries (user+private) is over 2k. We'd like to support more slots
so that we can
On Mon, Dec 03, 2012 at 04:39:24PM -0700, Alex Williamson wrote:
This allows us to resize this structure and therefore the number of
memslots as part of the RCU update.
Why is this necessary? struct memslots is updated, message above
conflicts with that.
If there is a reason, id_to_index
On Mon, Dec 03, 2012 at 04:39:05PM -0700, Alex Williamson wrote:
Memory slots are currently a fixed resource with a relatively small
limit. When using PCI device assignment in a qemu guest it's fairly
easy to exhaust the number of available slots. I posted patches
exploring growing the
On Mon, Dec 03, 2012 at 03:01:03PM +0800, Yang Zhang wrote:
Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
manually, which is fully taken care of by the hardware. This needs
some special awareness into existing interrupr injection path:
- for pending interrupt, instead of
On Wed, Dec 05, 2012 at 01:14:38PM +0200, Gleb Natapov wrote:
On Wed, Dec 05, 2012 at 03:43:41AM +, Zhang, Yang Z wrote:
@@ -5657,12 +5673,20 @@ static int vcpu_enter_guest(struct kvm_vcpu
*vcpu)
}
if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
On Wed, Dec 05, 2012 at 03:17:13AM +, Zhang, Yang Z wrote:
Marcelo Tosatti wrote on 2012-12-05:
On Mon, Dec 03, 2012 at 03:01:02PM +0800, Yang Zhang wrote:
- APIC read doesn't cause VM-Exit
- APIC write becomes trap-like
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
Signed-off
On Wed, Dec 05, 2012 at 04:02:53PM -0700, Alex Williamson wrote:
On Wed, 2012-12-05 at 19:26 -0200, Marcelo Tosatti wrote:
On Mon, Dec 03, 2012 at 04:39:36PM -0700, Alex Williamson wrote:
struct kvm_memory_slot is currently 52 bytes (LP64), not counting the
arch data. On x86 this means
On Mon, Dec 03, 2012 at 03:01:02PM +0800, Yang Zhang wrote:
- APIC read doesn't cause VM-Exit
- APIC write becomes trap-like
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
Signed-off-by: Kevin Tian kevin.t...@intel.com
---
arch/x86/include/asm/vmx.h |2 ++
arch/x86/kvm/lapic.c
On Mon, Dec 03, 2012 at 03:01:03PM +0800, Yang Zhang wrote:
Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
manually, which is fully taken care of by the hardware. This needs
some special awareness into existing interrupr injection path:
- for pending interrupt, instead of
On Mon, Dec 03, 2012 at 04:33:01PM +0800, Xiao Guangrong wrote:
Hi Marcelo,
Thanks for your patience. I was reading your reply over and over again, i
would
like to argue it more :).
Please see below.
On 11/29/2012 08:21 AM, Marcelo Tosatti wrote:
https://lkml.org/lkml/2012/11/17
On Wed, Nov 28, 2012 at 10:40:56AM +0530, Raghavendra K T wrote:
On 11/28/2012 06:42 AM, Marcelo Tosatti wrote:
Don't understand the reasoning behind why 3 is a good choice.
Here is where I came from. (explaining from scratch for
completeness, forgive me :))
In moderate overcommits, we
On Mon, Dec 03, 2012 at 12:36:33PM +0400, Glauber Costa wrote:
On 11/30/2012 09:55 PM, Pavel Emelyanov wrote:
Hello,
This is an attempt to implement support for memory snapshot for the the
checkpoint-restore project (http://criu.org).
To create a dump of an application(s) we save
On Thu, Nov 29, 2012 at 12:41:19PM -0800, Will Auld wrote:
I have re-based this patch set version (V6) to kvm.git's queue branch.
Will Auld (2):
Add code to track call origin for msr assignment.
Enabling IA32_TSC_ADJUST for KVM guest VM support
Applied, thanks.
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On Thu, Nov 29, 2012 at 02:07:59PM -0700, Alex Williamson wrote:
Prior to memory slot sorting this loop compared all of the user memory
slots for overlap with new entries. With memory slot sorting, we're
just checking some number of entries in the array that may or may not
be user slots.
On Wed, Nov 28, 2012 at 08:54:14PM +0800, Xiao Guangrong wrote:
vmcs-cpu indicates whether it exists on the target cpu, -1 means the vmcs
does not exist on any vcpu
If vcpu load vmcs with vmcs.cpu = -1, it can be directly added to cpu's percpu
list. The list can be corrupted if the cpu
On Mon, Nov 26, 2012 at 09:32:18PM -0800, Will Auld wrote:
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the
On Fri, Nov 30, 2012 at 10:36:43AM +0900, Yoshihiro YUNOMAE wrote:
Hi Marcelo,
Can you please write a succint but complete description of the method
so it can be verified?
Sure.
- Prerequisite
1. the host TSC is synchronized and stable.
2. kvm_write_tsc_offset events include previous
On Thu, Nov 29, 2012 at 07:21:28PM +, Auld, Will wrote:
Marcelo,
The behavior on reset is to return the TSC_AJUST msr value to 0x0. I am
currently initializing this emulated msr in kvm_arch_vcpu_init().
Will,
Reset is handled by QEMU. kvm_arch_vcpu_init is only called during vcpu
On Tue, Nov 27, 2012 at 07:53:47PM +0900, Yoshihiro YUNOMAE wrote:
Hi Marcelo,
(2012/11/27 8:16), Marcelo Tosatti wrote:
On Mon, Nov 26, 2012 at 08:05:10PM +0900, Yoshihiro YUNOMAE wrote:
500h. event tsc_write tsc_offset=-3000
Then a guest trace containing events with a TSC timestamp
On Wed, Nov 28, 2012 at 01:27:38PM +0800, Xiao Guangrong wrote:
On 11/18/2012 11:00 AM, Marcelo Tosatti wrote:
map gfn 4? See corrected step 7 above.
Ah, this is a real bug, and unfortunately, it exists in current
code. I will make a separate patchset to fix it. Thank you, Marcelo
On Wed, Nov 28, 2012 at 10:55:26PM +0800, Xiao Guangrong wrote:
On 11/28/2012 10:01 PM, Gleb Natapov wrote:
On Wed, Nov 28, 2012 at 11:15:13AM +0800, Xiao Guangrong wrote:
On 11/28/2012 07:32 AM, Marcelo Tosatti wrote:
On Tue, Nov 27, 2012 at 11:13:11AM +0800, Xiao Guangrong wrote
On Wed, Nov 28, 2012 at 10:59:35PM +0800, Xiao Guangrong wrote:
On 11/28/2012 10:12 PM, Gleb Natapov wrote:
On Tue, Nov 27, 2012 at 11:30:24AM +0800, Xiao Guangrong wrote:
On 11/27/2012 06:41 AM, Marcelo Tosatti wrote:
-return false;
+again:
+page_fault_count
On Wed, Nov 28, 2012 at 01:32:09PM -0800, Will Auld wrote:
Added x86/tsc_adjust.c and updated x86/vmexit.c to include timing tests
for reading and writing the emulated IA32_TSC_ADJUST msr.
Signed-off-by: Will Auld will.a...@intel.com
---
config-x86-common.mak | 5 -
x86/tsc_adjust.c
On Thu, Nov 29, 2012 at 06:40:51AM +0800, Xiao Guangrong wrote:
On 11/29/2012 05:57 AM, Marcelo Tosatti wrote:
On Wed, Nov 28, 2012 at 10:59:35PM +0800, Xiao Guangrong wrote:
On 11/28/2012 10:12 PM, Gleb Natapov wrote:
On Tue, Nov 27, 2012 at 11:30:24AM +0800, Xiao Guangrong wrote:
On 11
On Wed, Nov 28, 2012 at 08:53:15PM +0800, Xiao Guangrong wrote:
In loaded_vmcs_clear, loaded_vmcs-cpu is the fist parameter passed to
smp_call_function_single, if the target cpu is downing (doing cpu hot remove),
loaded_vmcs-cpu can become -1 then -1 is passed to smp_call_function_single
It
On Wed, Nov 28, 2012 at 03:19:08PM +0200, Gleb Natapov wrote:
As Frederic pointed idle_cpu() may return false even if async fault
happened in the idle task if wake up is pending. In this case the code
will try to put idle task to sleep. Fix this by using is_idle_task() to
check for idle task.
On Wed, Nov 28, 2012 at 08:54:14PM +0800, Xiao Guangrong wrote:
vmcs-cpu indicates whether it exists on the target cpu, -1 means the vmcs
does not exist on any vcpu
If vcpu load vmcs with vmcs.cpu = -1, it can be directly added to cpu's percpu
list. The list can be corrupted if the cpu
On Thu, Nov 29, 2012 at 07:16:50AM +0800, Xiao Guangrong wrote:
On 11/29/2012 06:40 AM, Xiao Guangrong wrote:
On 11/29/2012 05:57 AM, Marcelo Tosatti wrote:
On Wed, Nov 28, 2012 at 10:59:35PM +0800, Xiao Guangrong wrote:
On 11/28/2012 10:12 PM, Gleb Natapov wrote:
On Tue, Nov 27, 2012
On Mon, Nov 26, 2012 at 02:36:24PM -0600, Michael Wolf wrote:
In the case of where you have a system that is running in a
capped or overcommitted environment the user may see steal time
being reported in accounting tools such as top or vmstat.
The definition of stolen time is 'time during
On Tue, Nov 27, 2012 at 11:30:24AM +0800, Xiao Guangrong wrote:
On 11/27/2012 06:41 AM, Marcelo Tosatti wrote:
- return false;
+again:
+ page_fault_count = ACCESS_ONCE(vcpu-kvm-arch.page_fault_count);
+
+ /*
+ * if emulation was due to access to shadowed page table
On Tue, Nov 27, 2012 at 11:13:11AM +0800, Xiao Guangrong wrote:
+static bool reexecute_instruction(struct kvm_vcpu *vcpu, unsigned long
cr2)
{
- gpa_t gpa;
+ gpa_t gpa = cr2;
pfn_t pfn;
- if (tdp_enabled)
+ if (!ACCESS_ONCE(vcpu-kvm-arch.indirect_shadow_pages))
On Thu, Nov 22, 2012 at 12:51:59PM +0800, Dongxiao Xu wrote:
The launch state is not a member in the VMCS area, use a separate
variable (list) to store it instead.
Signed-off-by: Dongxiao Xu dongxiao...@intel.com
1. What is the problem with keeping launched state in the VMCS?
Assuming there
Will,
1. Please check CPUID before using ADJUST_TSC MSR, exit test successfully
if CPUID bit disabled.
2. Please test the implementation of ADJUST_TSC MSR (functional test).
vmexit.flat test can be used for performance of MSR emulation.
Example
tsc1 = rdtsc();
On Tue, Nov 27, 2012 at 09:24:42PM -0200, Marcelo Tosatti wrote:
On Mon, Nov 26, 2012 at 02:36:24PM -0600, Michael Wolf wrote:
In the case of where you have a system that is running in a
capped or overcommitted environment the user may see steal time
being reported in accounting tools
Hi Will,
On Tue, Nov 27, 2012 at 11:09:00AM -0800, Will Auld wrote:
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to a guest
vcpu specific location to store the value of the emulated MSR while adding
the
Don't understand the reasoning behind why 3 is a good choice.
On Mon, Nov 26, 2012 at 05:38:04PM +0530, Raghavendra K T wrote:
From: Raghavendra K T raghavendra...@linux.vnet.ibm.com
yield_to returns -ESRCH, When source and target of yield_to
run queue length is one. When we see three
On Tue, Nov 27, 2012 at 10:56:50AM +0800, Fengguang Wu wrote:
Hi Marcelo,
FYI, kernel build failed on
tree: git://git.kernel.org/pub/scm/virt/kvm/kvm.git queue
head: fc1ddea318fa2c1ac3d496d8653ca4bc9b66e679
commit: 438d76a60e7be59a558f8712a47565fa8258d17d [23/25] KVM: x86: add
On Tue, Nov 20, 2012 at 07:59:53AM +0800, Xiao Guangrong wrote:
The current reexecute_instruction can not well detect the failed instruction
emulation. It allows guest to retry all the instructions except it accesses
on error pfn.
For example, some cases are nested-write-protect - if the
On Tue, Nov 20, 2012 at 07:59:10AM +0800, Xiao Guangrong wrote:
Currently, reexecute_instruction refused to retry all instructions. If
nested npt is used, the emulation may be caused by shadow page, it can
be fixed by dropping the shadow page
Signed-off-by: Xiao Guangrong
On Mon, Nov 26, 2012 at 08:05:10PM +0900, Yoshihiro YUNOMAE wrote:
500h. event tsc_write tsc_offset=-3000
Then a guest trace containing events with a TSC timestamp.
Which tsc_offset to use?
(that is the problem, which unless i am mistaken can only be solved
easily if the guest can convert
On Tue, Nov 20, 2012 at 02:09:46PM +, Pandarathil, Vijaymohan R wrote:
-Original Message-
From: Stefan Hajnoczi [mailto:stefa...@gmail.com]
Sent: Tuesday, November 20, 2012 5:41 AM
To: Pandarathil, Vijaymohan R
Cc: kvm@vger.kernel.org; linux-...@vger.kernel.org;
On Mon, Nov 26, 2012 at 02:48:50PM -0800, H. Peter Anvin wrote:
On 11/25/2012 11:22 PM, Paolo Bonzini wrote:
Il 21/11/2012 23:41, H. Peter Anvin ha scritto:
From: H. Peter Anvin h...@linux.intel.com
In __emulate_1op_rax_rdx, we use +a and +d which are input/output
constraints, and
On Mon, Nov 26, 2012 at 03:49:36PM -0800, H. Peter Anvin wrote:
On 11/26/2012 03:48 PM, Marcelo Tosatti wrote:
Gleb, Marcelo: are you going to apply this or would you prefer I took it
in x86/urgent?
-hpa
Feel free to merge it through x86/urgent.
I presume that's an Acked
The following changes since commit 1ccbc2851282564308f790753d7158487b6af8e2:
qemu-sockets: Fix parsing of the inet option 'to'. (2012-11-21 12:07:59 +0400)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/qemu-kvm.git uq/master
Bruce Rogers (1):
Legacy
From: Bruce Rogers brog...@suse.com
The options no-kvm, no-kvm-pit, no-kvm-pit-reinjection, and no-kvm-irqchip
should be marked as having no argument.
Signed-off-by: Bruce Rogers brog...@suse.com
Reviewed-by: Jan Kiszka jan.kis...@siemens.com
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
On Thu, Nov 22, 2012 at 02:21:20PM +0900, Yoshihiro YUNOMAE wrote:
Hi Marcelo,
(2012/11/21 7:51), Marcelo Tosatti wrote:
On Tue, Nov 20, 2012 at 07:36:33PM +0900, Yoshihiro YUNOMAE wrote:
Hi Marcelo,
Sorry for the late reply.
(2012/11/17 4:15), Marcelo Tosatti wrote:
On Wed, Nov 14
On Wed, Nov 21, 2012 at 11:27:19PM +0800, Zhang Yanfei wrote:
The notifier will be registered in vmclear_notifier_list when loading
kvm-intel module. And the bitmap indicates whether we should do
VMCLEAR operation in kdump. The bits in the bitmap are set/unset
according to different
On Tue, Nov 20, 2012 at 07:57:48AM +0800, Xiao Guangrong wrote:
The current reexecute_instruction can not well detect the failed instruction
emulation. It allows guest to retry all the instructions except it accesses
on error pfn.
For example, these cases can not be detected:
- for tdp used
On Tue, Nov 20, 2012 at 06:09:48PM +0800, Hu Tao wrote:
Hi Marcelo,
On Tue, Nov 13, 2012 at 12:19:08AM -0200, Marcelo Tosatti wrote:
On Fri, Nov 09, 2012 at 03:17:39PM -0500, Sasha Levin wrote:
On Mon, Nov 5, 2012 at 8:58 PM, Hu Tao hu...@cn.fujitsu.com wrote:
But in the case of panic
On Wed, Nov 07, 2012 at 10:01:11AM +0800, Xudong Hao wrote:
Romove fpu lazy restore logic, using eager restore totally.
v5 changes from v4:
- remove lazy fpu restore totally, fpu eager restore does not have performance
regression and simple the code.
v4 changes from v3:
- Wrap up some
On Mon, Nov 05, 2012 at 08:12:07PM +0800, Xiao Guangrong wrote:
Then, no mmu specified code exists in the common function and drop two
parameters in set_spte
Signed-off-by: Xiao Guangrong xiaoguangr...@linux.vnet.ibm.com
arch/x86/kvm/mmu.c | 42
On Tue, Nov 13, 2012 at 04:39:44PM +0800, Xiao Guangrong wrote:
On 11/13/2012 07:12 AM, Marcelo Tosatti wrote:
On Mon, Nov 05, 2012 at 08:10:08PM +0800, Xiao Guangrong wrote:
In order to detecting spte remapping, we can simply check whether the
spte has already been pointing to the pfn even
On Mon, Nov 05, 2012 at 08:11:03PM +0800, Xiao Guangrong wrote:
It is more cleaner if we can update pte_access fist then set spte according
to pte_access, also introduce gfn_need_write_protect to check whether the
gfn need to be write-protected
Signed-off-by: Xiao Guangrong
On Tue, Nov 20, 2012 at 07:36:33PM +0900, Yoshihiro YUNOMAE wrote:
Hi Marcelo,
Sorry for the late reply.
(2012/11/17 4:15), Marcelo Tosatti wrote:
On Wed, Nov 14, 2012 at 05:26:10PM +0900, Yoshihiro YUNOMAE wrote:
Thank you for commenting on my patch set.
(2012/11/14 11:31), Steven
On Wed, Nov 21, 2012 at 07:23:26AM +0800, Xiao Guangrong wrote:
On 11/21/2012 06:18 AM, Marcelo Tosatti wrote:
-child = page_header(pte PT64_BASE_ADDR_MASK);
-drop_parent_pte(child, sptep);
-kvm_flush_remote_tlbs
Originally from Jeremy Fitzhardinge.
pvclock_get_time_values, which contains the memory barriers
will be removed by next patch.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall/arch/x86/kernel/pvclock.c
Improve performance of time system calls when using Linux pvclock,
by reading time info from fixmap visible copy of pvclock data.
Originally from Jeremy Fitzhardinge.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall/arch/x86/vdso/vclock_gettime.c
Acked-by: Glauber Costa glom...@parallels.com
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall/arch/x86/kernel/pvclock.c
===
--- vsyscall.orig/arch/x86/kernel/pvclock.c
+++ vsyscall/arch/x86/kernel/pvclock.c
Allow the caller to pass host tsc value to kvm_x86_ops-read_l1_tsc().
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall/arch/x86/include/asm/kvm_host.h
===
--- vsyscall.orig/arch/x86/include/asm/kvm_host.h
Otherwise its possible for an unrelated KVM_REQ_UPDATE_CLOCK (such as due to CPU
migration) to clear the bit.
Noticed by Paolo Bonzini.
Reviewed-by: Gleb Natapov g...@redhat.com
Reviewed-by: Glauber Costa glom...@parallels.com
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall
TSC must be matched for the above to guarantee monotonicity.
Allow master clock usage only if guest TSCs are synchronized.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall/arch/x86/include/asm/kvm_host.h
Originally from Jeremy Fitzhardinge.
So code can be reused.
Acked-by: Glauber Costa glom...@parallels.com
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall/arch/x86/kernel/pvclock.c
===
--- vsyscall.orig/arch/x86
As noted by Gleb, not advertising SSE2 support implies
no RDTSC barriers.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall/arch/x86/include/asm/pvclock.h
===
--- vsyscall.orig/arch/x86/include/asm/pvclock.h
Originally from Jeremy Fitzhardinge.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall/include/linux/sched.h
===
--- vsyscall.orig/include/linux/sched.h
+++ vsyscall/include/linux/sched.h
@@ -107,6 +107,14 @@ extern
TSC initialization will soon make use of online_vcpus.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall/arch/ia64/kvm/kvm-ia64.c
===
--- vsyscall.orig/arch/ia64/kvm/kvm-ia64.c
+++ vsyscall/arch/ia64/kvm/kvm-ia64.c
Originally from Jeremy Fitzhardinge.
Introduce generic, non hypervisor specific, pvclock initialization
routines.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall/arch/x86/kernel/pvclock.c
===
--- vsyscall.orig
Register a notifier for clocksource change event. In case
the host switches to clock other than TSC, disable master
clock usage.
Signed-off-by: Marcelo Tosatti mtosa...@redhat.com
Index: vsyscall/arch/x86/kvm/x86.c
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