-devel; Gleb; Andreas Farber; kvm@vger.kernel.org; Dugger,
Donald D; Liu, Jinsong; Zhang, Xiantao; a...@redhat.com
Subject: Re: [PATCH V5] target-i386: Enabling IA32_TSC_ADJUST for QEMU
KVM guest VMs
On Mon, Nov 26, 2012 at 09:32:18PM -0800, Will Auld wrote:
CPUID.7.0.EBX[1]=1 indicates
On Wed, Feb 06, 2013 at 10:22:32PM +, Auld, Will wrote:
Marcelo, Hi,
I have been watching for this patch in the upstream but have not seen it yet.
What version of QEMU should it be in?
Thanks,
Will
Will, its in the GIT tree:
Am 27.11.2012 06:32, schrieb Will Auld:
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the IA32_TSC_ADJUST value
On Mon, Nov 26, 2012 at 09:32:18PM -0800, Will Auld wrote:
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the
: [PATCH V5] target-i386: Enabling IA32_TSC_ADJUST for QEMU
KVM guest VMs
On Mon, Nov 26, 2012 at 09:32:18PM -0800, Will Auld wrote:
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to
the
hypervisor vcpu
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the IA32_TSC_ADJUST value will be included in all reads to
the TSC MSR
