On Thu, Jul 02, 2020 at 11:01:31AM +0800, Jingyi Wang wrote:
> Besides using separate running times parameter, we add time limit
> for loop_test to make sure each test should be done in a certain
> time(5 sec here).
>
> Signed-off-by: Jingyi Wang
> ---
> arm/micro-bench.c | 17 +++--
On Thu, Jul 02, 2020 at 11:01:32AM +0800, Jingyi Wang wrote:
> Trigger PPIs by setting up a 10msec timer and test the latency.
>
> Signed-off-by: Jingyi Wang
> ---
> arm/micro-bench.c | 56 ++-
> 1 file changed, 55 insertions(+), 1 deletion(-)
>
>
On Thu, Jul 02, 2020 at 11:01:30AM +0800, Jingyi Wang wrote:
> For some test in micro-bench can be time consuming, we add a
> micro-bench test parameter to allow each individual test to specify
> its running times.
>
> Signed-off-by: Jingyi Wang
> ---
> arm/micro-bench.c | 25
Hi Jingyi,
This patch has quite a long summary. How about instead of
arm64: microbench: Use the funcions for ipi test as the general functions for
gic(ipi/lpi/timer) test
we use
arm64: microbench: Generalize ipi test names
and then in the commit message, instead of
The following
Trigger PPIs by setting up a 10msec timer and test the latency.
Signed-off-by: Jingyi Wang
---
arm/micro-bench.c | 56 ++-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/arm/micro-bench.c b/arm/micro-bench.c
index 4c962b7..6822084
The following patches will use that.
Signed-off-by: Jingyi Wang
---
arm/micro-bench.c | 39 ++-
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/arm/micro-bench.c b/arm/micro-bench.c
index 794dfac..fc4d356 100644
--- a/arm/micro-bench.c
+++
Besides using separate running times parameter, we add time limit
for loop_test to make sure each test should be done in a certain
time(5 sec here).
Signed-off-by: Jingyi Wang
---
arm/micro-bench.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git
Triggers LPIs through the INT command and test the latency.
Mostly inherited form commit 0ef02cd6cbaa(arm/arm64: ITS: INT
functional tests).
Signed-off-by: Jingyi Wang
---
arm/micro-bench.c | 44
1 file changed, 44 insertions(+)
diff --git
If ipi_exec() fails because of timeout, we shouldn't increase
the number of ipi received.
Signed-off-by: Jingyi Wang
---
arm/micro-bench.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arm/micro-bench.c b/arm/micro-bench.c
index 4612f41..794dfac 100644
---
If gicv4.1(sgi hardware injection) supported, we test ipi injection
via hw/sw way separately.
Signed-off-by: Jingyi Wang
---
arm/micro-bench.c| 45 +++-
lib/arm/asm/gic-v3.h | 3 +++
lib/arm/asm/gic.h| 1 +
3 files changed, 44 insertions(+), 5
With the development of arm gic architecture, we think it will be useful
to add some performance test in kut to measure the cost of interrupts.
In this series, we add GICv4.1 support for ipi latency test and
implement LPI/vtimer latency test.
This series of patches has been tested on GICv4.1
Add the MIDR part number info for the Arm Cortex-A77.
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Rob Herring
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index
On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device load
and a store exclusive or PAR_EL1 read can cause a deadlock.
The workaround requires a DMB SY before and after a PAR_EL1 register read
and the disabling of KVM. KVM must be disabled to prevent the problematic
sequence in
If guests don't have certain CPU erratum work-arounds implemented, then
there is a possibility a guest can deadlock the system. IOW, only trusted
guests should be used on systems with the erratum.
This is the case for Cortex-A57 erratum 832075.
Cc: Marc Zyngier
Cc: James Morse
Cc: Julien
This series implements the work-around for Cortex-A77 erratum 1508412.
KVM guests which don't implement the work-around can still deadlock the
system. This is also the case with the existing Cortex-A57 erratum 832075,
so we add a warning message if an erratum can cause deadlock.
Rob
v1:
On 2020-07-01 15:20, Suzuki K Poulose wrote:
When the host doesn't support 32bit guests, the kvmtool fails
without a proper message on what is wrong. i.e,
$ lkvm run -c 1 Image --aarch32
# lkvm run -k Image -m 256 -c 1 --name guest-105618
Fatal: Unable to initialise vcpu
Given that there
On 29/06/20 18:25, Marc Zyngier wrote:
> Hi Paolo,
>
> Here's another pull request for a handful of KVM/arm64 fixes. Nothing
> absolutely critical (see the tag for the gory details), but I'd rather
> get these merged as soon as possible.
>
> Please pull,
>
> M.
>
> The following changes
When the host doesn't support 32bit guests, the kvmtool fails
without a proper message on what is wrong. i.e,
$ lkvm run -c 1 Image --aarch32
# lkvm run -k Image -m 256 -c 1 --name guest-105618
Fatal: Unable to initialise vcpu
Given that there is no other easy way to check if the host
Hi guys,
On 30/06/2020 09:36, Will Deacon wrote:
> On Tue, Jun 30, 2020 at 09:15:15AM +0100, Marc Zyngier wrote:
>> On 2020-06-29 22:33, Rob Herring wrote:
>>> On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device
>>> load
>>> and a store exclusive or PAR_EL1 read can cause a
Hi,
On 16/06/2020 10:35, Keqian Zhu wrote:
kvm_set_pte is called to replace a target PTE with a desired one.
We always do this without changing the desired one, but if dirty
status set by hardware is coverred, let caller know it.
Signed-off-by: Keqian Zhu
---
arch/arm64/kvm/mmu.c | 36
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