On Wed, Feb 21, 2018 at 05:59:37PM +, Marc Zyngier wrote:
> On Thu, 15 Feb 2018 21:03:23 +,
> Christoffer Dall wrote:
> >
> > As we are about to be more lazy with some of the trap configuration
> > register read/writes for VHE systems, move the logic that is curr
On Wed, Feb 21, 2018 at 05:52:41PM +, Marc Zyngier wrote:
> On 21/02/18 17:39, Andrew Jones wrote:
> > On Thu, Feb 15, 2018 at 10:03:02PM +0100, Christoffer Dall wrote:
> >> The debug save/restore functions can be improved by using the has_vhe()
> >> static key
On Wed, Feb 21, 2018 at 03:33:47PM +, Marc Zyngier wrote:
> On Thu, 15 Feb 2018 21:03:20 +,
> Christoffer Dall wrote:
> >
> > Some system registers do not affect the host kernel's execution and can
> > therefore be loaded when we are about to run a VCPU and
cgi?id=84129
Fixes: 33280b4cd1dc ("ARM: KVM: Add banked registers save/restore")
Cc: sta...@vger.kernel.org
Signed-off-by: Arnd Bergmann
Signed-off-by: Christoffer Dall
---
arch/arm/kvm/hyp/Makefile| 5 +
arch/arm/kvm/hyp/banked-sr.c | 4
2 files changed, 9 inserti
: Marc Zyngier
Cc: # v4.12+
Fixes: d9e139778376 ("KVM: arm/arm64: Support arch timers with a userspace gic")
Signed-off-by: Christoffer Dall
---
virt/kvm/arm/arch_timer.c | 116 +-
1 file changed, 64 insertions(+), 52 deletions(-)
diff --git
gcc-8 (2018-02-15 20:58:36 +0100)
Thanks,
-Christoffer
Arnd Bergmann (1):
ARM: kvm: fix building with gcc-8
Christoffer Dall (1):
KVM: arm/arm64: Fix arch timers with userspace irqchips
arch/arm/kvm/hyp/Makefile| 5 ++
arch/arm/kvm/hyp/banked-sr.c | 4 ++
virt/kvm/arm/arch_timer.c
On Fri, Feb 23, 2018 at 02:44:30PM +, Julien Grall wrote:
> Hi Christoffer,
>
> On 15/02/18 21:03, Christoffer Dall wrote:
> >There is really no need to store the vgic_elrsr on the VGIC data
> >structures as the only need we have for the elrsr is to figure out if an
>
On Fri, Feb 23, 2018 at 02:30:54PM +, Julien Grall wrote:
> Hi Christoffer,
>
> On 15/02/18 21:03, Christoffer Dall wrote:
> >@@ -85,37 +123,14 @@ static void __hyp_text __activate_traps(struct kvm_vcpu
> >*vcpu)
> > {
> > u64 hcr = vcpu->arch.hcr_el2
set_thread_flag(TIF_FOREIGN_FPSTATE);
> + fpsimd_bind_state_to_cpu(&vcpu->arch.ctxt.fpsimd_state);
> +
> + /*
> + * Protect ourselves against a softirq splatting the
> + * FPSIMD state on
On Fri, Feb 16, 2018 at 06:39:30PM +, Dave Martin wrote:
> Oops, forgot to post this patch that goes before patch 1 in the series.
>
> --8<--
>
> Expose an interface for associating an FPSIMD context with a CPU and
> checking the association, for use by KVM.
>
> Signed-off-by: Dave Martin
>
On Thu, Feb 22, 2018 at 06:31:08PM +, Julien Grall wrote:
>
>
> On 22/02/18 18:30, Julien Grall wrote:
> >Hi Christoffer,
> >
> >On 15/02/18 21:03, Christoffer Dall wrote:
> >>Some system registers do not affect the host kernel's execution and can
>
On Thu, Feb 22, 2018 at 06:30:11PM +, Julien Grall wrote:
> Hi Christoffer,
>
> On 15/02/18 21:03, Christoffer Dall wrote:
> >Some system registers do not affect the host kernel's execution and can
> >therefore be loaded when we are about to run a VCPU and we don
On Thu, Feb 22, 2018 at 05:21:20PM +, Marc Zyngier wrote:
> On 22/02/18 16:02, Christoffer Dall wrote:
> > On Thu, Feb 22, 2018 at 03:01:17PM +, Marc Zyngier wrote:
> >> On Thu, 22 Feb 2018 14:42:27 +,
> >> Christoffer Dall wrote:
> >>>
> &g
On Wed, Feb 21, 2018 at 06:26:39PM +, Marc Zyngier wrote:
> On Thu, 15 Feb 2018 21:03:26 +,
> Christoffer Dall wrote:
> >
> > To make the code more readable and to avoid the overhead of a function
> > call, let's get rid of a pair of the alternative function
On Wed, Feb 21, 2018 at 06:20:54PM +, Marc Zyngier wrote:
> On Thu, 15 Feb 2018 21:03:25 +,
> Christoffer Dall wrote:
> >
> > We do not have to change the c15 trap setting on each switch to/from the
> > guest on VHE systems, because this setting only affects EL
On Wed, Feb 21, 2018 at 05:59:37PM +, Marc Zyngier wrote:
> On Thu, 15 Feb 2018 21:03:23 +,
> Christoffer Dall wrote:
> >
> > As we are about to be more lazy with some of the trap configuration
> > register read/writes for VHE systems, move the logic that is curr
On Wed, Feb 21, 2018 at 04:27:25PM +, Marc Zyngier wrote:
> On Thu, 15 Feb 2018 21:03:22 +,
> Christoffer Dall wrote:
> >
> > When running a 32-bit VM (EL1 in AArch32), the AArch32 system registers
> > can be deferred to vcpu load/put on VHE systems because neither
On Thu, Feb 22, 2018 at 03:01:17PM +, Marc Zyngier wrote:
> On Thu, 22 Feb 2018 14:42:27 +,
> Christoffer Dall wrote:
> >
> > On Thu, Feb 22, 2018 at 12:32:11PM +, Marc Zyngier wrote:
> > > On 15/02/18 21:03, Christoffer Dall wrote:
> > >
On Thu, Feb 22, 2018 at 04:11:38PM +0100, Andrew Jones wrote:
>
> Hi Christoffer,
>
> I'm just pointing out some broken lines that we could maybe cheat the
> 80-char limit on. Naturally feel free to ignore.
Thanks. I'll go over them as I respin.
-Christoffer
___
On Thu, Feb 22, 2018 at 03:35:06PM +0100, Andrew Jones wrote:
> On Thu, Feb 15, 2018 at 10:03:22PM +0100, Christoffer Dall wrote:
> > When running a 32-bit VM (EL1 in AArch32), the AArch32 system registers
> > can be deferred to vcpu load/put on VHE systems because neither
> >
On Thu, Feb 22, 2018 at 02:40:52PM +0100, Andrew Jones wrote:
> On Thu, Feb 15, 2018 at 10:03:17PM +0100, Christoffer Dall wrote:
> > We are about to defer saving and restoring some groups of system
> > registers to vcpu_put and vcpu_load on supported systems. This means
> &
On Thu, Feb 22, 2018 at 01:11:55PM +, Marc Zyngier wrote:
> On 15/02/18 21:03, Christoffer Dall wrote:
> > The APRs can only have bits set when the guest acknowledges an interrupt
> > in the LR and can only have a bit cleared when the guest EOIs an
> > interrupt in the
On Thu, Feb 22, 2018 at 12:32:11PM +, Marc Zyngier wrote:
> On 15/02/18 21:03, Christoffer Dall wrote:
> > Just like we can program the GICv2 hypervisor control interface directly
> > from the core vgic code, we can do the same for the GICv3 hypervisor
> > control int
On Thu, Feb 22, 2018 at 12:33:20PM +, Marc Zyngier wrote:
> On 15/02/18 21:03, Christoffer Dall wrote:
> > The vgic-v2-sr.c file now only contains the logic to replay unaligned
> > accesses to the virtual CPU interface on 16K and 64K page systems, which
> > is only relevan
On Thu, Feb 22, 2018 at 02:34:21PM +0100, Andrew Jones wrote:
> On Thu, Feb 15, 2018 at 10:03:16PM +0100, Christoffer Dall wrote:
> > From: Christoffer Dall
> >
> > Currently we access the system registers array via the vcpu_sys_reg()
> > macro. However, we are abou
On Thu, Feb 22, 2018 at 10:48:10AM +, Marc Zyngier wrote:
> On Thu, 22 Feb 2018 09:22:37 +,
> Christoffer Dall wrote:
> >
> > On Wed, Feb 21, 2018 at 01:32:45PM +, Marc Zyngier wrote:
> > > On Thu, 15 Feb 2018 21:03:16 +0000,
> > > Christoff
On Thu, Feb 22, 2018 at 10:56:41AM +0100, Andrew Jones wrote:
> On Thu, Feb 22, 2018 at 10:10:34AM +0100, Christoffer Dall wrote:
> > On Wed, Feb 21, 2018 at 06:32:00PM +0100, Andrew Jones wrote:
> > >
> > > Besides my confusion on motivation, it looks good to me
&
On Wed, Feb 21, 2018 at 02:47:44PM +, Marc Zyngier wrote:
> On Thu, 15 Feb 2018 21:03:18 +,
> Christoffer Dall wrote:
> >
> > SPSR_EL1 is not used by a VHE host kernel and can be deferred, but we
> > need to rework the accesses to this register to access the lates
On Mon, Feb 19, 2018 at 06:12:29PM +, Julien Grall wrote:
> Hi Christoffer,
>
> On 15/02/18 21:03, Christoffer Dall wrote:
> >From: Christoffer Dall
> >
> >Currently we access the system registers array via the vcpu_sys_reg()
> >macro. However, we are abo
On Mon, Feb 19, 2018 at 05:21:17PM +, Julien Grall wrote:
> Hi Christoffer,
>
> On 15/02/18 21:03, Christoffer Dall wrote:
> >There's a semantic difference between the EL1 registers that control
> >operation of a kernel running in EL1 and EL1 registers that only cont
On Wed, Feb 21, 2018 at 01:32:45PM +, Marc Zyngier wrote:
> On Thu, 15 Feb 2018 21:03:16 +,
> Christoffer Dall wrote:
> >
> > From: Christoffer Dall
> >
> > Currently we access the system registers array via the vcpu_sys_reg()
> > macro. However, we
On Wed, Feb 21, 2018 at 07:18:32PM +0100, Andrew Jones wrote:
> On Wed, Feb 21, 2018 at 06:43:00PM +0100, Andrew Jones wrote:
> > On Thu, Feb 15, 2018 at 10:03:05PM +0100, Christoffer Dall wrote:
> > > So far this is mostly (see below) a copy of the legacy non-VHE switch
>
On Wed, Feb 21, 2018 at 12:05:27PM +, Marc Zyngier wrote:
> On Thu, 15 Feb 2018 21:03:00 +,
> Christoffer Dall wrote:
> >
> > We have numerous checks around that checks if the HCR_EL2 has the RW bit
> > set to figure out if we're running an AArch64 or A
On Wed, Feb 21, 2018 at 06:32:00PM +0100, Andrew Jones wrote:
> On Thu, Feb 15, 2018 at 10:02:55PM +0100, Christoffer Dall wrote:
> > We already have the percpu area for the host cpu state, which points to
> > the VCPU, so there's no need to store the VCPU pointer on the stack
On Wed, Feb 21, 2018 at 11:34:07AM +, Marc Zyngier wrote:
> On Thu, 15 Feb 2018 21:02:55 +,
> Christoffer Dall wrote:
> >
> > We already have the percpu area for the host cpu state, which points to
> > the VCPU, so there's no need to store the VCPU poin
On Mon, Feb 19, 2018 at 03:50:20PM +, Julien Grall wrote:
> Hi Christoffer,
>
> On 15/02/18 21:02, Christoffer Dall wrote:
> >We already have the percpu area for the host cpu state, which points to
> >the VCPU, so there's no need to store the VCPU pointer on the
Hi Shanker,
On Mon, Feb 19, 2018 at 09:38:07AM -0600, Shanker Donthineni wrote:
> In AArch64/AArch32, the virtual counter uses a fixed virtual offset
> of zero in the following situations as per ARMv8 specifications:
>
> 1) HCR_EL2.E2H is 1, and CNTVCT_EL0/CNTVCT are read from EL2.
> 2) HCR_EL2.{
On Fri, Feb 16, 2018 at 09:33:39AM +, Marc Zyngier wrote:
> On 16/02/18 09:05, Christoffer Dall wrote:
> > On Thu, Feb 15, 2018 at 01:22:56PM +, Marc Zyngier wrote:
> >> On 15/01/18 15:36, Christoffer Dall wrote:
> >>> On Thu, Jan 04, 2018 at 06:43:
On Thu, Feb 15, 2018 at 03:32:52PM +, Marc Zyngier wrote:
> On 18/01/18 20:28, Christoffer Dall wrote:
> > On Thu, Jan 04, 2018 at 06:43:33PM +, Marc Zyngier wrote:
> >> The main idea behind randomising the EL2 VA is that we usually have
> >> a few spare bits b
On Thu, Feb 15, 2018 at 01:52:05PM +, Marc Zyngier wrote:
> On 18/01/18 14:39, Christoffer Dall wrote:
> > On Thu, Jan 04, 2018 at 06:43:29PM +, Marc Zyngier wrote:
> >> We so far mapped our HYP IO (which is essencially the GICv2 control
> >> registers) using th
On Thu, Feb 15, 2018 at 01:22:56PM +, Marc Zyngier wrote:
> On 15/01/18 15:36, Christoffer Dall wrote:
> > On Thu, Jan 04, 2018 at 06:43:25PM +, Marc Zyngier wrote:
> >> kvm_vgic_global_state is part of the read-only section, and is
> >> usually accessed
On Thu, Feb 15, 2018 at 01:11:02PM +, Marc Zyngier wrote:
> On 15/01/18 11:47, Christoffer Dall wrote:
> > On Thu, Jan 04, 2018 at 06:43:23PM +, Marc Zyngier wrote:
> >> So far, we're using a complicated sequence of alternatives to
> >> patch the kernel/hyp
On Tue, Feb 13, 2018 at 11:41:16AM +0100, Jérémy Fanguède wrote:
> Set the handlers to emulate read and write operations for CNTP_CTL,
> CNTP_CVAL and CNTP_TVAL registers in such a way that VMs can use the
> physical timer.
>
> Signed-off-by: Jérémy Fanguède
> ---
>
> This patch is the equivalen
when running in the host), and doing the
configuration on every round-trip on non-VHE systems.
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v3:
- Removed extra blank line
arch/arm/include/asm/kvm_hyp.h | 2 +
arch/arm/kvm/hyp/switch.c| 8 ++-
arch/arm64/include
for migration. To make sure
this works, factor out the APR save/restore functionality into separate
functions called from the VCPU (and by extension VGIC) put/load hooks.
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_hyp.h | 2 +
arch/arm64/include/asm/kvm_hyp.h | 2 +
virt
though we have never
actually run the guest with the newly written GIC state. We solve this
by inserting an ISB in the early exit path.
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v2:
- Added ISB in the early exit path in the run loop as explained
in the commit message
remove the ifdef in the C file.
Reviewed-by: Andre Przywara
Signed-off-by: Christoffer Dall
---
arch/arm/kvm/hyp/Makefile | 1 -
arch/arm64/kvm/hyp/Makefile | 2 +-
{virt/kvm/arm => arch/arm64/kvm}/hyp/vgic-v2-sr.c | 2 --
3 files changed, 1 insert
We can program the GICv2 hypervisor control interface logic directly
from the core vgic code and can instead do the save/restore directly
from the flush/sync functions, which can lead to a number of future
optimizations.
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v1
the endianness conversion in the VGIC save
function, which is completely unnecessary and would actually result in
incorrect functionality on big-endian systems, because we are only using
typed values here and not converting pointers and reading different
types here.
Signed-off-by: Christoffer Dall
tatic function if it can.
Signed-off-by: Christoffer Dall
---
arch/arm64/kvm/hyp/switch.c | 30 ++
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 5e94955b89ea..0e54fe2aab1c 100644
--- a/arch/
while executing KVM kernel code.
Signed-off-by: Christoffer Dall
---
arch/arm64/include/asm/kvm_hyp.h | 3 +++
arch/arm64/kvm/hyp/switch.c | 31 ++-
arch/arm64/kvm/hyp/sysreg-sr.c | 4
3 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/arch/
There is no longer a need for an alternative to choose the right
function to tell us whether or not FPSIMD was enabled for the VM,
because we can simply cann the appropriate functions directly fromwithin
the _vhe and _nvhe run functions.
Signed-off-by: Christoffer Dall
---
Notes:
Changes
: Christoffer Dall
---
Notes:
Changes since v3:
- Separate fpsimd32 trap configuration into a separate function
which is still called from __activate_traps, because we no longer
defer saving/restoring of VFP registers to load/put.
arch/arm64/kvm/hyp/switch.c | 76
assembly handler from taking the EL2 fault, and therefore we have to
check if fpsimd is enabled for the guest in the exit path and save the
register then, for both VHE and non-VHE guests.
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v3:
- Rework the FPEXC32 save/restore logic to
32-bit registers are not used by a 64-bit host kernel and can be
deferred, but we need to rework the accesses to this register to access
the latest value depending on whether or not guest system registers are
loaded on the CPU or only reside in memory.
Signed-off-by: Christoffer Dall
---
Notes
this
value.
The 32-bit sysregs can also be deferred but we do this in a separate
patch as it requires a bit more infrastructure.
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v3:
- Changed to switch-based sysreg approach
arch/arm64/kvm/
32-bit VMs is a
bit clunky, but this will be improved in following patches which will
first prepare and subsequently implement deferred save/restore of the
32-bit registers, including the 32-bit SPSRs.
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v2:
- New patch (deferred
ELR_EL1 is not used by a VHE host kernel and can be deferred, but we
need to rework the accesses to this register to access the latest value
depending on whether or not guest system registers are loaded on the CPU
or only reside in memory.
Signed-off-by: Christoffer Dall
---
Notes:
Changes
easier when we have to start
accessing system registers that use deferred save/restore and might
have to be read directly from the physical CPU.
Reviewed-by: Andrew Jones
Reviewed-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm64/include/asm/kvm_host.h | 8
arch/arm64
s where it is clear which registers become
deferred.
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v3:
- Changed to a switch-statement based approach to improve
readability.
Changes since v2:
- New patch (deferred register handling has been reworked)
From: Christoffer Dall
Currently we access the system registers array via the vcpu_sys_reg()
macro. However, we are about to change the behavior to some times
modify the register file directly, so let's change this to two
primitives:
* Accessor macros vcpu_write_sys_reg(
e the other into simply save/restore.
Reviewed-by: Andrew Jones
Reviewed-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm64/include/asm/kvm_hyp.h | 6 ++
arch/arm64/kvm/hyp/switch.c | 10 +-
arch/arm64/kvm/hyp/sysreg-sr.c | 18 ++
3 files chang
-by: Christoffer Dall
---
arch/arm64/kvm/hyp/sysreg-sr.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
index d35b3aa680ab..906606dc4e2c 100644
--- a/arch/arm64/kvm/hyp/sysreg-sr.c
+++ b/arch/arm64/kvm/hyp/sysreg
The comment only applied to SPE on non-VHE systems, so we simply remove
it.
Suggested-by: Andrew Jones
Acked-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm64/kvm/hyp/switch.c | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp
VHE and non-VHE functionality now that we have
separate functions.
Reviewed-by: Andrew Jones
Reviewed-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm64/include/asm/kvm_hyp.h | 12
arch/arm64/kvm/hyp/switch.c | 20 ++--
arch/arm64/kvm/hyp/sysreg
As we are about to move calls around in the sysreg save/restore logic,
let's first rewrite the alternative function callers, because it is
going to make the next patches much easier to read.
Acked-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm64/kvm/hyp/sysreg-sr.c
ff-by: Christoffer Dall
---
Notes:
Changes since v3:
- Correct the comment about ACTLR_EL1 and adjust commit text.
Changes since v2:
- Save restore ACTLR_EL1 as part of the EL1 registers state instead of
the user register state, as ACTLR_EL1 can't affect the host&#
Marc Zyngier
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v2:
- Added comment explaining the timer enable/disable functions
are for !VHE only.
arch/arm64/kvm/hyp/switch.c | 2 --
virt/kvm/arm/hyp/timer-sr.c | 44 ++--
2 files ch
There is no need to reset the VTTBR to zero when exiting the guest on
VHE systems. VHE systems don't use stage 2 translations for the EL2&0
translation regime used by the host.
Reviewed-by: Andrew Jones
Acked-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
Notes:
Changes
switch
functions.
No functional change.
Reviewed-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm64/kvm/hyp/switch.c | 104
1 file changed, 57 insertions(+), 47 deletions(-)
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp
VHE kernels run completely in EL2 and therefore don't have a notion of
kernel and hyp addresses, they are all just kernel addresses. Therefore
don't call kern_hyp_va() in the VHE switch function.
Reviewed-by: Andrew Jones
Reviewed-by: Marc Zyngier
Signed-off-by: Christoffer Dall
that we omit the branch-predictor variant-2 hardening for
QC Falkor CPUs, because this workaround is specific to a series of
non-VHE ARMv8.0 CPUs.
Reviewed-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v3:
- Added BUG() to 32-bit ARM VHE run function
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v1:
- Change dot to comma in comment
- Rename __debug_restore_spe to __debug_restore_spe_nvhe
arch/arm64/kvm/hyp/debug-sr.c | 26 --
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/arch/arm6
e for switching to the host context, and we get the
benefit of only having to evaluate the dirty flag once on each path,
plus we give the compiler some more room to inline some of this
functionality.
Reviewed-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v1:
- R
nd
for the following patches that optimize KVM on AArch64 hosts with VHE.
Therefore, introduce a helper, vcpu_el1_is_32bit, and replace existing
direct checks of HCR_EL2.RW with the helper.
Reviewed-by: Julien Grall
Reviewed-by: Julien Thierry
Signed-off-by: Christoffer Dall
---
Notes:
Change
: Christoffer Dall
---
arch/arm64/kvm/debug.c| 5 +
arch/arm64/kvm/hyp/debug-sr.c | 6 --
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c
index fa63b28c65e0..feedb877cff8 100644
--- a/arch/arm64/kvm/debug.c
+++ b/arch/arm64/kvm
odify the bits in the vcpu->arch.hcr[_el2] directly when
needed.
Acked-by: Marc Zyngier
Reviewed-by: Andrew Jones
Reviewed-by: Julien Thierry
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_emulate.h | 9 ++---
arch/arm/include/asm/kvm_host.h | 3 ---
arch/arm/kvm/e
As we are about to move a bunch of save/restore logic for VHE kernels to
the load and put functions, we need some infrastructure to do this.
Reviewed-by: Andrew Jones
Acked-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v1:
- Reworded comments as suggested
e the HCR_RW bit set when returning to EL1 on non-VHE systems.
Reviewed-by: Marc Zyngier
Signed-off-by: Shih-Wei Li
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v3:
- Slightly reworded the commit message
arch/arm64/include/asm/kvm_arm.h | 4 ++--
arch/arm64/kvm/hyp/swi
n
VBAR_EL2 has been set to the KVM exception vectors. On VHE, we can
always safely disable the traps and restore the host registers at this
point, so we simply do that unconditionally and call into the panic
function directly.
Acked-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
Notes:
e the _EL1 accessor on VHE systems, but this was actually unnecessary
as the _EL1 accessor aliases the ESR_EL2 register on VHE, and the _EL2
accessor does the same thing on both systems.
Cc: Ard Biesheuvel
Signed-off-by: Christoffer Dall
---
Notes:
Changes since v3:
- Reworked the assemb
Moving the call to vcpu_load() in kvm_arch_vcpu_ioctl_run() to after
we've called kvm_vcpu_first_run_init() simplifies some of the vgic and
there is also no need to do vcpu_load() for things such as handling the
immediate_exit flag.
Reviewed-by: Julien Grall
Signed-off-by: Christoffer
ll
Signed-off-by: Christoffer Dall
---
arch/arm64/kvm/guest.c | 3 ---
virt/kvm/arm/arm.c | 9 -
2 files changed, 12 deletions(-)
diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
index d7e3299a7734..959e50d2588c 100644
--- a/arch/arm64/kvm/guest.c
+++ b/arch/arm64/k
ernel/git/cdall/linux.git
vhe-optimize-v4
Christoffer Dall (39):
KVM: arm/arm64: Avoid vcpu_load for other vcpu ioctls than KVM_RUN
KVM: arm/arm64: Move vcpu_load call after kvm_vcpu_first_run_init
KVM: arm64: Avoid storing the vcpu pointer on the stack
KVM: arm64: Rework hyp_panic for VH
On Wed, Feb 14, 2018 at 02:43:42PM +, Dave Martin wrote:
> [CC Ard, in case he has a view on how much we care about softirq NEON
> performance regressions ... and whether my suggestions make sense]
>
> On Wed, Feb 14, 2018 at 11:15:54AM +0100, Christoffer Dall wrote:
> > On
On Fri, Feb 09, 2018 at 06:50:14PM +, Julien Grall wrote:
> Hi Christoffer,
>
> On 01/12/2018 12:07 PM, Christoffer Dall wrote:
> >There's a semantic difference between the EL1 registers that control
> >operation of a kernel running in EL1 and EL1 registers that
reRelease
> respectively. We can ensure this by clearing LORC_EL1.EN when a CPU's
> EL2 is first initialized, as the host kernel will not modify this.
>
> Signed-off-by: Mark Rutland
> Cc: Vladimir Murzin
> Cc: Catalin Marinas
> Cc: Christoffer Dall
> Cc: M
On Tue, Feb 13, 2018 at 02:08:47PM +, Dave Martin wrote:
> On Tue, Feb 13, 2018 at 09:51:30AM +0100, Christoffer Dall wrote:
> > On Fri, Feb 09, 2018 at 03:59:30PM +, Dave Martin wrote:
> > > On Wed, Feb 07, 2018 at 06:56:44PM +0100, Christoffer Dall wrote:
> > >
On Fri, Feb 09, 2018 at 05:53:43PM +, Julien Grall wrote:
> Hi Christoffer,
>
> On 01/12/2018 12:07 PM, Christoffer Dall wrote:
> >The VHE switch function calls __timer_enable_traps and
> >__timer_disable_traps which don't do anything on VHE systems.
> >Ther
On Fri, Feb 09, 2018 at 11:38:50AM +, Julien Grall wrote:
> Hi,
>
> On 01/12/2018 12:07 PM, Christoffer Dall wrote:
> >From: Shih-Wei Li
> >
> >We always set the IMO and FMO bits in the HCR_EL2 when running the
> >guest, regardless if we use the vgic
ensure this by clearing LORC_EL1.EN when a CPU's
> EL2 is first initialized, as the host kernel will not modify this.
>
> Signed-off-by: Mark Rutland
> Reviewed-by: Vladimir Murzin
> Cc: Catalin Marinas
> Cc: Christoffer Dall
> Cc: Marc Zyngier
> Cc: Wi
On Fri, Feb 09, 2018 at 04:17:39PM +, Dave Martin wrote:
> On Thu, Jan 25, 2018 at 08:54:13PM +0100, Christoffer Dall wrote:
> > On Tue, Jan 23, 2018 at 04:04:40PM +, Dave Martin wrote:
> > > On Fri, Jan 12, 2018 at 01:07:32PM +0100, Christoffer Dall wrote:
> > &
On Fri, Feb 09, 2018 at 05:53:43PM +, Julien Grall wrote:
> Hi Christoffer,
>
> On 01/12/2018 12:07 PM, Christoffer Dall wrote:
> >The VHE switch function calls __timer_enable_traps and
> >__timer_disable_traps which don't do anything on VHE systems.
> >Ther
On Fri, Feb 09, 2018 at 05:34:05PM +, Julien Grall wrote:
> Hi Christoffer,
>
> On 01/12/2018 12:07 PM, Christoffer Dall wrote:
> >So far this is just a copy of the legacy non-VHE switch function, but we
> >will start reworking these functions in separate directions to w
On Fri, Feb 09, 2018 at 03:26:59PM +, Julien Grall wrote:
> Hi Christoffer,
>
> On 01/12/2018 12:07 PM, Christoffer Dall wrote:
> >Avoid saving the guest VFP registers and restoring the host VFP
> >registers on every exit from the VM. Only when we're about to
On Fri, Feb 09, 2018 at 03:59:30PM +, Dave Martin wrote:
> On Wed, Feb 07, 2018 at 06:56:44PM +0100, Christoffer Dall wrote:
> > On Wed, Feb 07, 2018 at 04:49:55PM +, Dave Martin wrote:
> > > On Thu, Jan 25, 2018 at 08:46:53PM +0100, Christoffer Dall wrote:
> > >
On Thu, Feb 08, 2018 at 05:53:17PM +, Suzuki K Poulose wrote:
> On 08/02/18 11:14, Christoffer Dall wrote:
> >On Tue, Jan 09, 2018 at 07:04:10PM +, Suzuki K Poulose wrote:
> >>Allow the guests to choose a larger physical address space size.
> >>The default an
On Thu, Feb 08, 2018 at 05:22:29PM +, Suzuki K Poulose wrote:
> On 08/02/18 11:00, Christoffer Dall wrote:
> >On Tue, Jan 09, 2018 at 07:04:09PM +, Suzuki K Poulose wrote:
> >>Now that we can manage the stage2 page table per VM, switch the
> >>configuration det
On Thu, Feb 08, 2018 at 05:19:22PM +, Suzuki K Poulose wrote:
> On 08/02/18 11:00, Christoffer Dall wrote:
> >On Tue, Jan 09, 2018 at 07:04:03PM +, Suzuki K Poulose wrote:
> >>On arm/arm64 we pre-allocate the entry level page tables when
> >>a VM is created an
table. The common configuration for
> VTCR is still performed during the early init. But the SL0
> and T0SZ are programmed for each VM and is cleared once we
> exit the VM.
>
> Cc: Marc Zyngier
> Cc: Christoffer Dall
> Signed-off-by: Suzuki K Poulose
> ---
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