= read_sysreg_el1(SYS_TTBR0);
> @@ -95,7 +94,6 @@ static inline void __sysreg_restore_user_state(struct
> kvm_cpu_context *ctxt)
> static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
> {
> write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2);
Hi Jonathan,
On Tue, Jan 3, 2023 at 4:47 AM Marc Zyngier wrote:
>
> On Tue, 03 Jan 2023 12:40:34 +,
> Jonathan Cameron wrote:
> >
> > On Thu, 29 Dec 2022 19:59:21 -0800
> > Reiji Watanabe wrote:
> >
> > > The goal of this series is to allow usersp
Add a new test case to the vpmu_counter_access test to check
if PMU registers or their bits for unimplemented counters are not
accessible or are RAZ, as expected.
Signed-off-by: Reiji Watanabe
---
.../kvm/aarch64/vpmu_counter_access.c | 103 +-
.../selftests/kvm/include
Add a new test case to the vpmu_counter_access test to check if PMU
registers or their bits for implemented counters on the vCPU are
readable/writable as expected, and can be programmed to count events.
Signed-off-by: Reiji Watanabe
---
.../kvm/aarch64/vpmu_counter_access.c | 347
is equal to
or less than PMCR_EL1.N on the host.
Signed-off-by: Reiji Watanabe
---
tools/testing/selftests/kvm/.gitignore| 1 +
tools/testing/selftests/kvm/Makefile | 1 +
.../kvm/aarch64/vpmu_counter_access.c | 181 ++
3 files changed, 183 insertions
Copy perf_event.h from the kernel's arch/arm64/include/asm/perf_event.h.
The following patches will use macros defined in this header.
Signed-off-by: Reiji Watanabe
---
tools/arch/arm64/include/asm/perf_event.h | 258 ++
1 file changed, 258 insertions(+)
create mode 1
reset_pmcr() resets
PMCR_EL0.N to the host value on vCPU reset.
Change reset_pmcr() to preserve the vCPU's PMCR_EL0.N value on
vCPU reset so that userspace can limit the number of the PMU
event counter on the vCPU.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/pmu-emul.c | 6 ++
arch/
The default reset function for PMU registers (reset_pmu_reg())
now simply clears a specified register. Use that function for
PMUSERENR_EL0 and PMCCFILTR_EL0, since those registers should
simply be cleared on vCPU reset.
No functional change intended.
Signed-off-by: Reiji Watanabe
---
arch
RAZ bits of those registers could end up being set to 1).
Fix reset_pmu_reg() to clear the registers so that it can ensure
that all the RAZ bits are cleared even when the PMCR_EL1.N value
for the vCPU is different from the host value.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c
es at the following commit:
commit aff234839f8b ("KVM: arm64: PMU: Fix PMCR_EL0 reset value")
Reiji Watanabe (7):
KVM: arm64: PMU: Have reset_pmu_reg() to clear a register
KVM: arm64: PMU: Use reset_pmu_reg() for PMUSERENR_EL0 and
PMCCFILTR_EL0
KVM: arm64: PMU: Preserve vC
Hi Marc,
On Thu, Nov 24, 2022 at 2:17 AM Marc Zyngier wrote:
>
> On Wed, 23 Nov 2022 17:11:41 +0000,
> Reiji Watanabe wrote:
> >
> > Hi Marc,
> >
> > On Wed, Nov 23, 2022 at 3:11 AM Marc Zyngier wrote:
> > >
> > > On Wed, 23 N
Hi Marc,
On Wed, Nov 23, 2022 at 3:11 AM Marc Zyngier wrote:
>
> On Wed, 23 Nov 2022 05:58:17 +0000,
> Reiji Watanabe wrote:
> >
> > Hi Marc,
> >
> > On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier wrote:
> > >
> > > PMUv3p5 (which is mandatory
step and directly compute the target
> vcpu.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Reiji Watanabe
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On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier wrote:
>
> Now that the infrastructure is in place, bump the PMU support up
> to PMUv3p5.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Reiji Watanabe
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Hi Marc,
On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier wrote:
>
> PMUv3p5 (which is mandatory with ARMv8.5) comes with some extra
> features:
>
> - All counters are 64bit
>
> - The overflow point is controlled by the PMCR_EL0.LP bit
>
> Add the required checks in the helpers that control counter
>
IMP_DEF (I have the same
comment for pmuver_to_perfmon in the patch-10).
> + default:
> + /* Anything ARMv8.1+ has the same value. For now. */
Nit: Shouldn't the comment also mention NI (and IMP_DEF) ?
(I have the same comment for pmuver_to_perfmon in the
On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier wrote:
>
> Allow userspace to write ID_AA64DFR0_EL1, on the condition that only
> the PMUver field can be altered and be at most the one that was
> initially computed for the guest.
>
> Signed-off-by: Marc Zyngier
Reviewed-
Hi Marc,
On Sun, Nov 13, 2022 at 8:38 AM Marc Zyngier wrote:
>
> Even when using PMUv3p5 (which implies 64bit counters), there is
> no way for AArch32 to write to the top 32 bits of the counters.
> The only way to influence these bits (other than by counting
> events) is by writing PMCR.P==1.
>
>
Hi Marc,
On Sun, Nov 13, 2022 at 8:38 AM Marc Zyngier wrote:
>
> In order to reduce the boilerplate code, add two helpers returning
> the counter register index (resp. the event register) in the vcpu
> register file from the counter index.
>
> Reviewed-by: Oliver Upton
> Signed-off-by: Marc Zyng
n.
>
> Link: https://lore.kernel.org/all/20221006003409.649993-8-sea...@google.com
> Cc: Oliver Upton
> Cc: Marc Zyngier
> Signed-off-by: Sean Christopherson
Reviewed-by: Reiji Watanabe
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pens unconditionally.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Reiji Watanabe
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ow(vcpu, i) ? reg :
> lower_32_bits(reg))
A few lines up, the 'reg' is unconditionally updated with
"lower_32_bits(reg)". So, the change initially confused me
(until I checked the following patch). IMHO it might be more
clear if this patch and the next pa
tively disables single-step debug.
>
> No functional change intended.
>
> Cc: Reiji Watanabe
> Fixes: b18e4d4aebdd ("KVM: arm64: selftests: Add a test case for
> KVM_GUESTDBG_SINGLESTEP")
> Signed-off-by: Sean Christopherson
> ---
> tools/testing/selftests/kvm
and "canonical counter".
> The code is further restructured to make the CHAIN handling similar
> to SWINC, as the two are now extremely similar in behaviour.
>
> Reported-by: Ricardo Koller
> Signed-off-by: Marc Zyngier
Reviewed-by: Reiji Watanabe
__
Hi Marc,
> > > +#define PERF_ATTR_CFG1_COUNTER_64BIT BIT(0)
> >
> > Although this isn't the new code (but just a name change),
> > wouldn't it be nicer to have armv8pmu_event_is_64bit()
> > (in arch/arm64/kernel/perf_event.c) use the macro as well ?
>
> We tried that in the past, and the amount
;
> Signed-off-by: Marc Zyngier
Reviewed-by: Reiji Watanabe
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Hi Marc,
On Mon, Nov 7, 2022 at 12:54 AM Marc Zyngier wrote:
>
> Ricardo recently pointed out that the PMU chained counter emulation
> in KVM wasn't quite behaving like the one on actual hardware, in
> the sense that a chained counter would expose an overflow on
> both halves of a chained counter
Hi Marc,
On Mon, Nov 7, 2022 at 1:16 AM Marc Zyngier wrote:
>
> Allow userspace to write ID_AA64DFR0_EL1, on the condition that only
> the PMUver field can be altered and be at most the one that was
> initially computed for the guest.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/kvm/sys_r
Hi Marc,
> > BTW, if we have no intention of supporting a mix of vCPUs with and
> > without PMU, I think it would be nice if we have a clear comment on
> > that in the code. Or I'm hoping to disallow it if possible though.
>
> I'm not sure we're in a position to do this right now. The current API
Hi Marc,
On Fri, Nov 4, 2022 at 5:21 AM Marc Zyngier wrote:
>
> Hi Reiji,
>
> On Fri, 04 Nov 2022 07:00:22 +0000,
> Reiji Watanabe wrote:
> >
> > On Thu, Nov 3, 2022 at 3:25 AM Marc Zyngier wrote:
> > >
> > > On Thu, 03 Nov 2022 05:31:56 +,
&g
Hi Marc,
On Thu, Nov 3, 2022 at 3:25 AM Marc Zyngier wrote:
>
> On Thu, 03 Nov 2022 05:31:56 +0000,
> Reiji Watanabe wrote:
> >
> > Hi Marc,
> >
> > On Fri, Oct 28, 2022 at 4:16 AM Marc Zyngier wrote:
> > >
> > > Allow userspace to write ID
Hi Marc,
On Thu, Nov 3, 2022 at 1:44 AM Marc Zyngier wrote:
>
> Hi Reiji,
>
> On Thu, 03 Nov 2022 04:55:52 +0000,
> Reiji Watanabe wrote:
> >
> > Hi Marc,
> >
> > On Fri, Oct 28, 2022 at 4:16 AM Marc Zyngier wrote:
> > >
> > > ca
Hi Marc,
On Fri, Oct 28, 2022 at 4:16 AM Marc Zyngier wrote:
>
> Allow userspace to write ID_AA64DFR0_EL1, on the condition that only
> the PMUver field can be altered and be at most the one that was
> initially computed for the guest.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/kvm/sys_
Hi Marc,
On Fri, Oct 28, 2022 at 4:16 AM Marc Zyngier wrote:
>
> As further patches will enable the selection of a PMU revision
> from userspace, sample the supported PMU revision at VM creation
> time, rather than building each time the ID_AA64DFR0_EL1 register
> is accessed.
>
> This shouldn't
Hi Marc,
> Sorry it took so long to get back to this.
No problem!
>
> On Fri, 26 Aug 2022 07:02:21 +0100,
> Reiji Watanabe wrote:
> >
> > Hi Marc,
> >
> > On Thu, Aug 25, 2022 at 9:34 PM Reiji Watanabe wrote:
> > >
> > > Hi Marc,
> >
Hi Marc,
> > > +static void kvm_pmu_counter_increment(struct kvm_vcpu *vcpu,
> > > + unsigned long mask, u32 event)
> > > +{
> > > + int i;
> > > +
> > > + if (!kvm_vcpu_has_pmu(vcpu))
> > > + return;
> > > +
> > > + if (!(__vcpu_
Hi Oliver,
On Thu, Oct 20, 2022 at 12:08 PM Oliver Upton wrote:
>
> On Wed, Oct 19, 2022 at 10:41:54PM -0700, Reiji Watanabe wrote:
> > Use FIELD_GET() macro to extract ID register fields for existing
> > aarch64 selftests code. No functional change intended.
> >
Currently, the debug-exceptions test always uses only
{break,watch}point#0 and the highest numbered context-aware
breakpoint. Modify the test to use all {break,watch}points and
context-aware breakpoints supported on the system.
Signed-off-by: Reiji Watanabe
---
.../selftests/kvm/aarch64/debug
aware breakpoint.
Signed-off-by: Reiji Watanabe
---
.../selftests/kvm/aarch64/debug-exceptions.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c
b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c
index 362e766
s the breakpoint#0 (for Address Match), which
is linked to the context-aware breakpoint.
Signed-off-by: Reiji Watanabe
---
.../selftests/kvm/aarch64/debug-exceptions.c | 63 +--
1 file changed, 57 insertions(+), 6 deletions(-)
diff --git a/tools/testing/selftests/kvm/aarch64/
Change debug_version() to take the ID_AA64DFR0_EL1 value instead of
vcpu as an argument, and change its callsite to read ID_AA64DFR0_EL1
(and pass it to debug_version()).
Subsequent patches will reuse the register value in the callsite.
No functional change intended.
Signed-off-by: Reiji
Currently, debug-exceptions test unnecessarily tracks some test stages
using GUEST_SYNC(). The code for it needs to be updated as test cases
are added or removed. Stop doing the unnecessary stage tracking,
as they are not so useful and are a bit pain to maintain.
Signed-off-by: Reiji Watanabe
Add helpers to enable breakpoint and watchpoint exceptions.
No functional change intended.
Signed-off-by: Reiji Watanabe
Reviewed-by: Ricardo Koller
Reviewed-by: Oliver Upton
---
.../selftests/kvm/aarch64/debug-exceptions.c | 25 ++-
1 file changed, 13 insertions(+), 12
{break,watch}points are specified for guest_code().
Subsequent patches will add test cases for non-zero {break,watch}points.
Signed-off-by: Reiji Watanabe
Reviewed-by: Ricardo Koller
---
.../selftests/kvm/aarch64/debug-exceptions.c | 50 ---
1 file changed, 32 insertions(+), 18
Introduce helpers in the debug-exceptions test to write to
dbg{b,w}{c,v}r registers. Those helpers will be useful for
test cases that will be added to the test in subsequent patches.
No functional change intended.
Signed-off-by: Reiji Watanabe
Reviewed-by: Ricardo Koller
---
.../selftests
Use FIELD_GET() macro to extract ID register fields for existing
aarch64 selftests code. No functional change intended.
Signed-off-by: Reiji Watanabe
---
tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c | 3 ++-
tools/testing/selftests/kvm/aarch64/debug-exceptions.c | 3 ++-
tools/testing
/20220825050846.3418868-1-rei...@google.com/
[1] https://lore.kernel.org/all/20221017195834.2295901-6-ricar...@google.com/
Reiji Watanabe (9):
KVM: arm64: selftests: Use FIELD_GET() to extract ID register fields
KVM: arm64: selftests: Add write_dbg{b,w}{c,v}r helpers in
debug-exceptions
KVM
Hi Mingwei,
On Mon, Sep 26, 2022 at 5:27 PM Mingwei Zhang wrote:
>
> Cleanup __get_fault_info() to take out the code that checks HPFAR. The
> conditions in __get_fault_info() that checks if HPFAR contains a valid IPA
> is slightly messy in that several conditions are written within one IF
> state
Hi Marc,
On Mon, Sep 19, 2022 at 2:36 AM Marc Zyngier wrote:
>
> On Sat, 17 Sep 2022 02:06:00 +0100,
> Reiji Watanabe wrote:
> >
> > Add a test case for KVM_GUESTDBG_SINGLESTEP to the debug-exceptions test.
> > The test enables single-step execution from userspace, a
always reproduce the problem that the previous patch fixes
on an Ampere Altra machine.
Signed-off-by: Reiji Watanabe
---
.../selftests/kvm/aarch64/debug-exceptions.c | 131 ++
1 file changed, 131 insertions(+)
diff --git a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c
b
is not used for the next guest entry).
With this patch, GET_ONE_REG/SET_ONE_REG will get/set the guest's
preserved value, which KVM will preserve and try to restore after
single-step is disabled.
Fixes: 337b99bf7edf ("KVM: arm64: guest debug, add support for single-step")
Signed-off
g" to make DBG_SS_ACTIVE_PENDING
and PSTATE.SS consistent [Marc]
- Add a fix to preserve PSTATE.SS for the guest.
v1: https://lore.kernel.org/all/20220909044636.1997755-1-rei...@google.com/
Reiji Watanabe (4):
KVM: arm64: Preserve PSTATE.SS for the guest while single-step is
enabled
.
Fixes: 337b99bf7edf ("KVM: arm64: guest debug, add support for single-step")
Signed-off-by: Reiji Watanabe
---
arch/arm64/include/asm/kvm_host.h | 3 +++
arch/arm64/kvm/debug.c| 22 +-
arch/arm64/kvm/guest.c| 1 +
arch/arm64/kvm/handle_exit.c
Split up the current test into a helper, but leave the debug version
checking in main(), to make it convenient to add a new debug exception
test case in a subsequent patch.
Signed-off-by: Reiji Watanabe
---
.../selftests/kvm/aarch64/debug-exceptions.c | 18 ++
1 file changed
Hi Alex,
On 11/17/21 7:38 AM, Alexandru Elisei wrote:
Unpin the backing pages mapped at stage 2 after the stage 2 translation
tables are destroyed.
Signed-off-by: Alexandru Elisei
---
arch/arm64/kvm/mmu.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff -
for the source
code comments of arm64_check_features(), which I will fix in v2.
On Mon, Oct 18, 2021 at 11:25 PM Andrew Jones wrote:
>
> On Mon, Oct 18, 2021 at 03:59:35PM -0700, Reiji Watanabe wrote:
> > > > > > +int arm64_check_features(u32 sys_reg, u64 val, u64 limit)
> >
> > > > +static void reset_id_reg(struct kvm_vcpu *vcpu, const struct
> > > > sys_reg_desc *rd)
> > >
> > > Since not all ID registers will use this, then maybe name it
> > > reset_sanitised_id_reg?
> >
> > Thank you for the suggestion.
> >
> > I named it 'reset_id_reg' according to the naming con
> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -263,6 +263,76 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu,
> > return read_zero(vcpu, p);
> > }
> >
> > +struct id_reg_info {
> > + u32 sys_reg;/* Register ID */
> > + u64 sys
On Fri, Oct 15, 2021 at 6:09 AM Andrew Jones wrote:
>
> On Mon, Oct 11, 2021 at 09:35:12PM -0700, Reiji Watanabe wrote:
> > Extend sys_regs[] of kvm_cpu_context for ID registers and save ID
> > registers' sanitized value in the array for the vCPU at the first
> > v
Hi Andrew,
On Fri, Oct 15, 2021 at 3:13 AM Andrew Jones wrote:
>
> On Mon, Oct 11, 2021 at 09:35:11PM -0700, Reiji Watanabe wrote:
> > Introduce 'has_reset_once' flag in kvm_vcpu_arch, which indicates
> > if the vCPU reset has been done once, for later use.
> >
ols/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -18,6 +18,7 @@ HAS_CRC32
> HAS_DCPODP
> HAS_DCPOP
> HAS_E0PD
> +HAS_ECV2
> HAS_EPAN
> HAS_GENERIC_AUTH
> HAS_GENERIC_AUTH_ARCH
> --
Reviewed-by: Reiji Watanabe
Personally, I would prefer a more descriptive name (e.g. ECV_PH
ton wrote:
> > > > On Thu, Sep 30, 2021 at 11:05 PM Reiji Watanabe
> > > > wrote:
> > > > >
> > > > > On Thu, Sep 23, 2021 at 12:16 PM Oliver Upton
> > > > > wrote:
> > > > > >
> > > > > >
Make ID registers that don't have id_reg_info writable.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 71cfd62f9c85..2c092136cdff 100644
--- a
atches will add the feature_config_ctrl for several features.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c | 117 ++
1 file changed, 117 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 536e313992d4..55c5
: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c | 98 +--
1 file changed, 94 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 2c092136cdff..536e313992d4 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm
This patch adds id_reg_info for ID_AA64ISAR0_EL1 to make it writable
by userspace.
Updating sm3, sm4, sha1, sha2 and sha3 fields are allowed only
if values of those fields follow Arm ARM.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c | 31 +++
1 file
-off-by: Reiji Watanabe
---
arch/arm64/include/asm/kvm_arm.h | 16
arch/arm64/kvm/arm.c | 5 -
arch/arm64/kvm/hyp/vhe/switch.c | 14 ++
3 files changed, 22 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64
This patch adds id_reg_info for ID_AA64ISAR1_EL1 to make it
writable by userspace.
Return an error if userspace tries to set PTRAUTH related fields
of the register to values that conflict with PTRAUTH configuration
for the guest (via KVM_ARM_VCPU_INIT).
Signed-off-by: Reiji Watanabe
---
arch
Introduce a new capability KVM_CAP_ARM_ID_REG_WRITABLE to indicate
that ID registers are writable by userspace.
Signed-off-by: Reiji Watanabe
---
Documentation/virt/kvm/api.rst | 8
arch/arm64/kvm/arm.c | 1 +
include/uapi/linux/kvm.h | 1 +
3 files changed, 10
This patch adds id_reg_info for ID_AA64PFR1_EL1 to make it writable
by userspace.
Return an error if userspace tries to set MTE field of the register
to a value that conflicts with KVM_CAP_ARM_MTE configuration for
the guest.
Signed-off-by: Reiji Watanabe
---
arch/arm64/include/asm/sysreg.h
Add feature_config_ctrl for PMUv3, PMS and TraceFilt, which are
indicated in ID_AA64DFR0_EL1, to program configuration registers
to trap guest's using those features when they are not exposed to
the guest.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c
Add feature_config_ctrl for PTRAUTH, which is indicated in
ID_AA64ISAR1_EL1, to program configuration register to trap
guest's using the feature when it is not exposed to the guest.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c | 41 +++
1
Introduce a test for aarch64 to validate basic behavior of
KVM_GET_ONE_REG and KVM_SET_ONE_REG for ID registers.
This test runs only when KVM_CAP_ARM_ID_REG_WRITABLE is supported.
Signed-off-by: Reiji Watanabe
---
tools/arch/arm64/include/asm/sysreg.h |1 +
tools/testing/selftests
breakpoints according to Arm ARM, return an error
if userspace tries to set CTX_CMPS field to such value.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c | 108 ++
1 file changed, 97 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b
Call kvm_vcpu_id_regs_trap_activate() at the first KVM_RUN
to activate trapping of disabled CPU features.
Signed-off-by: Reiji Watanabe
---
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/kvm/arm.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm64/include/asm
sible), a visibility
function for RAS registers is not added.
No code is added for AMU's access/visibility handler because the
current code already injects the exception for Guest's AMU register
access unconditionally because AMU is never exposed to the guest.
Signed-off-by: Reiji Watanabe
This patch adds id_reg_info for ID_DFR0_EL1 to make it writable
by userspace.
Return an error if userspace tries to set PerfMon field of the
register to a value that conflicts with the PMU configuration.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c | 57
Add feature_config_ctrl for MTE, which is indicated in
ID_AA64PFR1_EL1, to program configuration register to trap the
guest's using the feature when it is not exposed to the guest.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c | 15 +++
1 file changed, 15 inser
register
to a value that conflicts with SVE configuration for the guest (via
KVM_ARM_VCPU_INIT). SIMD/FP/SVE fields of the requested value are
validated according to Arm ARM.
Signed-off-by: Reiji Watanabe
---
arch/arm64/include/asm/kvm_host.h | 3 -
arch/arm64/kvm/arm.c | 18
ailability.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 23a3bcac4986..68df4e4eba05 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch
.
No ID register has the structure yet and the following patches
will add the id_reg_info for some ID registers.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c | 120 +++---
1 file changed, 111 insertions(+), 9 deletions(-)
diff --git a/arch/arm6
: Reiji Watanabe
---
arch/arm64/include/asm/kvm_arm.h | 16
arch/arm64/kvm/arm.c | 1 +
arch/arm64/kvm/debug.c | 13 -
3 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm
value of ID register for a vCPU that already
started KVM_RUN once.
Changing ID register is still not allowed at present though.
Signed-off-by: Reiji Watanabe
---
arch/arm64/include/asm/kvm_host.h | 2 ++
arch/arm64/kvm/arm.c | 3 +++
arch/arm64/kvm/sys_regs.c | 31
valid combinations.
Signed-off-by: Reiji Watanabe
---
arch/arm64/kvm/sys_regs.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 84c064dfc63a..71cfd62f9c85 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b
ttps://lore.kernel.org/kvm/20201102033422.657391-1-liangpen...@huawei.com/
[3] https://lore.kernel.org/kvmarm/20211007233439.1826892-1-rana...@google.com/
Reiji Watanabe (25):
KVM: arm64: Add has_reset_once flag for vcpu
KVM: arm64: Save ID registers' sanitized value per vCPU
KVM: arm64:
Extend sys_regs[] of kvm_cpu_context for ID registers and save ID
registers' sanitized value in the array for the vCPU at the first
vCPU reset. Use the saved ones when ID registers are read by
userspace (via KVM_GET_ONE_REG) or the guest.
Signed-off-by: Reiji Watanabe
---
arch/arm64/includ
n
the host.
Signed-off-by: Reiji Watanabe
---
arch/arm64/include/asm/cpufeature.h | 1 +
arch/arm64/kernel/cpufeature.c | 26 ++
2 files changed, 27 insertions(+)
diff --git a/arch/arm64/include/asm/cpufeature.h
b/arch/arm64/include/asm/cpufeature.h
index ef6be92
Introduce 'has_reset_once' flag in kvm_vcpu_arch, which indicates
if the vCPU reset has been done once, for later use.
Signed-off-by: Reiji Watanabe
---
arch/arm64/include/asm/kvm_host.h | 2 ++
arch/arm64/kvm/reset.c| 4
2 files changed, 6 insertions(+)
diff --
; -*/
> - smp_wmb();
> -
> - vcpu->arch.power_off = false;
> + kvm_psci_vcpu_request_reset(vcpu, smccc_get_arg2(source_vcpu),
> + smccc_get_arg3(source_vcpu),
> + kvm_vcpu_is_be(sou
ons.
>
> Signed-off-by: Oliver Upton
Looks nice.
Reviewed-by: Reiji Watanabe
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On Thu, Sep 23, 2021 at 12:16 PM Oliver Upton wrote:
>
> The helper function does not need a pointer to the vCPU, as it only
> consults a constant mask; drop the unused vcpu parameter.
>
> Signed-off-by: Oliver Upton
Reviewed-by:
Hi Oliver,
I have additional questions/comments.
> > +2.2. ATTRIBUTE: KVM_ARM_VCPU_TIMER_PHYS_OFFSET
> > +-
> > +
> > +:Parameters: in kvm_device_attr.addr the address for the timer offset is a
> > + pointer to a __u64
> > +
> > +Returns:
> > +
Hi Oliver,
On Thu, Sep 16, 2021 at 11:15 AM Oliver Upton wrote:
>
> Presently, KVM provides no facilities for correctly migrating a guest
> that depends on the physical counter-timer. While most guests (barring
> NV, of course) should not depend on the physical counter-timer, an
> operator may wi
u32 host_timer_irq;
> u32 host_timer_irq_flags;
> +
> + /* offset relative to the host's physical counter-timer */
> + u64 host_offset;
> };
Just out of curiosity, have you c
of the calling vcpu. The interface is architecture
> independent, but defined only for arm64 as of now.
>
> Suggested-by: Reiji Watanabe
> Signed-off-by: Raghavendra Rao Ananta
> Reviewed-by: Ricardo Koller
Reviewed-by: Reiji Watanabe
Thank yo
Hi Raghu and all,
On Wed, Sep 8, 2021 at 6:38 PM Raghavendra Rao Ananta
wrote:
>
> At times, such as when in the interrupt handler, the guest wants
> to get the vcpuid that it's running on. As a result, introduce
> get_vcpuid() that returns the vcpuid of the calling vcpu. At its
> backend, the VM
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