On Wed, Aug 29, 2018 at 1:35 PM, Andrey Konovalov wrote:
> KWHASAN uses 1 shadow byte for 16 bytes of kernel memory, so it requires
> 1/16th of the kernel virtual address space for the shadow memory.
>
> This commit sets KASAN_SHADOW_SCALE_SHIFT to 4 when KHWASAN is enabled.
>
> Signed-off-by: And
Signed-off-by: Guo Ren
---
.../bindings/interrupt-controller/csky,mpintc.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-contro
Changelog:
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Use clksource_mmio framework
Signed-off-by: Guo Ren
---
drivers/clocksource/timer-gx6605s.c | 150
1 file changed, 150 insertions(+)
create mode 100644
Signed-off-by: Guo Ren
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 7cad066..335f9e0 100644
--- a/Documentation/dev
Signed-off-by: Guo Ren
---
drivers/clocksource/Kconfig | 15 +++
drivers/clocksource/Makefile | 2 ++
2 files changed, 17 insertions(+)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index dec0dd8..6ff0a25 100644
--- a/drivers/clocksource/Kconfig
+++ b/drive
On Mon, Sep 10, 2018 at 7:43 PM Maxime Ripard wrote:
>
> On Sun, Sep 09, 2018 at 09:04:39PM +0200, Paul Kocialkowski wrote:
> > This makes it possible to build the sunxi SRAM driver without building
> > for the sunxi architecture. This allows selecting the driver when
> > building the kernel in te
The SC16IS752 has an Enhanced Feature Register which is aliased at the
same address as the Interrupt Identification Register; accessing it
requires that a magic value is written to the Line Configuration
Register. If an interrupt is raised while the EFR is mapped in then
the ISR won't be able to ac
This timer is used by SMP system and use mfcr/mtcr instruction
to access the regs.
Changelog:
- Support csky mp timer alpha version.
- Just use low-counter with 32bit width as clocksource.
- Coding convention with upstream feed-back.
Signed-off-by: Guo Ren
---
drivers/clocksource/csky_mptime
The SC16IS752 is a dual-channel device. The two channels are largely
independent, but the IRQ signals are wired together as an open-drain,
active low signal which will be driven low while either of the
channels requires attention, which can be for significant periods of
time until operations comple
The interrupt handling of the sc16is7xx driver is broken in a number of ways,
as observed by multiple Raspberry Pi users. The attached patches attempt to
address its failings, with apparent success.
The first is a workaround for a side-effect of the switch away from using a
thread IRQ, a change wh
Signed-off-by: Guo Ren
---
arch/csky/include/asm/uaccess.h | 398
arch/csky/lib/usercopy.c| 271 +++
2 files changed, 669 insertions(+)
create mode 100644 arch/csky/include/asm/uaccess.h
create mode 100644 arch/csky/lib/us
Signed-off-by: Guo Ren
---
.../interrupt-controller/csky,apb-intc.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-cont
Signed-off-by: Guo Ren
---
arch/csky/include/asm/smp.h | 26 +
arch/csky/kernel/smp.c | 234
2 files changed, 260 insertions(+)
create mode 100644 arch/csky/include/asm/smp.h
create mode 100644 arch/csky/kernel/smp.c
diff --git a/arch/csky
Signed-off-by: Guo Ren
---
arch/csky/include/asm/bug.h | 26 +++
arch/csky/include/uapi/asm/ptrace.h | 103
arch/csky/kernel/dumpstack.c| 64
arch/csky/kernel/ptrace.c | 317
4 files changed, 510 insertions(+)
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/reg_ops.h | 26 +++
arch/csky/abiv1/inc/abi/regdef.h | 25 +++
arch/csky/abiv2/inc/abi/reg_ops.h | 17 ++
arch/csky/abiv2/inc/abi/regdef.h | 26 +++
arch/csky/boot/dts/qemu.dts| 77 +
arch/csky/inclu
Signed-off-by: Guo Ren
---
.../bindings/timer/csky,gx6605s-timer.txt | 42 ++
1 file changed, 42 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.
Signed-off-by: Guo Ren
---
arch/csky/abiv1/bswapdi.c| 18 ++
arch/csky/abiv1/bswapsi.c| 14 ++
arch/csky/abiv1/inc/abi/string.h | 13 ++
arch/csky/abiv1/memcpy.S | 344 +++
arch/csky/abiv1/memset.c | 37 +
arch/csky/abiv1
Signed-off-by: Guo Ren
---
arch/csky/include/asm/elf.h | 149
arch/csky/kernel/module.c | 82
2 files changed, 231 insertions(+)
create mode 100644 arch/csky/include/asm/elf.h
create mode 100644 arch/csky/kernel/module.c
Signed-off-by: Guo Ren
---
arch/csky/include/asm/atomic.h | 215 +
arch/csky/include/asm/cmpxchg.h| 70
arch/csky/include/asm/spinlock.h | 286 +
arch/csky/include/asm/spinlock_types.h | 35
arch/csky/ke
On 9/12/2018 4:49 AM, Sudeep Holla wrote:
On 11/09/18 21:38, Jeffrey Hugo wrote:
On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
[..]
If you look at the next line of code following this comment its going
to update the cache type for fully populated PPTT nodes. Although
From: Richard Henderson
For ease of disabling this feature, split the actual enabling into its
own patch.
Signed-off-by: Richard Henderson
Signed-off-by: Matthew Wilcox
---
arch/x86/include/asm/percpu.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/include/asm/percpu.h b/
From: Richard Henderson
GCC 6 adds support for __seg_fs and __seg_gs as named address spaces,
producing the obvious segment overrides for objects so marked.
Exposing the memory reference allows slightly better code generation
in some cases (and in others, merely affects the scheduling). E.g.:
rth wrote a patch back in 2016 that uses gcc's address space machinery
to improve code generation for percpu accesses. Ingo asked for some
minor changes to be made, but Richard didn't respond. While looking at
something related, I came across them, and asked Richard's permission
to resurrect and
A couple drivers were accessing the region struct after it had been
freed. Save off the pointer to the mgr before the region struct gets
freed.
Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
---
drivers/fpga/dfl-fme-region.c | 4 +++-
drivers/fpga/of-fpga-region.c | 3 ++-
2 files changed,
Add flags #defines to kerneldoc documentation in a
useful place.
Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
---
Documentation/driver-api/fpga/fpga-mgr.rst | 5 +
include/linux/fpga/fpga-mgr.h | 20 ++--
2 files changed, 19 insertions(+), 6 deletions(-)
fpga_bridge_dev_match() returns a FPGA bridge struct, not a
FPGA manager struct so s/manager/bridge/.
Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
---
drivers/fpga/fpga-bridge.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fp
From: Moritz Fischer
Use platform_set_drvdata rather than dev_set_drvdata
to match the platform_get_drvdata in the _remove()
function of the platform driver.
Signed-off-by: Moritz Fischer
Acked-by: Alan Tull
---
drivers/fpga/of-fpga-region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
From: Moritz Fischer
Use platform_get_drvdata() in remove() function of
the platform driver rather than dev_get_drvdata()
to match the platform_set_drvdata in the probe().
Signed-off-by: Moritz Fischer
Acked-by: Alan Tull
---
drivers/fpga/dfl-fme-region.c | 2 +-
1 file changed, 1 insertion(+
Hi Greg,
Please take these five small patches for FPGA. They
have been reviewed on the mailing lists and apply cleanly
on linux-next/master and char-misc-testing.
Thanks,
Alan
Alan Tull (3):
fpga: do not access region struct after fpga_region_unregister
fpga: bridge: fix obvious function do
On 2018-09-12 18:47, Michal Hocko wrote:
On Wed 12-09-18 22:57:43, Balbir Singh wrote:
On Wed, Sep 12, 2018 at 12:38:53PM +0200, Michal Hocko wrote:
> On Wed 12-09-18 14:56:45, Arun KS wrote:
> > When free pages are done with pageblock_order, time spend on
> > coalescing pages by buddy allocator
On 9/11/2018 3:25 PM, Jeremy Linton wrote:
Hi,
On 09/11/2018 03:38 PM, Jeffrey Hugo wrote:
On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
On 09/11/2018 02:32 PM, Jeffrey Hugo wrote:
The type of a cache might not be specified by architectural
mechanisms (ie
system registers
On 9/12/18 10:27 AM, Gerald Schaefer wrote:
> On Wed, 12 Sep 2018 15:39:33 +0200
> Michal Hocko wrote:
>
>> On Wed 12-09-18 15:03:56, Gerald Schaefer wrote:
>> [...]
>>> BTW, those sysfs attributes are world-readable, so anyone can trigger
>>> the panic by simply reading them, or just run lsmem
Currently, /proc/cpuinfo show logical CPU ID as Hart ID which
is in-correct. This patch shows CPU ID and Hart ID separately
in /proc/cpuinfo using cpuid_to_hardid_map().
With this patch, contents of /proc/cpuinfo looks as follows:
cpu : 0
hart: 1
isa : rv64imafdcsu
mmu : sv48
cpu
On 2018/9/4 0:59, Will Deacon wrote:
> On Thu, Aug 09, 2018 at 10:20:39PM +0800, zhong jiang wrote:
>> There are some extra semicolon in arm64 architecture. Just remove them.
> These are trivial but certainly not urgent, so I guess Catalin can pick
> them up for 4.20.
Thanks,
Catalin, Do you ca
This patch provides arch_show_interrupts() implementation to
show IPI stats via /proc/interrupts.
Now the contents of /proc/interrupts" will look like below:
CPU0 CPU1 CPU2 CPU3
8: 17 7 6 14 SiFive PLIC 8 virtio0
10: 10
On Tue, 11 Sep 2018 22:23:55 +0200
Remi Pommarel wrote:
> This patchset adds a way to have a specific keyboard config (i.e.
> keycode to keysym map) for a vt attached input.
Who actually needs this given that you can't even render most
international symbols in text mode and X and friends already
On Wed, Sep 12, 2018 at 3:25 PM Guo Ren wrote:
>
> This is the 3th version patchset to add the Linux kernel port for C-SKY(csky).
> Thanks to everyone who provided feedback on the previous version.
>
> This patchset adds architecture support to Linux for C-SKY's 32-bit embedded
> CPU cores and the
On Wed, 12 Sep 2018, Florian Weimer wrote:
> On 09/12/2018 04:17 PM, Thomas Gleixner wrote:
> > On Wed, 12 Sep 2018, Florian Weimer wrote:
> > > Does this mean glibc can keep using a single vDSO entrypoint, the one we
> > > have today?
> >
> > We have no intention to change that.
>
> Okay, I was
On Mon, 10 Sep 2018 15:26:55 +
Pasha Tatashin wrote:
>
> I agree memoryblock is a hack, it fails to do both things it was
> designed to do:
>
> 1. On bare metal you cannot free a physical dimm of memory using
> memoryblock granularity because memory devices do not equal to physical
> dimms.
On Wed, 12 Sep 2018 15:39:33 +0200
Michal Hocko wrote:
> On Wed 12-09-18 15:03:56, Gerald Schaefer wrote:
> [...]
> > BTW, those sysfs attributes are world-readable, so anyone can trigger
> > the panic by simply reading them, or just run lsmem (also available for
> > x86 since util-linux 2.32). O
When producing memory snapshot image, hibernation uses HMAC-SHA512
with snapshot key (from TPM trusted key) to calculate the hash of
all data pages in snapshot image. The hash result will be kept in the
snapshot header as the image signature. Before hibernation restores
image, kernel executes HMAC-
Hi,
We are waiting for your photos.
Please send photos to hansre...@outlook.com for further editing.
Our team is ready to edit your photos. Do you have photos for editing?
We are team who can do following work for you.
Cutting out your photos, or retouching if needed.
It is for products photos
This kernel option is similar to the option for kernel module signature
verification. When this option is unselected, kernel will be tainted by
restored from a snapshot image without (valid) signature.
When the option is selected, kernel will refuse the system to be restored
from a unauthenticated
If the encryption key be guessed then the snapshot master key can
also be grabbed from snapshot image. Which means that the authentication
key can also be calculated. So kernel erases master key in snapshot
pages.
Because the master key in image kernel be erased, kernel uses the
trampoline page to
To protect the secret in memory snapshot image, this patch adds the
logic to encrypt snapshot pages by AES-CTR. Using AES-CTR is because
it's simple, fast and parallelizable. But this patch didn't implement
parallel encryption.
The encrypt key is derived from the snapshot key. And the initializati
On Tue, 11 Sep 2018, Paul E. McKenney wrote:
> > I think what you meant to write in the second and third sentences was
> > something more like this:
> >
> > Any code in an RCU critical section that extends beyond the
> > end of a given RCU grace period is guaranteed to see the
> >
From: Liu Song
Although the 'need_to_create_worker' has been determined to be
true before entering the function. However, adjusting the order
of judgment can combine two judgments in the loop. Also improve
the matching between logical operations and function naming.
Signed-off-by: Liu Song
---
Hi,
This patchset is the implementation of encryption and authentication
for hibernate snapshot image. The image will be encrypted by AES and
authenticated by HMAC.
The hibernate function can be used to snapshot memory pages to an image,
then kernel restores the image to memory space in a appropr
This patch adds a snapshot keys handler for using the key retention
service api to create keys for snapshot image encryption and
authentication.
This handler uses TPM trusted key as the snapshot master key, and the
encryption key and authentication key are derived from the snapshot
key. The user d
On 09/12, Oleg Nesterov wrote:
>
> it's pity. cause this means I will have to actually test this change and
> (worse) write the changelog ;)
Seems to work, see v2 below, I tried to address your comments.
The new helper is prepare_arg_pages(), matches setup_arg_pages/shift_arg_pages.
s/p_min/argm
debugfs_remove_recursive has taken IS_ERR_OR_NULL into account. So just
remove the condition check before debugfs_remove_recursive.
Signed-off-by: zhong jiang
---
drivers/net/wireless/broadcom/brcm80211/brcmsmac/debug.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/driver
On Wed, Sep 12, 2018 at 3:25 PM Guo Ren wrote:
>
> Signed-off-by: Guo Ren
> diff --git a/arch/csky/boot/dts/qemu.dts b/arch/csky/boot/dts/qemu.dts
> new file mode 100644
> index 000..c6643b1
> --- /dev/null
> +++ b/arch/csky/boot/dts/qemu.dts
> @@ -0,0 +1,77 @@
Did you consider renaming the
On Wed 12-09-18 09:54:17, Andrea Arcangeli wrote:
> Hello,
>
> On Tue, Sep 11, 2018 at 01:56:13PM +0200, Michal Hocko wrote:
> > Well, it seems that expectations differ for users. It seems that kvm
> > users do not really agree with your interpretation.
>
> Like David also mentioned here:
>
> lk
On 09/12/2018 04:17 PM, Thomas Gleixner wrote:
On Wed, 12 Sep 2018, Florian Weimer wrote:
On 09/09/2018 10:05 PM, Thomas Gleixner wrote:
See the patch below. It's integrating TAI without slowing down everything
and it definitely does not result in indirect calls.
On a HSW it slows down clock_g
On 09-Sep 11:52, Suren Baghdasaryan wrote:
> On Tue, Aug 28, 2018 at 6:53 AM, Patrick Bellasi
> wrote:
[...]
> > +/**
> > + * release_uclamp_sched_group: release utilization clamp references of a TG
>
> free_uclamp_sched_group
+1
> > + * @tg: the task group being removed
> > + *
> > + * An em
On 12/09/2018 15:33, Sebastian Andrzej Siewior wrote:
> From: Rik van Riel
>
> While most of a task's FPU state is only needed in user space,
> the protection keys need to be in place immediately after a
> context switch.
>
> The reason is that any accesses to userspace memory while running
> in
On Wed, 12 Sep 2018, Florian Weimer wrote:
> On 09/09/2018 10:05 PM, Thomas Gleixner wrote:
> > See the patch below. It's integrating TAI without slowing down everything
> > and it definitely does not result in indirect calls.
> >
> > On a HSW it slows down clock_gettime() by ~0.5ns. On a SKL I ge
Hello Michal and Balbir,
Thanks for reviewing.
On 2018-09-12 18:27, Balbir Singh wrote:
On Wed, Sep 12, 2018 at 12:38:53PM +0200, Michal Hocko wrote:
On Wed 12-09-18 14:56:45, Arun KS wrote:
> When free pages are done with pageblock_order, time spend on
> coalescing pages by buddy allocator ca
Am Mittwoch, 12. September 2018, 10:22:44 CEST schrieb Manivannan Sadhasivam:
> On Wed, Sep 12, 2018 at 09:26:12AM +0200, Heiko Stübner wrote:
> > Am Mittwoch, 12. September 2018, 05:12:48 CEST schrieb Manivannan
> > Sadhasivam:
> > > Hi Ezequiel,
> > >
> > > On Tue, Sep 11, 2018 at 04:40:29PM -0
On Wed, Sep 12, 2018 at 7:29 AM Martin Schwidefsky
wrote:
> On Tue, 11 Sep 2018 22:26:54 +0200 Arnd Bergmann wrote:
> > On Sun, Sep 9, 2018 at 6:12 AM Al Viro wrote:
> > Out of those, there are only a few that may get used on s390,
> > in particular at most infiniband/uverbs, nvme, nvdimm,
> >
* Sudeep Holla [180912 13:47]:
>
>
> On 12/09/18 14:32, Tony Lindgren wrote:
> > * Sudeep Holla [180912 11:41]:
> >> On 12/09/18 12:19, Keerthy wrote:
> >>> suspend to mem and suspend to disk are pretty generic states and i agree
> >>> implementation is platform dependent so why not have proper
Hi Thomas,
On Thu, Aug 30, 2018 at 5:06 PM Thomas Gleixner wrote:
> Commit 0a0e0829f990 ("nohz: Fix missing tick reprogram when interrupting an
> inline softirq") got backported to stable trees and now causes the NOHZ
> softirq pending warning to trigger. It's not an upstream issue as the NOHZ
>
On Wed, Sep 12, 2018 at 01:58:39PM +0530, Viresh Kumar wrote:
> Hello,
>
> Niklas Cassle recently reported some regressions with his Qcom cpufreq
> driver where he was getting some errors while creating the OPPs tables.
>
> After looking into it I realized that the OPP core incorrectly creates
> mu
While we updated the coresight DT bindings, some of the
new examples were not updated due to the order in which they
were merged. Let us update all the missed out ones to the
new bindings to avoid confusion.
Cc: Mathieu Poirier
Cc: Rob Herring
Cc: Frank Rowand
Signed-off-by: Suzuki K Poulose
-
Switch to the new hardware port bindings for coresight
Cc: Andy Gross
Cc: David Brown
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 71 ++-
arch/arm/boot/dts/qcom-msm8974.dtsi | 104 +++-
2 files changed,
Switch to the new the hardware port bindings.
Cc: Wei Xu
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/hip04.dtsi | 346 ++-
1 file changed, 176 insertions(+), 170 deletions(-)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boo
Switch to the new coresight bindings for hardware ports
Cc: Nicolas Ferre
Cc: Alexandre Belloni
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/sama5d2.dtsi | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/sama5
Hello,
On Tue, Sep 11, 2018 at 01:56:13PM +0200, Michal Hocko wrote:
> Well, it seems that expectations differ for users. It seems that kvm
> users do not really agree with your interpretation.
Like David also mentioned here:
lkml.kernel.org/r/alpine.deb.2.21.1808211021110.258...@chino.kir.corp.
Switch to the new coresight bindings for hardware ports
Cc: linux-o...@vger.kernel.org
Cc: "Benoît Cousson"
Cc: Tony Lindgren
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/omap3-beagle-xm.dts | 17 ++---
arch/arm/boot/dts/omap3-beagle.dts| 17 ++
Switch to the new coresight bindings
Cc: Linus Walleij
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/ste-dbx5x0.dtsi | 65 ---
1 file changed, 33 insertions(+), 32 deletions(-)
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi
b/arch/arm/b
Switch to updated coresight bindings for hw ports
Cc: Andy Gross
Cc: David Brown
Cc: Ivan T. Ivanov
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v1:
- Fixed TPIU port direction
- Use better subject tag for the patch
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 95 ++
Switch to the updated coresight bindings.
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/imx7d.dtsi | 14 +++---
arch/arm/boot/dts/imx7s.dtsi | 82
2
Switch to the new coresight bindings for hw ports
Cc: orsonz...@gmail.com
Cc: zhang.l...@gmail.com
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm64/boot/dts/sprd/sc9836.dtsi | 82 +-
arch/arm64/boot/dts/sprd/sc9860.dtsi | 215 ++-
2 files chang
TPIU component has an input port. The example uses out-ports
which is wrong. Let us fix it.
Reported-by: Leo Yan
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Documentation/devicetree/bindings/arm/coresight.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Docum
Switch to updated coresight bindings for hw ports.
Cc: xuw...@hisilicon.com
Cc: lipengche...@huawei.com
Cc: Mathieu Poirier
Tested-by: Leo Yan
Signed-off-by: Suzuki K Poulose
---
.../boot/dts/hisilicon/hi6220-coresight.dtsi | 181 +-
1 file changed, 86 insertions(+), 95 deleti
Coresight DT bindings have been updated to obey the DTS rules
for label/address matching for graph nodes. The changes are in
coresight/next tree scheduled for v4.20. This series updates the
in kernel dts to match the new bindings along with updating a couple
of new examples (e.,g CATU) in the Docum
Hi Ben,
>> From: Fabio Estevam
>>
>> [ Upstream commit 157bcc06094c3c5800d3f4676527047b79b618e7 ]
>>
>> Select CONFIG_USB_CHIPIDEA_ULPI and CONFIG_USB_ULPI_BUS so that
>> USB ULPI can be functional on some boards like imx51-babbge.
> [...]
>
> CONFIG_USB_CHIPIDEA_ULPI doesn't exist in 4.4 or 4.9,
On Wed 12-09-18 17:19:20, Li RongQing wrote:
> memory.force_empty is used to empty a memory cgoup memory before
> rmdir it, avoid to charge those memory into parent cgroup
We do not reparent LRU pages on the memcg removal. We just keep
those pages around and reclaim them on the memory pressure. So
On Tue, Aug 28, 2018 at 02:53:10PM +0100, Patrick Bellasi wrote:
> +/**
> + * Utilization's clamp group
> + *
> + * A utilization clamp group maps a "clamp value" (value), i.e.
> + * util_{min,max}, to a "clamp group index" (group_id).
> + */
> +struct uclamp_se {
> + unsigned int value;
> +
On 12/09/18 14:32, Tony Lindgren wrote:
> * Sudeep Holla [180912 11:41]:
>> On 12/09/18 12:19, Keerthy wrote:
>>> suspend to mem and suspend to disk are pretty generic states and i agree
>>> implementation is platform dependent so why not have properties that
>>> convey if they are supported?
>
Convert the remaining files to SPDX license description.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/ap806-system-controller.c | 4 +---
drivers/clk/mvebu/armada-370.c | 4 +---
drivers/clk/mvebu/armada-375.c | 4 +---
drivers/clk/mvebu/armada-37xx-tbg.c
Hi Sean:
Thanks for your review.
On 9/10/2018 10:21 PM, Sean Christopherson wrote:
> On Mon, 2018-09-10 at 08:38 +, Tianyu Lan wrote:
>> Add flush range call back in the kvm_x86_ops and platform can use it
>> to register its associated function. The parameter "kvm_tlb_range"
>> accepts
On Wed 12-09-18 15:03:56, Gerald Schaefer wrote:
[...]
> BTW, those sysfs attributes are world-readable, so anyone can trigger
> the panic by simply reading them, or just run lsmem (also available for
> x86 since util-linux 2.32). OK, you need a special not-memory-block-aligned
> mem= parameter and
From: Rik van Riel
While most of a task's FPU state is only needed in user space,
the protection keys need to be in place immediately after a
context switch.
The reason is that any accesses to userspace memory while running
in kernel mode also need to abide by the memory permissions
specified in
From: Rik van Riel
If TIF_LOAD_FPU is set, then the registers are saved (not loaded). In that case
we skip the saving part.
Signed-off-by: Rik van Riel
Signed-off-by: Sebastian Andrzej Siewior
---
arch/x86/kernel/fpu/signal.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletion
From: Rik van Riel
Add helper function that ensures the floating point registers for
the current task are active. Use with preemption disabled.
Signed-off-by: Rik van Riel
Signed-off-by: Sebastian Andrzej Siewior
---
arch/x86/include/asm/fpu/internal.h | 27 ++-
1 file
From: Rik van Riel
The fpu->initialized flag should not be changed underneath us. This might be a
fallout during the removal of the LazyFPU support. The FPU is marked
initialized as soon as the state has been set to an initial value. It does not
signal if the CPU's FPU registers are loaded.
Sign
Add TIF_LOAD_FPU. This is reserved for loading the FPU registers before
returning to userpace. It is introduced now, so we can add code handling
it now before adding the main feature.
Signed-off-by: Sebastian Andrzej Siewior
---
arch/x86/include/asm/thread_info.h | 2 ++
1 file changed, 2 insert
From: Rik van Riel
copy_fpstate_to_sigframe() has two callers and both invoke the function only if
fpu->initialized is set. So the check in the function for ->initialized makes
no sense. It might be a relict from the lazy-FPU time: If the FPU registers
were "loaded" then we would could save them
From: Rik van Riel
If the FPU state is not loaded in registers at fork time, memcpy the
fpstate from the parent task to the child task.
Signed-off-by: Rik van Riel
Signed-off-by: Sebastian Andrzej Siewior
---
arch/x86/kernel/fpu/core.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions
From: Rik van Riel
Defer loading of FPU state until return to userspace. This gives
the kernel the potential to skip loading FPU state for tasks that
stay in kernel mode, or for tasks that end up with repeated
invocations of kernel_fpu_begin.
It also increases the chances that a task's FPU state
There is no user of _TIF_ALLWORK_MASK since commit 21d375b6b34ff
("x86/entry/64: Remove the SYSCALL64 fast path").
Remove unused define _TIF_ALLWORK_MASK.
Signed-off-by: Sebastian Andrzej Siewior
---
arch/x86/include/asm/thread_info.h | 8
1 file changed, 8 deletions(-)
diff --git a/ar
The functions
kvm_load_guest_fpu()
kvm_put_guest_fpu()
are only used locally, make them static. This requires also that both
functions are moved because they are used before their implementation.
Those functions were exported (via EXPORT_SYMBOL) before commit
e5bb40251a920 ("KVM: D
This is a refurbished series originally started by by Rik van Riel. The
goal is load the FPU registers on return to userland and not on every
context switch. By this optimisation we can:
- avoid loading the registers if the task stays in kernel and does
not return to userland
- make kernel_fpu_be
On Wed 2018-09-12 16:49:30, Sergey Senozhatsky wrote:
> On (09/11/18 10:47), Petr Mladek wrote:
> > > > Most problems should probably be solved when we store console_seq
> > > > before setting exclusive_console. Then we could clear
> > > > exclusive_console when reaching the stored sequence number.
Hi Peter,
Any comments for the patch series regarding to v4 PMI handler?
Thanks,
Kan
On 8/8/2018 3:12 AM, kan.li...@linux.intel.com wrote:
From: Andi Kleen
Implements counter freezing for Arch Perfmon v4 (Skylake and
newer). This allows to speed up the PMI handler by avoiding
unnecessary MSR
Hi Michael:
Thanks for your review.
On 9/12/2018 8:22 AM, Michael Kelley (EOSG) wrote:
> From: Tianyu Lan Sent: Monday, September 10, 2018 1:39 AM
>> +
>> +int hyperv_flush_guest_mapping_range(u64 as, struct kvm_tlb_range *range)
>
> I'm really concerned about defining the Hyper-V functi
* Sudeep Holla [180912 11:41]:
> On 12/09/18 12:19, Keerthy wrote:
> > suspend to mem and suspend to disk are pretty generic states and i agree
> > implementation is platform dependent so why not have properties that
> > convey if they are supported?
> >
>
> We already have power domains and idl
On 9/11/18 12:40 PM, Laurent Dufour wrote:
On 11/09/2018 02:42, Daniel Jordan wrote:
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index 32699b2dc52a..6d4c23a3069d 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -229,6 +229,12 @@ struct zone_reclaim_stat {
On 9/11/18 12:32 PM, Laurent Dufour wrote:
On 11/09/2018 02:42, Daniel Jordan wrote:
diff --git a/include/linux/memcontrol.h b/include/linux/memcontrol.h
index d99b71bc2c66..6377dc76dc41 100644
--- a/include/linux/memcontrol.h
+++ b/include/linux/memcontrol.h
@@ -99,7 +99,8 @@ struct mem_cgroup_
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