On Mon, Dec 3, 2018 at 11:07 AM Daniel Lezcano
wrote:
>
> On 18/10/2018 21:55, Daniel Lezcano wrote:
> > The SPDX tags are not present in cpufreq.c and cpufreq_schedutil.c.
> >
> > Add them and remove the license descriptions
> >
> > Signed-off-by: Daniel Lezcano
>
> Hi Rafael,
>
> I think this p
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3.
Add a compatible string for it with H3 fallback compatible string,
in this case the H3 driver can be used.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/media/sun6i-csi.txt | 1 +
1 fil
Most of the Allwinner A64 CSI controllers are supply with
VCC-PE pin. which need to supply for some of the boards to
trigger the power.
So, document the supply property as vcc-csi so-that the required
board can eable it via device tree.
Used vcc-csi instead of vcc-pe to have better naming convent
Amarula A64-Relic board by default bound with OV5640 camera,
so add support for it with below pin information.
- PE13, PE12 via i2c-gpio bitbanging
- CLK_CSI_MCLK as external clock
- PE1 as external clock pin muxing
- DLDO3 as vcc-csi supply
- DLDO3 as AVDD supply
- ALDO1 as DOVDD supply
- ELDO3 a
Most of the Allwinner A64 CSI controllers are supply with
VCC-PE pin, which may not be turned on by default.
Add support for such boards by adding voltage regulator handling
code to sun6i csi driver.
Used vcc-csi instead of vcc-pe to have better naming convention
wrt other controller pin supplies
Hi Vitor,
On Mon, 26 Nov 2018 09:45:14 +0100
Boris Brezillon wrote:
> Follow the naming scheme introduced by the Cadence driver to keep things
> consistent.
>
> Signed-off-by: Boris Brezillon
> ---
> drivers/i3c/master/Makefile | 2 +-
> drivers/i3c/master/{dw-i3c-
On 18/10/2018 21:55, Daniel Lezcano wrote:
> The SPDX tags are not present in cpufreq.c and cpufreq_schedutil.c.
>
> Add them and remove the license descriptions
>
> Signed-off-by: Daniel Lezcano
Hi Rafael,
I think this patch passed between the cracks.
-- Daniel
> ---
> kernel/sched/cpufre
On 03/12/2018 10:28, Xingyu Chen wrote:
>
>
> On 2018/12/3 17:19, Jerome Brunet wrote:
>> On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
>>> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
>>> other Meson SoCs, A totle of 100 pins can be spied on, which is the su
On Thu, 22 Nov 2018 18:11:15 +0100
Pierre Morel wrote:
> This is the implementation of the VFIO ioctl calls to handle
> the AQIC interception and use GISA to handle interrupts.
>
> Signed-off-by: Pierre Morel
> ---
> drivers/s390/crypto/vfio_ap_ops.c | 110
> ++
From: Michal Hocko
We have received a bug report that an injected MCE about faulty memory
prevents memory offline to succeed. The underlying reason is that the
HWPoison page has an elevated reference count and the migration keeps
failing. There are two problems with that. First of all it is dubio
On 03/12/2018 08:33, Peter Zijlstra wrote:
> On Sat, Dec 01, 2018 at 05:09:36PM +0800, Wen Yang wrote:
>> Fix the following warnings reported by coccinelle:
>> kernel//sched/fair.c:7958:3-12: WARNING: Assignment of bool to 0/1
>>
Duh, Patrick raised that one to me last week but I got caught up in
On 11/30/2018 8:45 PM, Jarkko Sakkinen wrote:
On Fri, Nov 30, 2018 at 11:41:49AM -0800, Jarkko Sakkinen wrote:
Even after looking at the spec the last field does not make sense as the
event after digests and digests are not in union. It is just not right.
The comment does not fix that.
You sh
Hi Fabrice,
On 10/3/18 4:41 PM, Fabrice Gasnier wrote:
This enables drivers for STM32 timer, low power timer and analog hardware
that can be used on STM32MP1 SoC:
- Timer & LP Timer MFD core, PWM, trigger & encoder drivers
- IIO ADC/DAC/DFSDM
- vrefbuf regu driver (voltage reference buffer).
Si
In order to make sure Energy Aware Scheduling (EAS) will not impact
systems where no Energy Model is available, introduce a static key
guarding the access to EAS code. Since EAS is enabled on a
per-root-domain basis, the static key is enabled when at least one root
domain meets all conditions for E
In its current state, Energy Aware Scheduling (EAS) starts automatically
on asymmetric platforms having an Energy Model (EM). However, there are
users who want to have an EM (for thermal management for example), but
don't want EAS with it.
In order to let users disable EAS explicitly, introduce a
***
* This patch illustrates the usage of the newly introduced Energy *
* Model framework and isn't supposed to be merged as-is. *
***
The Energy Model framework
In preparation for the definition of an energy-aware wakeup path,
introduce a helper function to estimate the consequence on system energy
when a specific task wakes-up on a specific CPU. compute_energy()
estimates the capacity state to be reached by all performance domains
and estimates the consum
If an Energy Model (EM) is available and if the system isn't
overutilized, re-route waking tasks into an energy-aware placement
algorithm. The selection of an energy-efficient CPU for a task
is achieved by estimating the impact on system-level active energy
resulting from the placement of the task
Energy Aware Scheduling (EAS) is designed with the assumption that
frequencies of CPUs follow their utilization value. When using a CPUFreq
governor other than schedutil, the chances of this assumption being true
are small, if any. When schedutil is being used, EAS' predictions are at
least consist
In preparation for the introduction of a new root domain flag which can
be set during load balance (the 'overutilized' flag), clean-up the set
of parameters passed to update_sg_lb_stats(). More specifically, the
'local_group' and 'local_idx' parameters can be removed since they can
easily be recons
Energy Aware Scheduling (EAS) in its current form is most relevant on
platforms with asymmetric CPU topologies (e.g. Arm big.LITTLE) since
this is where there is a lot of potential for saving energy through
scheduling. This is particularly true since the Energy Model only
includes the active power
From: Morten Rasmussen
Energy-aware scheduling is only meant to be active while the system is
_not_ over-utilized. That is, there are spare cycles available to shift
tasks around based on their actual utilization to get a more
energy-efficient task distribution without depriving any tasks. When
a
Add another member to the family of per-cpu sched_domain shortcut
pointers. This one, sd_asym_cpucapacity, points to the lowest level
at which the SD_ASYM_CPUCAPACITY flag is set. While at it, rename the
sd_asym shortcut to sd_asym_packing to avoid confusions.
Generally speaking, the largest oppor
The existing scheduling domain hierarchy is defined to map to the cache
topology of the system. However, Energy Aware Scheduling (EAS) requires
more knowledge about the platform, and specifically needs to know about
the span of Performance Domains (PD), which do not always align with
caches.
To ad
Expose the Energy Model (read-only) of all performance domains in sysfs
for convenience. To do so, add a kobject to the CPU subsystem under the
umbrella of which a kobject for each performance domain is attached.
The resulting hierarchy is as follows for a platform with two
performance domains for
This patch series introduces Energy Aware Scheduling (EAS) for CFS tasks
on platforms with asymmetric CPU topologies (e.g. Arm big.LITTLE).
For more details about the ideas behind it and the overall design,
please refer to the cover letter of version 5 [1].
1. Version history
--
Several subsystems in the kernel (task scheduler and/or thermal at the
time of writing) can benefit from knowing about the energy consumed by
CPUs. Yet, this information can come from different sources (DT or
firmware for example), in different formats, hence making it hard to
exploit without a sta
Schedutil requests frequency by aggregating utilization signals from
the scheduler (CFS, RT, DL, IRQ) and applying a 25% margin on top of
them. Since Energy Aware Scheduling (EAS) needs to be able to predict
the frequency requests, it needs to forecast the decisions made by the
governor.
In order
By default, arch_scale_cpu_capacity() is only visible from within the
kernel/sched folder. Relocate it to include/linux/sched/topology.h to
make it visible to other clients needing to know about the capacity of
CPUs, such as the Energy Model framework.
Cc: Ingo Molnar
Cc: Peter Zijlstra
Signed-o
Re-sending the patches with the "Cc: sta...@vger.kernel.org" included
in the sign-off area, as per Option 1 of the rules Greg referred me
to. I hope that now I have done everything by the rules.
On Sun, 2 Dec 2018 at 21:42, Tigran Aivazian wrote:
>
> just wanted to add: although the subject says
On Fri, Nov 30, 2018 at 1:29 PM Chen-Yu Tsai wrote:
>
> The Bananapi M2+ comes with an optional sensor based on the ov5640 from
> Omnivision. Enable the support for it in the DT.
>
> Signed-off-by: Chen-Yu Tsai
> ---
> arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 87 +++
> 1 f
On Sun, 02 Dec 2018 17:57:06 +0100,
Jeremy Cline wrote:
>
> On 12/1/18 9:44 AM, Takashi Iwai wrote:
> > On Fri, 30 Nov 2018 17:51:33 +0100,
> > Jeremy Cline wrote:
> >>
> >> On 11/30/18 11:00 AM, Takashi Iwai wrote:
> >>> On Fri, 30 Nov 2018 15:49:17 +0100,
> >>> Jeremy Cline wrote:
>
>
Scenario 1, ARMv7:
==
If code in arch/arm/kernel/ftrace.c would operate on mcount() pointer
the following may be generated:
0230 :
230: b5f8push{r3, r4, r5, r6, r7, lr}
232: b500push{lr}
234: f7ff fffe bl 0 <__gnu_mcount_nc>
Hi David,
On 10/5/18 12:08 PM, David HERNANDEZ SANCHEZ wrote:
Add configuration on DT for thermal sensor driver
Signed-off-by: David Hernandez Sanchez
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi
b/arch/arm/boot/dts/stm32mp157c.dtsi
index 661be94..e90b9f6 100644
--- a/arch/arm/boot/dts/s
On 2018/12/3 17:19, Jerome Brunet wrote:
On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
- 223:100 undefined (no interrupt)
- 99:97 3
On Fri, Nov 30, 2018 at 1:29 PM Chen-Yu Tsai wrote:
>
> The CSI controller found on the H3 (and H5) is a reduced version of the
> one found on the A31. It only has 1 channel, instead of 4 channels for
> time-multiplexed BT.656. Since the H3 is a reduced version, it cannot
> "fallback" to a compati
On Sun, 2018-12-02 at 22:42 +0100, Martin Blumenstingl wrote:
> Martin Blumenstingl (3):
> - clk: meson: meson8b: fix the offset of -- vid_pll_dco's N value
> - clk: meson: meson8b: add the fractional divider for -- vid_pll_dco
> - clk: meson: meson8b: add the read-only video clock trees
>
>
On Fri, Nov 30, 2018 at 1:29 PM Chen-Yu Tsai wrote:
>
> The CSI controller found on the H3 (and H5) is a reduced version of the
> one found on the A31. It only has 1 channel, instead of 4 channels for
> time-multiplexed BT.656. Since the H3 is a reduced version, it cannot
> "fallback" to a compati
Hi Shawn,
Thank you for the review.
> On Tue, Nov 13, 2018 at 01:12:13PM +0100, Lukasz Majewski wrote:
> > The procedure to read this ID value is as follows:
> >
> > rmmod spi_fsl_dspi
> > insmod spi-gpio.ko
> >
> > echo 504 > /sys/class/gpio/export
> > cat /sys/class/gpio/gpio504/value
> > ...
In KVM, specially for nested guests, there is a dominant pattern of:
=> map guest memory -> do_something -> unmap guest memory
In addition to all this unnecessarily noise in the code due to boiler plate
code, most of the time the mapping function does not properly handle memory
that is no
Guest memory can either be directly managed by the kernel (i.e. have a "struct
page") or they can simply live outside kernel control (i.e. do not have a
"struct page"). KVM mostly support these two modes, except in a few places
where the code seems to assume that guest memory must have a "struct pa
Use kvm_vcpu_map for accessing the shadow VMCS since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/vmx.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --
Use kvm_vcpu_map when mapping the virtual APIC page since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
One additional semantic change is that the virtual host mapping lifecycle
has changed a bit. It now has the same lifetime of the pinning of th
Use kvm_vcpu_map when mapping the posted interrupt descriptor table since
using kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory
that has a "struct page".
One additional semantic change is that the virtual host mapping lifecycle
has changed a bit. It now has the same lifetime of t
From: Filippo Sironi
cmpxchg_gpte() calls get_user_pages_fast() to retrieve the number of
pages and the respective struct page to map in the kernel virtual
address space.
This doesn't work if get_user_pages_fast() is invoked with a userspace
virtual address that's backed by PFNs outside of kernel
Use kvm_vcpu_map in emulator_cmpxchg_emulated since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
Signed-off-by: KarimAllah Ahmed
---
v1 -> v2:
- Update to match the new API return codes
---
arch/x86/kvm/x86.c | 13 ++---
1 file changed
Use kvm_vcpu_map in synic_clear_sint_msg_pending since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
Signed-off-by: KarimAllah Ahmed
---
v1 -> v2:
- Update to match the new API return codes
---
arch/x86/kvm/hyperv.c | 16 ++--
1 fil
On Sun, Dec 02, 2018 at 07:28:55PM -0800, Randy Dunlap wrote:
> Hi,
> I have more editing comments below.
>
>
> On 11/15/18 5:01 PM, Jarkko Sakkinen wrote:
> > Documentation of the features of the Software Guard eXtensions used
> > by the Linux kernel and basic design choices for the core and dri
Use kvm_vcpu_map in synic_deliver_msg since using kvm_vcpu_gpa_to_page()
and kmap() will only work for guest memory that has a "struct page".
Signed-off-by: KarimAllah Ahmed
---
v1 -> v2:
- Update to match the new API return codes
---
arch/x86/kvm/hyperv.c | 12 ++--
1 file changed, 6 in
Use kvm_vcpu_map for accessing the enhanced VMCS since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/vmx.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/ar
Use the new mapping API for mapping guest memory to avoid depending on
"struct page".
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/svm.c | 97 +++---
1 file changed, 49 insertions(+), 48 deletions(-)
diff --git a/arch/x86/kvm/svm.c b/arch/x86/
Read the data directly from guest memory instead of the map->read->unmap
sequence. This also avoids using kvm_vcpu_gpa_to_page() and kmap() which
assumes that there is a "struct page" for guest memory.
Suggested-by: Jim Mattson
Signed-off-by: KarimAllah Ahmed
Reviewed-by: Jim Mattson
---
v1 ->
Use kvm_vcpu_map when mapping the L1 MSR bitmap since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
Signed-off-by: KarimAllah Ahmed
---
v1 -> v2:
- Do not change the lifecycle of the mapping (pbonzini)
---
arch/x86/kvm/vmx.c | 14 --
Copy the VMCS12 directly from guest memory instead of the map->copy->unmap
sequence. This also avoids using kvm_vcpu_gpa_to_page() and kmap() which
assumes that there is a "struct page" for guest memory.
Signed-off-by: KarimAllah Ahmed
---
v3 -> v4:
- Return VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION
Update the PML table without mapping and unmapping the page. This also
avoids using kvm_vcpu_gpa_to_page(..) which assumes that there is a "struct
page" for guest memory.
Signed-off-by: KarimAllah Ahmed
---
v1 -> v2:
- Use kvm_write_guest_page instead of kvm_write_guest (pbonzini)
- Do not use po
On Mon, Dec 03, 2018 at 11:01:00AM +0800, Baoquan He wrote:
> It looks do-able, not sure if the test case is complicated or not, if
> not hard, I can have a try. And I have some internal bugs, can focus on
> this later. I saw you posted another patchset to fix xen issue, it may
> not be needed any
On Fri 2018-11-30 20:51:54, Yangtao Li wrote:
> We already have the DEFINE_SHOW_ATTRIBUTE,There is no need to define such
> a macro,so remove define_genpd_open_function and define_genpd_debugfs_fops.
> Also use DEFINE_SHOW_ATTRIBUTE to simplify somecode.
"and there", ", so".
> Signed-off-by: Yang
On Mon, 3 Dec 2018 11:14:54 +0200
Tomer Maimon wrote:
> This patch set adds Flash Interface Unit(FIU) SPI-NOR
> support for the Nuvoton NPCM Baseboard Management
> Controller (BMC).
>
> The FIU supports single, dual or quad communication interface.
>
> the FIU controller can operate i
On Mon, Dec 03, 2018 at 10:23:03AM +1100, Dave Chinner wrote:
On Sat, Dec 01, 2018 at 02:49:09AM -0500, Sasha Levin wrote:
In 'git log'! You report these every time you fix something in upstream
xfs but don't backport it to stable trees:
That is so wrong on so many levels I don't really know w
Le 22/10/2018 à 22:13, Dave Hansen a écrit :
> Persistent memory is cool. But, currently, you have to rewrite
> your applications to use it. Wouldn't it be cool if you could
> just have it show up in your system like normal RAM and get to
> it like a slow blob of memory? Well... have I got the p
On Fri, Nov 30, 2018 at 04:35:06PM -0800, Dan Williams wrote:
> Dan Williams (5):
> generic/pgtable: Make {pmd,pud}_same() unconditionally available
> generic/pgtable: Introduce {p4d,pgd}_same()
> generic/pgtable: Introduce set_pte_safe()
> x86/mm: Validate kernel_physical_m
On Mon, 3 Dec 2018, Peter Zijlstra wrote:
> On Mon, Dec 03, 2018 at 09:35:00AM +0100, Peter Zijlstra wrote:
> > On Sat, Dec 01, 2018 at 12:37:01PM -0800, Paul E. McKenney wrote:
> > > On Sat, Dec 01, 2018 at 04:31:49PM +0800, Wen Yang wrote:
> > > > Fix the following warnings reported by coccin
On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>
> - 223:100 undefined (no interrupt)
> - 99:97 3 pins on bank GPIOE
> - 96:77 20 pi
Add a driver for Renesas R-Car Gen3 RPC SPI controller.
Signed-off-by: Mason Yang
---
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-renesas-rpc.c | 808 ++
3 files changed, 815 insertions(+)
create mode 1006
Hi Mark,
On Mon, 3 Dec 2018 08:39:00 +
Yogesh Narayan Gaur wrote:
>
> Yogesh Gaur (7):
> spi: add support for octal mode I/O data transfer
> spi: spi-mem: add support for octal mode I/O data transfer
Can you take those 2 patches in your tree for 4.21/5.0?
> mtd: spi-nor: add opcodes
Added device tree binding documentation for Nuvoton BMC
NPCM Flash Interface Unit(FIU) SPI-NOR controller.
Signed-off-by: Tomer Maimon
---
Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI-NOR
controller driver
The FIU supports single, dual or quad communication interface.
the FIU controller can operate in following modes:
- User Mode Access(UMA): provides flash access by using an
indirect address/data mechanism.
- direct rd/wr m
This patch set adds Flash Interface Unit(FIU) SPI-NOR
support for the Nuvoton NPCM Baseboard Management
Controller (BMC).
The FIU supports single, dual or quad communication interface.
the FIU controller can operate in following modes:
- User Mode Access(UMA): provides flash access by us
* Wen Yang wrote:
> This is the patch to the file cpu.c
> which fixes the following coccinelle warning:
>
> WARNING: Comparison to bool
>
> Signed-off-by: Wen Yang
> CC: Thomas Gleixner
> CC: Ingo Molnar
> CC: Konrad Rzeszutek Wilk
> CC: Josh Poimboeuf
> CC: "Peter Zijlstra (Intel)"
> C
On Mon, Dec 03, 2018 at 06:10:51PM +0900, Ryusuke Konishi wrote:
> Hi, Pan Bian
>
> Thank you for feeding back this patch.
> I reviewed this and am thinking this must be sent to upstream.
>
> Did you see any kernel oops on this bug ?
Not yet. In fact, I found it with a static method.
Best regar
On 12/02/2018 09:43 PM, Arnd Bergmann wrote:
> On Sun, Dec 2, 2018 at 2:47 PM Gabriel Francisco Mandaji
> wrote:
>
>> @@ -667,10 +653,28 @@ static void vivid_overlay(struct vivid_dev *dev,
>> struct vivid_buffer *buf)
>> }
>> }
>>
>> +static void vivid_cap_update_frame_period(struct viv
On Fri, Nov 30, 2018 at 3:26 PM Yangtao Li wrote:
>
> In a function whose return type is void, returning on the last line is
> not required.So remove it.Also move the module declaration to the end.
The last piece is not reflected by the subject.
Also, why do you move the MODULE_ stuff around at
On Sat, Dec 1, 2018 at 2:51 AM Yangtao Li wrote:
>
> We already have the DEFINE_SHOW_ATTRIBUTE,There is no need to define such
> a macro,so remove define_genpd_open_function and define_genpd_debugfs_fops.
> Also use DEFINE_SHOW_ATTRIBUTE to simplify somecode.
>
> Signed-off-by: Yangtao Li
It wou
Hi, Pan Bian
Thank you for feeding back this patch.
I reviewed this and am thinking this must be sent to upstream.
Did you see any kernel oops on this bug ?
Regards,
Ryusuke Konishi
On Mon, 26 Nov 2018 11:08:29 +0800, Pan Bian wrote:
> brelse(bh) is called to drop the reference count of bh whe
On Mon 03-12-18 04:00:08, Yueyi Li wrote:
> Found warning:
>
> WARNING: EXPORT symbol "gsi_write_channel_scratch" [vmlinux] version
> generation failed, symbol will not be versioned.
> WARNING: vmlinux.o(.text+0x1e0a0): Section mismatch in reference from the
> function valid_phys_addr_range() to
On Fri, Nov 30, 2018 at 8:28 PM Jarkko Sakkinen
wrote:
>
> In order to comply with the CoC, replace with a hug.
>
> Signed-off-by: Jarkko Sakkinen
> ---
> drivers/cpufreq/powernow-k7.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/powernow-k7.c b/d
Hi Chunyan,
On 29/11/18 2:53 PM, Adrian Hunter wrote:
> On 29/11/18 8:07 AM, Chunyan Zhang wrote:
>> Some standard SD host controllers can support both external dma
>> controllers as well as ADMA/SDMA in which the SD host controller
>> acts as DMA master. TI's omap controller is the case as an exa
Hi Bich,
On 11/15/18 9:52 AM, Bich HEMON wrote:
This patchset changes the CAN RAM mapping and adds CAN sleep pins.
Bich Hemon (3):
ARM: dts: stm32: change CAN RAM mapping on stm32mp157c
ARM: dts: stm32: add can1 sleep pins muxing
ARM: dts: stm32: add can1 sleep pins muxing on stm32mp15
* Peter Zijlstra wrote:
> On Sat, Dec 01, 2018 at 12:37:01PM -0800, Paul E. McKenney wrote:
> > On Sat, Dec 01, 2018 at 04:31:49PM +0800, Wen Yang wrote:
> > > Fix the following warnings reported by coccinelle:
> > >
> > > kernel/locking/locktorture.c:703:6-10: WARNING: Assignment of bool to 0
On 30-11-18, 10:44, Ulf Hansson wrote:
> On Mon, 26 Nov 2018 at 09:10, Viresh Kumar wrote:
> > +static int _genpd_reeval_performance_state(struct generic_pm_domain *genpd,
> > + unsigned int state, int depth);
> > +
>
> I don't like forward declarations li
* Ingo Molnar wrote:
> From 22b71f970f18f5f38161be028ab7ce7cd1f769f7 Mon Sep 17 00:00:00 2001
> From: Ingo Molnar
> Date: Mon, 3 Dec 2018 09:15:40 +0100
> Subject: [PATCH] x86/pci: Remove the dead-code DBG() macro
>
> While reading arch/x86/include/asm/pci_x86.h I noticed that we have ancient
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, December 3, 2018 1:35 PM
> To: Yogesh Narayan Gaur ;
> broo...@kernel.org
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; vigne...@ti.com;
> linux-...@vger.kernel.org; de
On Mon, Dec 03, 2018 at 09:35:00AM +0100, Peter Zijlstra wrote:
> On Sat, Dec 01, 2018 at 12:37:01PM -0800, Paul E. McKenney wrote:
> > On Sat, Dec 01, 2018 at 04:31:49PM +0800, Wen Yang wrote:
> > > Fix the following warnings reported by coccinelle:
> > >
> > > kernel/locking/locktorture.c:703:6-
Hi Benjamin,
On 11/12/18 4:23 PM, Benjamin Gaignard wrote:
This serie adds the support of the hardware semaphore block for stm32mp1 SoC.
version 3:
- fix clock name in properties description.
- use postcore_initcall() instead of module_platform_driver()
version 2:
- fix comments done by Bjorn
- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag specifying flash support octal read commands.
Signed-off-by: Vignesh R
Signed-off
On Mon 03-12-18 08:47:00, Ingo Molnar wrote:
[...]
> I reviewed the ->cred_guard_mutex code, and the mutex is held across all
> of exec() - and we always did this.
Yes, this is something that has been pointed out during the review. Oleg
has argued that making this path freezable is really hard an
Add support for octal mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
C
Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new SPI_NOR_OCTAL_REA
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- None
Changes for v4:
- None
Changes fo
Add support for octal mode I/O data transfer in spi-mem framework.
Signed-off-by: Yogesh Gaur
Reviewed-by: Boris Brezillon
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Patch added in v2
Add flags for Octal mode I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
SPI_TX_OCTAL: transmit with 8 wires
SPI_RX_OCTAL: receive with 8 wires
Signed-off-by: Yogesh Gaur
Reviewed-by: Boris Brezillon
---
Chan
Add octal mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports 8 lines Rx/Tx data transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2
Add support for octal mode IO data transfer.
Micron flash, mt35xu512aba, supports octal mode data transfer and
NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
Patch series
* Add support for octal mode flags and parsing of same in spi driver.
* Add parsing logic for spi-mem
Add DT binding document for stingray usb phy.
Signed-off-by: Srinath Mannam
Reviewed-by: Florian Fainelli
Reviewed-by: Scott Branden
---
.../bindings/phy/brcm,stingray-usb-phy.txt | 62 ++
1 file changed, 62 insertions(+)
create mode 100644
Documentation/devicetre
Add DT nodes for
- Two xHCI host controllers
- Two BDC Broadcom USB device controller
- Five USB PHY controllers
[xHCI0] [BDC0][xHCI1][BDC1]
| | | |
--- ---
|
These patches add stingray usb phy driver and its
corresponding DT nodes with documentation.
All patches are based on Linux-4.19.
Changes from v1:
- Addressed Kishon review comments
- phy init call return value handle
Srinath Mannam (3):
dt-bindings: phy: Add binding document for stingra
This driver supports all versions of stingray SS and HS
USB phys.
In version 1 is combo phy contain both SS and HS phys
in a common IO space.
In version 2 a single HS phy.
These phys support both xHCI host driver and
BDC Broadcom device controller driver.
Signed-off-by: Srinath Mannam
Reviewed-by
Hi,
another friendly reminder for this patchset...
Any comments/objections?
regards;Richard.L
On 17.10.18 14:51, Richard Leitner wrote:
> Add reset-gpio, sx8654[056] and common of_touchscreen functions support
> for the sx8654 driver.
>
> Changes v2:
> - use devm_gpiod_get_optional in pro
On Sat, Dec 01, 2018 at 12:37:01PM -0800, Paul E. McKenney wrote:
> On Sat, Dec 01, 2018 at 04:31:49PM +0800, Wen Yang wrote:
> > Fix the following warnings reported by coccinelle:
> >
> > kernel/locking/locktorture.c:703:6-10: WARNING: Assignment of bool to 0/1
> > kernel/locking/locktorture.c:91
Hello!
On 03.12.2018 6:45, Yu Chen wrote:
This patch adds binding descriptions to support the dwc3 controller
on HiSilicon SoCs and boards like the HiKey960.
Cc: Greg Kroah-Hartman
Cc: Rob Herring
Cc: Mark Rutland
Cc: John Stultz
Signed-off-by: Yu Chen
---
.../devicetree/bindings/usb/dw
701 - 800 of 816 matches
Mail list logo
