There is no real need to use locking since we can simply read out the
volatile variable value once and the watermark changing shouldn't clash
with the changes made by the interrupt handler.
Signed-off-by: Dmitry Osipenko
---
drivers/devfreq/tegra-devfreq.c | 21 -
1 file
The kHz to Hz is incorrectly converted in a few places in the code,
this results in a wrong frequency being calculated because devfreq core
uses OPP frequencies that are given in Hz to clamp the rate, while
tegra-devfreq gives to the core value in kHz and then it also expects to
receive value in
This fixes "_opp_is_duplicate" warning messages on driver's module reload.
Signed-off-by: Dmitry Osipenko
---
drivers/devfreq/tegra-devfreq.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/devfreq/tegra-devfreq.c b/drivers/devfreq/tegra-devfreq.c
index
The IRQ releasing is handled by "managed resources", hence there is no
need to release IRQ manually.
Signed-off-by: Dmitry Osipenko
---
drivers/devfreq/tegra-devfreq.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/devfreq/tegra-devfreq.c b/drivers/devfreq/tegra-devfreq.c
index
The devfreq driver can be used on Tegra30 without any code change and
it works perfectly fine, the default Tegra124 parameters are good enough
for Tegra30.
Signed-off-by: Dmitry Osipenko
---
drivers/devfreq/Kconfig | 2 +-
drivers/devfreq/tegra-devfreq.c | 1 +
2 files changed, 2
The clk_set_min_rate() could fail and in this case clk_set_rate() sets
rate to 0, which may drop EMC rate to minimum and make machine very
difficult to use.
Signed-off-by: Dmitry Osipenko
---
drivers/devfreq/tegra-devfreq.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff
Hello,
I tried to utilize the Tegra devfreq driver on Tegra30 and found out that
it doesn't work properly due to improper Hz<->kHz conversions made by the
driver. After fixing that problem and doing some more testing I noticed
that there are things that could be improved and in result here is
On Thu, Apr 11, 2019 at 11:55:40PM +0200, Enric Balletbo Serra wrote:
> Hi,
>
> Many thanks for sending this patch upstream. Looks really interesting.
> Some few comments below ...
>
> Please prefix the patch with "chrome/platform: cros_ec_proto: ..."
>
> Missatge de Raul E Rangel del dia dc.,
On 4/11/2019 6:21 PM, Kees Cook wrote:
Proposed alternative plan: let's add a new symbol, something like
DEBUG_MISC ("Miscellaneous debug code that should be under a more
specific debug option but isn't"), make it depend on DEBUG_KERNEL and be
"default DEBUG_KERNEL" but allow itself to be turned
On Thu, Apr 11, 2019 at 3:16 PM Josh Triplett wrote:
>
> On Wed, Apr 10, 2019 at 11:13:52PM -0400, Sinan Kaya wrote:
> > On 4/10/2019 11:02 PM, Josh Triplett wrote:
> > > Then let's fix*that*, and get checkpatch to help enforce it in the
> > > future. EXPERT doesn't affect code generation, and
Hello RT Folks!
I'm pleased to announce the 3.18.138-rt115 stable release.
You can get this release via the git tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-stable-rt.git
branch: v3.18-rt
Head SHA1: 0b31ad979fb6e00b1aa16f873c05fa2cb486b00f
Or to build 3.18.138-rt115
On 4/11/19 5:10 PM, Miquel Raynal wrote:
> Hi Gustavo,
>
> "Gustavo A. R. Silva" wrote on Thu, 11 Apr
> 2019 13:30:31 -0500:
>
>> Hi Miquel,
>>
>> On 2/5/19 6:55 AM, Miquel Raynal wrote:
>> [..]
@@ -3280,12 +3280,14 @@ static void onenand_check_features(struct mtd_info
*mtd)
On Thu, Apr 11, 2019 at 10:00:24AM -0700, Kees Cook wrote:
> On Wed, Apr 10, 2019 at 10:34 PM Masahiro Yamada
> wrote:
> >
> > On Thu, Apr 11, 2019 at 11:47 AM Kees Cook wrote:
> > >
> > > On Wed, Apr 10, 2019 at 5:56 PM Sinan Kaya wrote:
> > > >
> > > > We can't seem to have a kernel with
On Wed, Apr 10, 2019 at 11:13:52PM -0400, Sinan Kaya wrote:
> On 4/10/2019 11:02 PM, Josh Triplett wrote:
> > Then let's fix*that*, and get checkpatch to help enforce it in the future.
> > EXPERT doesn't affect code generation, and neither should this.
>
> I think we have to do both. We need to
On Fri, 2019-04-05 at 14:59 +0100, Will Deacon wrote:
> + 1. All readX() and writeX() accesses to the same peripheral are ordered
> +with respect to each other. For example, this ensures that MMIO
> register
> + writes by the CPU to a particular device will arrive in program
Some of Memory Controller registers are shadowed and require latching in
order to copy assembly state into the active, MC_EMEM_ARB_CFG is one of
these registers.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
There is no need for a memory barriers on reading/writing of register
values as we only care about the read/write order, hence let's use the
common helpers.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
Multiplying the Memory Controller clock rate by the tick count results
in an integer overflow and in result the truncated tick value is being
programmed into hardware, such that the GR3D memory client performance is
reduced by two times.
Cc: stable
Signed-off-by: Dmitry Osipenko
---
Hello, this series properly addresses the bugged memory arbitration
programming and in result the previous suspend-resume workaround change
is reverted as it was not entirely correct.
Dmitry Osipenko (4):
memory: tegra: Fix missed registers values latching
memory: tegra: Fix integer overflow
Turned out that the actual bug was in the Memory Controller driver
that programmed shadowed registers without latching the new values
and then there was a bug on EMEM arbitration configuration calculation
that results in a wrong value being latched on resume from suspend.
The Memory Controller has
Hi Gustavo,
"Gustavo A. R. Silva" wrote on Thu, 11 Apr
2019 13:30:31 -0500:
> Hi Miquel,
>
> On 2/5/19 6:55 AM, Miquel Raynal wrote:
> [..]
> >> @@ -3280,12 +3280,14 @@ static void onenand_check_features(struct mtd_info
> >> *mtd)
> >>if ((this->version_id & 0xf) == 0xe)
>
Preparing to add an sdhci-trace.o to the sdhci module.
Signed-off-by: Raul E Rangel
---
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/{sdhci.c => sdhci-core.c} | 0
2 files changed, 1 insertion(+)
rename drivers/mmc/host/{sdhci.c => sdhci-core.c} (100%)
diff --git
I was debugging a SDHC hardware bug and got tired of having to
translate the register values by hand. This patch set makes it so all
SDHC register read and write operations can be traced and easily read by
a human.
An example trace can be seen here: https://pastebin.com/x73d5cvL
I ended up
An example trace can be seen here: https://pastebin.com/x73d5cvL
I was unable to leave sdhci_readX and sdhci_writeX as macros because
they are used in other modules (i.e., sdhci-pci). This means they can't
call the trace_sdhci_XXX functions without explicitly exporting the
private trace function
Adds an sdhci-trace object file that is linked with the sdhci module.
This will allow sdhci-core to call the trace functions.
There weren't constants defined for some of the fields, so I just used
the raw values.
See the next change for usage.
Signed-off-by: Raul E Rangel
---
This is a hybrid method that combines the functionality of
trace_print_flags_seq and trace_print_symbols_seq. It supports printing
bit fields, enum fields, and numeric fields.
Given the following register definition:
* 0 - Enabled
* 1 - Width, 0 = 1-bits, 1 = 4-bits
* 2:3 - DMA, 0 =
Hi Dan,
this probaly was discussed, but I did not follow brightness model
discussions:
what will happen if I set yellow by writing into yellow mode
brightness, and then orange by writing orange model brightness?
Will the resulting color be a mix of yellow and orange, or will the
orange overwrite
Hi,
Am Donnerstag, 11. April 2019, 17:26:41 CEST schrieb Doug Anderson:
> On Wed, Apr 10, 2019 at 8:27 PM elaine.zhang wrote:
> > 在 2019/4/10 下午11:34, Doug Anderson 写道:
> > On Tue, Apr 9, 2019 at 11:23 PM elaine.zhang
> > wrote:
> > 在 2019/4/10 上午4:47, Douglas Anderson 写道:
> >
> > This reverts
When a clk user requests rate that is higher than the maximum possible,
the rate shall be clamped to the maximum and not to the current value.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-emc.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git
The EMC clock marked as critical, hence it is already enabled at the
registration time.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-emc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c
index 0621a3a82ea6..23416982e7c7
The Memory Controller clock rate can't be simply changed and nothing in
kernel need to change the rate, hence let's make the clock read-only.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-divider.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
There is no justification for the BUG() in this code.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-emc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c
index 9a0179235939..93ecb538e59b 100644
---
Hello, I was helping with fixing EMC clock scaling on T124 Nyan Big and
in process found some weak points in the code. Primarily the ram code
parsing didn't work if device-tree defines memory timings for multiple
ram codes and after fixing that I spotted few other things that could be
improved.
The timings parser doesn't append timings, but instead it parses only
the first timing and hence doesn't store all of the timings when
device-tree has timings for multiple ram codes. In a result EMC scaling
doesn't work if timings are missing.
Tested-by: Steev Klimaszewski
Signed-off-by: Dmitry
Hi, Light
On Thu, Apr 11, 2019 at 2:32 AM Light Hsieh wrote:
>
> Since no single Mediatek chip use code for PINCTRL_MTK and code for
> PINCTRL_MTK_MOORE/PINCTRL_MTK_PARIS simultaneously, it is better to use
> different config to determine if related code will be built or not on
> building
Use the of_property_count_elems_of_size() helper instead of open-coding
it's logic. As a bonus this will now error out if the "reg" property
values use an incorrect size (anything other than sizeof(u32)).
Signed-off-by: Martin Blumenstingl
---
drivers/mtd/nand/raw/meson_nand.c | 5 +
1 file
This series comes with four small improvements for the meson-nand
driver:
* the first patches are replacing open-coded logic with existing
utilities / helpers
* the third patch drops some unnecessary casting after changing
the type of the info buffer parameter from "u8 *" to "void *"
* the
Documentation/scheduler/completion.txt states:
Calling init_completion() on the same completion object twice is
most likely a bug as it re-initializes the queue to an empty queue and
enqueued tasks could get "lost" - use reinit_completion() in that case,
but be aware of other races.
Use the recently introduced struct_size macro instead of open-coding
it's logic.
No functional changes.
Signed-off-by: Martin Blumenstingl
---
drivers/mtd/nand/raw/meson_nand.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/meson_nand.c
This simplifies the code because it gets rid of the casts to an
u8-pointer when passing "info_buf" from struct meson_nfc_nand_chip.
Also it gets rid of the cast of the u8 databuf pointer to a void
pointer.
The logic inside meson_nfc_dma_buffer_setup() doesn't care about the
pointer types
On Thu, Apr 11, 2019 at 2:45 PM Roman Gushchin wrote:
>
> On Thu, Apr 11, 2019 at 10:09:06AM -0700, Suren Baghdasaryan wrote:
> > On Thu, Apr 11, 2019 at 8:33 AM Matthew Wilcox wrote:
> > >
> > > On Wed, Apr 10, 2019 at 06:43:53PM -0700, Suren Baghdasaryan wrote:
> > > > Add new SS_EXPEDITE flag
Hi,
Many thanks for sending this patch upstream. Looks really interesting.
Some few comments below ...
Please prefix the patch with "chrome/platform: cros_ec_proto: ..."
Missatge de Raul E Rangel del dia dc., 10
d’abr. 2019 a les 22:25:
>
> This is useful to see which EC commands are being
On 4/11/19 2:12 PM, Paul Walmsley wrote:
On Thu, 11 Apr 2019, Christoph Hellwig wrote:
On Thu, Apr 11, 2019 at 01:42:59AM -0700, Paul Walmsley wrote:
Similar to ARM64, add support for building DTB files from DT source
data for RISC-V boards.
This patch starts with the infrastructure needed
Hello, here are two trivial patches that are correcting PLLM on Tegra124.
First fixes system lockup due to a bad hardware configuration, second
removes usage of a non-existent register bit.
Dmitry Osipenko (2):
clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides
divider
clk:
According to the Tegra124 TRM documentation, PLLM_MISC2 register doesn't
have the lock-enable bit as well as any other PLLM-related register. Hence
PLLM re-locking can't be initiated by software. The incorrect bit setting
should have been harmless since that bit is undefined according to TRM.
There are wrongly set parenthesis in the code that are resulting in a
wrong configuration being programmed for PLLM. The original fix was made
by Danny Huang in the downstream kernel. The patch was tested on Nyan Big
Tegra124 chromebook, PLLM rate changing works correctly now and system
doesn't
Fixes:
commit 1e381f60dad9 ("ext4: do not allow journal_opts for fs w/o journal")
Instead of removing EXT4_MOUNT_JOURNAL_CHECKSUM from s_def_mount_opt as
I assume was intended, all other options were blown away leading to
_ext4_show_options() output being incorrect. I don't see why this or
other
On Thu, Apr 11, 2019 at 10:09:06AM -0700, Suren Baghdasaryan wrote:
> On Thu, Apr 11, 2019 at 8:33 AM Matthew Wilcox wrote:
> >
> > On Wed, Apr 10, 2019 at 06:43:53PM -0700, Suren Baghdasaryan wrote:
> > > Add new SS_EXPEDITE flag to be used when sending SIGKILL via
> > > pidfd_send_signal()
Hi Nick,
Some comments below ...
Missatge de Nick Crews del dia dj., 11 d’abr.
2019 a les 0:09:
>
> As part of Chrome OS's FAFT (Fully Automated Firmware Testing)
> tests, we need to ensure that the H1 chip is properly setting
> some GPIO lines. The h1_gpio attribute exposes the state
> of the
Hi Guillaume,
On Thu, Apr 11, 2019 at 10:46 AM Guillaume La Roque
wrote:
>
> Add TS clock used by two temperature sensor
thank you for working on this!
> Signed-off-by: Guillaume La Roque
> ---
> drivers/clk/meson/g12a.c | 31 +++
> drivers/clk/meson/g12a.h | 3
On 4/11/19 4:46 AM, Christoph Hellwig wrote:
On Thu, Apr 11, 2019 at 01:42:59AM -0700, Paul Walmsley wrote:
Similar to ARM64, add support for building DTB files from DT source
data for RISC-V boards.
This patch starts with the infrastructure needed for SiFive boards.
Boards from other vendors
On Thu, Apr 11, 2019 at 04:24:21PM -0400, Joel Fernandes (Google) wrote:
> Since commit title ("srcu: Allocate per-CPU data for DEFINE_SRCU() in
> modules"), modules that call DEFINE_{STATIC,}SRCU will have a new array
> of srcu_struct pointers, which is used by srcu code to initialize and
> clean
When offlining a memory block that contains reserved CMA areas, it will
set those page blocks migration type as MIGRATE_ISOLATE. Then, onlining
will set them as MIGRATE_MOVABLE. As the results, those page blocks lose
their original types, i.e., MIGRATE_CMA, and then it causes troubles
like
Hi all,
In commit
270ad142eb0f ("apparmor: fix missing ZLIB defines")
Fixes tag
Fixes: 876dd866c084 ("apparmor: Initial implementation of raw policy blob co
has these problem(s):
- Subject has leading but no trailing parentheses
- Subject has leading but no trailing quotes
Please do
Hi all,
In commit
5c41ea6d5200 ("mmc: sdhci-omap: Don't finish_mrq() on a command error during
tuning")
Fixes tag
Fixes: 5b0d62108b46 ("mmc: sdhci-omap: Add platform specific reset
has these problem(s):
- Subject has leading but no trailing parentheses
- Subject has leading but no
On 4/11/19 2:02 AM, Paul Walmsley wrote:
Add a serial driver for the SiFive UART, found on SiFive FU540 devices
(among others).
The underlying serial IP block is relatively basic, and currently does
not support serial break detection. Further information on the IP
block can be found in the
On Thu, Apr 11, 2019 at 09:54:24PM +0200, Peter Zijlstra wrote:
> On Thu, Apr 11, 2019 at 09:39:06PM +0200, Peter Zijlstra wrote:
> > I think this bisect is bad. If you look at your own logs this patch
> > merely changes the failure, but doesn't make it go away.
> >
> > Before this patch (in
On Thu, 11 Apr 2019, Andreas Schwab wrote:
> On Apr 11 2019, Paul Walmsley wrote:
>
> > +static void sifive_serial_set_termios(struct uart_port *port,
> > + struct ktermios *termios,
> > + struct ktermios *old)
> > +{
> > +
On Thu, 11 Apr 2019, Christoph Hellwig wrote:
> On Thu, Apr 11, 2019 at 01:42:59AM -0700, Paul Walmsley wrote:
> > Similar to ARM64, add support for building DTB files from DT source
> > data for RISC-V boards.
> >
> > This patch starts with the infrastructure needed for SiFive boards.
> >
On Thu, Apr 11, 2019 at 10:11:51PM +0200, Michal Hocko wrote:
> On Thu 11-04-19 15:14:30, Joel Fernandes wrote:
> > On Thu, Apr 11, 2019 at 08:12:43PM +0200, Michal Hocko wrote:
> > > On Thu 11-04-19 12:18:33, Joel Fernandes wrote:
> > > > On Thu, Apr 11, 2019 at 6:51 AM Michal Hocko wrote:
> > >
Hi,
* Daniel Lezcano [190411 19:21]:
> On 10/04/2019 22:07, Tony Lindgren wrote:
> > Hi,
> >
> > * Daniel Lezcano [190410 17:02]:
> >> can you ask for an acked-by before pulling a patch in your tree?
> >
> > I certainly do ask and wait for acks where possible :)
>
> Ok, I may have missed
Let's allow adapters, domains and control domains to be assigned to or
unassigned from an AP matrix mdev device while it is in use by a guest.
When an adapter, domain or control domain is assigned to or unassigned
from an mdev device while a guest is using it, the guest's CRYCB will be
updated
This patch series extends the crypto adapter pass-through support to
provide safeguards against inadvertent sharing of AP resources between
guests and/or the host, and to implement more of the s390 AP
architecture related to provisioning and dynamic configuration of
AP resources.
Tony Krowiak
Let's implement the callback to indicate when an APQN
is in use by the vfio_ap device driver. The callback is
invoked whenever a change to the apmask or aqmask may
result in one or APQNs being removed from the driver. The
vfio_ap device driver will indicate a resource is in use
if any of the
Updates to the documentation to reflect changes introduced by
this patch series. This patch also clarifies the section on
configuring the apmask and aqmask.
Signed-off-by: Tony Krowiak
---
Documentation/s390/vfio-ap.txt | 147 +++--
1 file changed, 113
Refactors the AP queue reset function to wait until the queue is empty
after the PQAP(ZAPQ) instruction is executed to zero out the queue as
required by the AP architecture.
Signed-off-by: Tony Krowiak
---
drivers/s390/crypto/vfio_ap_ops.c | 35 ---
1 file
The AP architecture does not preclude assignment of AP resources that are
not yet in the AP configuration (i.e., not available or not online).
Let's go ahead and implement this facet of the AP architecture for linux
guests.
Access to AP resources is controlled by bit masks in a guest's SIE
state
Once an APQN is assigned to an mdev device it will remained assigned until
it is explicitly unassigned from the mdev device. The associated AP queue
devices, however, can come and go due to failures or deliberate actions by
a sysadmin. For example, a sysadmin can dynamically remove an AP adapter
Introduces a new driver callback to prevent a root user from unbinding
an AP queue from its device driver if the queue is in use. This prevents
a root user from inadvertently taking a queue away from a guest and
giving it to the host, or vice versa. The callback will be invoked
whenever a change
On Thu, Apr 11, 2019 at 05:47:46AM +0100, Al Viro wrote:
> Note, BTW, that umount coming between isolate and drop is not a problem;
> it call shrink_dcache_parent() on the root. And if shrink_dcache_parent()
> finds something on (another) shrink list, it won't put it to the shrink
> list of its
On Tue, Apr 2, 2019 at 10:09 AM Moritz Fischer wrote:
>
> Hi Wu,
>
> On Mon, Mar 25, 2019 at 11:07:36AM +0800, Wu Hao wrote:
> > This patch adds id_table for each dfl private feature driver,
> > it allows to reuse same private feature driver to match and support
> > multiple dfl private features.
Hello
On 4/11/19 2:38 PM, Dan Murphy wrote:
> Introduce the bindings for the Texas Instruments LP5036, LP5030, LP5024 and
> the LP5018
> RGB LED device driver. The LP5036/3024/18 can control RGB LEDs individually
s/LP5036/3024/18->LP5036/30/24/18
Dan
On Thu, Apr 11, 2019 at 1:22 PM Dan Williams wrote:
>
> On Thu, Apr 11, 2019 at 1:08 PM Guenter Roeck wrote:
> >
> > On Thu, Apr 11, 2019 at 10:35 AM Kees Cook wrote:
> > >
> > > On Thu, Apr 11, 2019 at 9:42 AM Guenter Roeck wrote:
> > > >
> > > > On Thu, Apr 11, 2019 at 9:19 AM Kees Cook
Hello
On 4/11/19 2:38 PM, Dan Murphy wrote:
> Introduce the LP5036/30/24/18 RGB LED driver.
> The difference in these parts are the number of
> LED outputs where the:
>
> LP5036 can control 36 LEDs
> LP5030 can control 30 LEDs
> LP5024 can control 24 LEDs
> LP5018 can control 18 LEDs
>
> The
This adds the initial DT for the Lenovo Miix 630 laptop. Supported
functionality includes USB (host), microSD-card, keyboard, and trackpad.
Signed-off-by: Jeffrey Hugo
---
v2:
-Changed "cls" to "clam" since feedback indicated "cls" is too opaque, but
"clamshell" is a mouthfull. "clam" seems
On Thu, Apr 11, 2019 at 01:08:15PM -0700, Guenter Roeck wrote:
> On Thu, Apr 11, 2019 at 10:35 AM Kees Cook wrote:
> >
> > On Thu, Apr 11, 2019 at 9:42 AM Guenter Roeck wrote:
> > >
> > > On Thu, Apr 11, 2019 at 9:19 AM Kees Cook wrote:
> > > >
> > > > On Thu, Mar 7, 2019 at 7:43 AM Dan
On Tue, Apr 2, 2019 at 10:50 AM Moritz Fischer wrote:
Hi Hao,
>
> On Mon, Mar 25, 2019 at 11:07:37AM +0800, Wu Hao wrote:
> > As these two functions are used by other private features. e.g.
> > in error reporting private feature, it requires to check port status
> > and reset port for error
On Thu, Apr 11, 2019 at 8:17 PM Ulf Hansson wrote:
>
> After some preceding changes, PM domains managed by genpd may contain
> CPU devices, so idle state residency values should be taken into
> account during the state selection process. [The residency value is
> the minimum amount of time to be
Hi,
* Daniel Lezcano [190411 20:13]:
> I can see those fixes in timers/core:
>
> Fixes: 592ea6bd1fad ("clocksource: timer-ti-dm: Make unexported
> functions static")
Hmm so this one was over a year ago related to the PWM series :)
> Fixes: 008258d995a6 ("clocksource/drivers/timer-ti-dm: Make
On Tue, Apr 2, 2019 at 10:07 AM Moritz Fischer wrote:
>
> Hi Wu,
>
> On Mon, Mar 25, 2019 at 11:07:39AM +0800, Wu Hao wrote:
> > STP (SignalTap) is one of the private features under the port for
> > debugging. This patch adds private feature driver support for it
> > to allow userspace
Quoting Paul Cercueil (2019-03-19 07:05:35)
> Add macro for the UDC PHY clock of the JZ4725B.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
Quoting Paul Cercueil (2019-03-19 07:05:36)
> Add clock for the USB Device Controller PHY.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
Quoting Bjorn Andersson (2019-03-06 09:47:58)
> +
> +static int turingcc_probe(struct platform_device *pdev)
> +{
> + int ret;
> +
> + pm_runtime_enable(>dev);
> + ret = pm_clk_create(>dev);
Neat solution. Thanks!
> + if (ret)
> + goto disable_pm_runtime;
>
On Thu, Apr 11, 2019 at 12:26 PM Eric Biggers wrote:
> Well, I guess I'll just add __GFP_COMP so I at least don't get spammed with
> useless bug reports.
Thanks, I appreciate it.
> But I don't think it's in any way acceptable to change the semantics of the
> kernel's page allocator but only
Quoting Bjorn Andersson (2019-03-06 09:47:58)
> The Turing Clock Controller provides resources related to running the
> Turing subsystem.
>
> PM runtime is used to ensure that the associated AHB clock is ticking
> while the clock framework is accessing the registers in the Turing clock
>
Quoting Bjorn Andersson (2019-03-06 09:47:57)
> Some clocks can only be turned on by resetting the block containing
> them, provide a clock type that allow us to reference these clocks and
> have the client drivers enable and "disable" them.
>
> Signed-off-by: Bjorn Andersson
> ---
Applied to
Quoting Bjorn Andersson (2019-03-06 09:47:56)
> Add devicetree binding for the turing clock controller found in QCS404.
>
> Signed-off-by: Bjorn Andersson
> ---
Applied to clk-next
Quoting Bjorn Andersson (2019-03-05 21:51:48)
> Add the clocks and resets need in order to control the Turing
> remoteproc.
>
> Signed-off-by: Bjorn Andersson
> ---
Applied to clk-next
On 11/04/2019 21:36, Nathan Chancellor wrote:
> On Thu, Apr 11, 2019 at 09:20:56PM +0200, Daniel Lezcano wrote:
>> On 10/04/2019 22:07, Tony Lindgren wrote:
>>> Hi,
>>>
>>> * Daniel Lezcano [190410 17:02]:
can you ask for an acked-by before pulling a patch in your tree?
>>>
>>> I certainly
Since commit title ("srcu: Allocate per-CPU data for DEFINE_SRCU() in
modules"), modules that call DEFINE_{STATIC,}SRCU will have a new array
of srcu_struct pointers, which is used by srcu code to initialize and
clean up these structures and save valuable per-cpu reserved space.
There is no
Quoting Weiyi Lu (2019-03-04 21:05:46)
> From: James Liao
>
> Some modules may need to change its clock rate before turn on it.
> So changing PLL's rate when it is off should be allowed.
> This patch removes PLL enabled check before set rate, so that
> PLLs can set new frequency even if they are
Quoting Weiyi Lu (2019-03-04 21:05:45)
> Add MT8183 clock support, include topckgen, apmixedsys,
> infracfg, mcucfg and subsystem clocks.
>
> Signed-off-by: Weiyi Lu
> ---
Applied to clk-next
Quoting Nicolas Boichat (2019-03-08 06:46:01)
>
> > > +
> > > +#define GATE_AUDIO0(_id, _name, _parent, _shift) \
> > > + GATE_MTK(_id, _name, _parent, _cg_regs, _shift, \
> > > + _clk_gate_ops_no_setclr)
>
> This macro (or variants that end up being
On Thu, Apr 11, 2019 at 1:08 PM Guenter Roeck wrote:
>
> On Thu, Apr 11, 2019 at 10:35 AM Kees Cook wrote:
> >
> > On Thu, Apr 11, 2019 at 9:42 AM Guenter Roeck wrote:
> > >
> > > On Thu, Apr 11, 2019 at 9:19 AM Kees Cook wrote:
> > > >
> > > > On Thu, Mar 7, 2019 at 7:43 AM Dan Williams
> >
Quoting Weiyi Lu (2019-03-04 21:05:44)
> In previous MediaTek PLL design, it assumes the pcw change control
> is always on the CON1 register.
> However, the pcw change bit on MT8183 was moved onto CON0 because
> the the PCW length of audio PLLs are extended to 32-bit.
> Add configurable
Quoting Weiyi Lu (2019-03-04 21:05:43)
> On some Mediatek platforms, there are critical clocks of
> clock gate type.
> To register clock gate with flags CLK_IS_CRITICAL,
> we need to add the flags field in mtk_gate data and register APIs.
>
> Signed-off-by: Weiyi Lu
This patch doesn't apply,
On Thu, Apr 11, 2019 at 10:02:32PM +0200, Christian Brauner wrote:
> On April 11, 2019 10:00:59 PM GMT+02:00, Joel Fernandes
> wrote:
> >On Thu, Apr 11, 2019 at 01:50:42PM -0400, Joel Fernandes (Google)
> >wrote:
> >> pidfd are /proc/pid directory file descriptors referring to a task
> >group
>
From: Yazen Ghannam
The focus of this patchset is define and use the MCA bank structures
and bank count per logical CPU.
With the exception of patch 4, this set applies to systems in production
today.
Patch 1:
Moves the declaration of struct mce_banks[] to the only file it's used.
Patch 2:
From: Yazen Ghannam
On legacy systems, the addresses of the MCA_MISC* registers need to be
recursively discovered based on a Block Pointer field in the registers.
On Scalable MCA systems, the register space is fixed, and particular
addresses can be derived by regular offsets for bank and
From: Yazen Ghannam
The struct mce_banks[] array is only used in mce/core.c so move the
definition of struct mce_bank to mce/core.c and make the array static.
Also, change the "init" field to bool type.
Signed-off-by: Yazen Ghannam
---
Link:
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