On Wed, 10 Apr 2019 21:07:47 +0800
Yue Haibing wrote:
> From: YueHaibing
>
> Fix gcc build error while CONFIG_MTD_NAND_ECC_SW_BCH
> is set to module:
>
> drivers/mtd/nand/raw/nand_base.o: In function `nand_cleanup':
> (.text+0xef6): undefined reference to `nand_bch_free'
>
On Wed, 10 Apr 2019 09:14:14 +0800
masonccy...@mxic.com.tw wrote:
> Hi Boris,
>
> >
> > Subject
> >
> > Re: [PATCH] mtd: rawnand: Add Macronix NAND read retry and randomizer
> support
> >
> > On Tue, 9 Apr 2019 17:35:39 +0800
> > masonccy...@mxic.com.tw wrote:
> >
> > > > > +
> > > > >
o them in order to move more driver data from .data to
> .rodata section.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Boris Brezillon
> ---
>
> include/linux/mtd/rawnand.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/linux/m
On Tue, 9 Apr 2019 17:35:39 +0800
masonccy...@mxic.com.tw wrote:
> > > +
> > > +static const struct kobj_attribute sysfs_mxic_nand =
> > > + __ATTR(nand_random, S_IRUGO | S_IWUSR,
> > > + mxic_nand_rand_type_show,
> > > + mxic_nand_rand_type_store);
> >
> > No, we don't
On Tue, 9 Apr 2019 11:22:52 +0800
Mason Yang wrote:
> Add a driver for Macronix NAND read retry and randomizer.
These are 2 orthogonal changes, and should thus bit split in 2 patches.
>
> Signed-off-by: Mason Yang
> ---
> drivers/mtd/nand/raw/nand_macronix.c | 169
>
d-by
>
> Cc: Doug Anderson
> Cc: Eric Anholt
> Cc: Heiko Stuebner
> Cc: Jeffy Chen
> Cc: Rob Herring
> Cc: Stéphane Marchesin
> Cc: Thierry Reding
> Cc: devicet...@vger.kernel.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Sean Paul
On Mon, 1 Apr 2019 17:26:51 +0200
Miquel Raynal wrote:
> Hi Aditya,
>
> Aditya Pakki wrote on Mon, 18 Mar 2019 18:24:34
> -0500:
>
> > of_match_device can return NULL if there is no matching device is found.
> > The patch avoids a potential NULL pointer dereference by checking for the
> >
On Fri, 29 Mar 2019 16:28:13 +0900
Masahiro Yamada wrote:
> With the recent refactoring, the NAND driver hooks now take a pointer
> to nand_chip. Add to_denali() in order to convert (struct nand_chip *)
> to (struct denali_nand_info *) directly. It is more useful than the
> current
Uytterhoeven
Signed-off-by: Boris Brezillon
---
drivers/misc/eeprom/at25.c | 282 +++--
1 file changed, 176 insertions(+), 106 deletions(-)
diff --git a/drivers/misc/eeprom/at25.c b/drivers/misc/eeprom/at25.c
index 99de6939cd5a..818853babbd0 100644
--- a/drivers/misc
iately.
I'll fix that. Thanks for reporting the problem.
Boris
>
> 1: ---
>
> linux-next MAINTAINERS section:
>
> 7333I3C SUBSYSTEM
> 7334M: Boris Brezillon
> 7335L: lin
On Fri, 29 Mar 2019 13:50:26 +0530
Vignesh Raghavendra wrote:
> Hi Boris,
>
> On 29/03/19 1:25 AM, Boris Brezillon wrote:
> > On Thu, 28 Mar 2019 16:46:24 +0530
> > Naga Sureshkumar Relli wrote:
> >
> >> Call spi_mem_default_supports_op() first, before c
On Thu, 28 Mar 2019 16:46:24 +0530
Naga Sureshkumar Relli wrote:
> Call spi_mem_default_supports_op() first, before calling controller
> specific ctlr->supports_op().
> With this, controller drivers can drop checking the buswidths again.
No, this was done on purpose, in case the controller does
rrent offset in gpio_values like the old driver used to.
>
> Fixes: commit ba32ce95cbd9 ("mtd: maps: Merge gpio-addr-flash.c into
> physmap-core.c")
You miss
Cc:
> Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/maps/physmap-core.
On Tue, 19 Mar 2019 22:57:11 +0100
Maxime Ripard wrote:
> Move the DRM formats API to turn this into a more generic image formats API
> to be able to leverage it into some other places of the kernel, such as
> v4l2 drivers.
>
> Signed-off-by: Maxime Ripard
> ---
>
On Wed, 13 Mar 2019 09:55:34 -0300
Paul Cercueil wrote:
> Hi,
>
> Le lun. 4 mars 2019 à 15:51, Miquel Raynal
> a écrit :
> > Hi Paul,
> >
> >> >> ---
> >> a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
> >> >> +++
> >>
On Tue, 12 Mar 2019 17:44:45 +0900
Masahiro Yamada wrote:
> +
> +static int denali_exec_instr(struct nand_chip *chip,
> + const struct nand_op_instr *instr)
> +{
> + struct denali_nand_info *denali = to_denali(chip);
> + bool width16 = chip->options &
gh atomic")
BTW, the same applies to other patches in this series.
> Suggested-by: Boris Brezillon
Other than that,
Reviewed-by: Boris Brezillon
Regards,
Boris
> Signed-off-by: Helen Koike
>
> ---
> Hello,
>
> As mentioned in the cover letter,
> I tested on the rockchi
The "mtd: " prefix is still missing. Should be "mtd: cfi: ". If you
send a new version, please fix that.
Thanks,
Boris
On Tue, 26 Feb 2019 22:00:48 +0800
Liu Jian wrote:
> In function do_write_buffer(), in the for loop, there is a case
> chip_ready() returns 1 while chip_good() returns 0, so
On Sat, 2 Mar 2019 01:59:41 +0900
"Tokunori Ikegami" wrote:
> > [...]
> > > In function do_write_buffer(), in the for loop, there is a
> > > case chip_ready() returns 1 while chip_good() returns 0, so
> > > it never break the loop.
> > > To fix this, chip_good() is enough and
Hi Ikegami,
On Fri, 1 Mar 2019 23:51:16 +0900
"Tokunori Ikegami" wrote:
> > Except this version no longer does what Vignesh suggested. See how you
> > no longer test if chip_good() is true if time_after() returns true. So,
> > imagine the thread entering this function is preempted just after
Boris Brezillon (1):
MAINTAINERS: Add an IRC channel for the I3C subsystem
Gustavo A. R. Silva (1):
i3c: master: dw-i3c-master: mark expected switch fall-through
MAINTAINERS| 1 +
drivers/i3c/master/dw-i3c-master.c | 1
On Thu, 28 Feb 2019 15:12:15 +
"liujian (CE)" wrote:
> > -Original Message-
> > From: Tokunori Ikegami [mailto:ikegam...@gmail.com]
> > Sent: Thursday, February 28, 2019 10:26 PM
> > To: liujian (CE) ; dw...@infradead.org;
> > computersforpe...@gmail.com; bbrezil...@kernel.org;
> >
On Wed, 27 Feb 2019 15:22:19 +0530
Vignesh Raghavendra wrote:
> On 26/02/19 11:46 PM, Sergei Shtylyov wrote:
> > On 02/19/2019 09:36 AM, Vignesh R (by way of Boris Brezillon
> > ) wrote:
> >
> >> Cypress HyperBus is Low Signal Count, High Performance Doubl
On Tue, 26 Feb 2019 21:53:16 -0600
"Gustavo A. R. Silva" wrote:
> Hi all,
>
> Friendly ping:
>
> Who can ack or review this, please?
Will be queued for the next release. Please be patient.
>
> Thanks
> --
> Gustavo
>
> On 2/11/19 4:14 PM, Gustavo A. R. Silva wrote:
> > In preparation to
mtd: spi-nor: split s25fl128s into s25fl128s0 and s25fl128s1
André Valentin (1):
mtd: spi-nor: Add support for mx25u3235f
Bean Huo (1):
mtd: spi-nor: Fix wrong abbreviation HWCPAS
Boris Brezillon (16):
mtd: Implement mtd_{read,write}() as wrappers around
mtd_{read,write}_
On Thu, 21 Feb 2019 10:41:33 +
"Bean Huo (beanhuo)" wrote:
> Hi, Vignesh
>
> >
> >Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an
> >integrated PHY. IP register layout is very similar to existing QSPI IP
> >except for
> >additional bits to support Octal and Octal
From: Boris Brezillon
On Fri, 2019-02-08 at 18:34:31 UTC, "Bean Huo (beanhuo)" wrote:
> From: Bean Huo
>
> Change SNOR_HWCPAS_READ_OCTAL to SNOR_HWCAPS_READ_OCTAL.
>
> Signed-off-by: Bean Huo
> Reviewed-by: Tudor Ambarus
Applied to http://git.infradead.or
From: Boris Brezillon
On Mon, 2019-02-18 at 12:04:43 UTC, Schrempf Frieder wrote:
> From: Frieder Schrempf
>
> This adds support for the EON EN25Q80A, a 8Mb SPI NOR chip.
> It is used on i.MX6 boards by Kontron Electronics GmbH
> (N60xx, N61xx).
> It was only tested with
From: Boris Brezillon
On Mon, 2019-02-18 at 12:04:43 UTC, Schrempf Frieder wrote:
> From: Frieder Schrempf
>
> This adds support for the Macronix MX25V8035F, a 8Mb SPI NOR chip.
> It is used on i.MX6UL/ULL SoMs by Kontron Electronics GmbH (N631x).
> It was only tested with a s
From: Boris Brezillon
On Fri, 2019-02-15 at 15:15:47 UTC, Colin King wrote:
> From: Colin Ian King
>
> There is a spelling mistake in a dev_error message. Fix it.
>
> Signed-off-by: Colin Ian King
> Reviewed-by: Tudor Ambarus
Applied to http://git.infradead.org/linux-mt
Hello Linus,
Here are 2 fixes for 5.0 (or -rc8 if you end up delaying the release).
Regards,
Boris
The following changes since commit d13937116f1e82bf508a6325111b322c30c85eb9:
Linux 5.0-rc6 (2019-02-10 14:42:20 -0800)
are available in the Git repository at:
+Sergei and Mason who recently worked on an HyperFlash controller.
On Tue, 19 Feb 2019 12:06:02 +0530
Vignesh R wrote:
> Cypress HyperBus is Low Signal Count, High Performance Double Data Rate Bus
> interface between a host system master and one or more slave interfaces.
> HyperBus is used to
From: Boris Brezillon
On Tue, 2019-02-12 at 08:38:09 UTC, Vignesh R wrote:
> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
> It also has an integrated PHY. IP register layout is very
> similar to existing QSPI IP except for additional bits to support Octal
> and Oc
From: Boris Brezillon
On Tue, 2019-02-12 at 08:38:08 UTC, Vignesh R wrote:
> AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence
> QSPI controller but supports Octal IO(x8 data lines) and Double Data
> Rate(DDR) mode. Add new compatible to support OSPI controlle
On Tue, 12 Feb 2019 09:31:31 -0600
"Gustavo A. R. Silva" wrote:
> In preparation to enabling -Wimplicit-fallthrough, mark switch
> cases where we are expecting to fall through.
>
> This patch fixes the following warning:
>
> drivers/mtd/lpddr/lpddr_cmds.c: In function ‘chip_ready’:
>
From: Boris Brezillon
On Mon, 2019-01-28 at 05:02:29 UTC, Purna Chandra Mandal wrote:
> cadence-quadspi controller allows upto eight bytes of data to
> be written in software Triggered Instruction generator (STIG) mode
> of operation. Lower 4 bytes are written through writedatalower an
On Tue, 5 Feb 2019 11:43:46 +0530
Vignesh R wrote:
> >> static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node
> >> *np)
> >> {
> >> - const struct spi_nor_hwcaps hwcaps = {
> >> - .mask = SNOR_HWCAPS_READ |
> >> - SNOR_HWCAPS_READ_FAST |
> >> -
OGRAM LOAD operation which
does not work as expected on some parts.
--------
Boris Brezillon (4):
mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache
mtd: spinand: Fix the error/cleanup path in spinand_init()
On Fri, 8 Feb 2019 18:43:26 +
"Bean Huo (beanhuo)" wrote:
> Hi,Boris
> I sent three times, seems last time is successful. would you check that is
> correct?
That's much better now, thanks!
Hi Bean,
On Fri, 8 Feb 2019 17:13:52 +
"Bean Huo (beanhuo)" wrote:
> Hi, Tutor
> Thanks. unfortunately, it doesn't work on my side. Problem is on our email
> server side, not my local setting.
> I followed your configuration, then git-email failed.
Can you paste the output of git
On Thu, 7 Feb 2019 10:16:05 +
wrote:
> Hi, Frieder,
>
> On 02/07/2019 12:06 PM, Schrempf Frieder wrote:
> > Hi Tudor,
> >
> > On 03.02.19 14:33, tudor.amba...@microchip.com wrote:
> >> Hi, Frieder,
> >>
> >> On 01/23/2019 09:56 AM, Schrempf Frieder wrote:
> >>> From: Frieder Schrempf
Hi Sobon,
On Tue, 5 Feb 2019 22:28:44 +
"Sobon, Przemyslaw" wrote:
> > From: Boris Brezillon
> > Sent: Sunday, February 3, 2019 12:35 AM
> > > +Przemyslaw
> > >
> > > On Fri, 1 Feb 2019 07:30:39 +0800
> > > Liu
off-by: Tudor Ambarus
Add my R-b back
Reviewed-by: Boris Brezillon
> ---
> v6: no change
> v5: collect R-b
> v4: s/smm/mr, init controller in serial memory mode by default
> v3: update smm value when different. rename mr/smm
> v2: cache MR value instead of moving the write
Hi Martin,
On Tue, 5 Feb 2019 16:52:51 +0100
Martin Kepplinger wrote:
> Disable BCH soft reset according to MX23 erratum #2847 ("BCH soft
> reset may cause bus master lock up") for MX28 too. It has the same
> problem.
>
> Observed problem: once per 100,000+ MX28 reboots NAND read failed on
>
From: Your Name
On Tue, 2019-02-05 at 15:52:51 UTC, Martin Kepplinger wrote:
> Disable BCH soft reset according to MX23 erratum #2847 ("BCH soft
> reset may cause bus master lock up") for MX28 too. It has the same
> problem.
>
> Observed problem: once per 100,000+ MX28 reboots NAND read failed
controller and mx25l25635e jedec,spi-nor flash.
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
> ---
> v6: add a caps instance to the sama5d2 entry instead of allowing caps
> to be NULL
> v5:
> - use WICR for sam9x60
> - remove ops hooks and introduce
Can we add a caps instance to the sama5d2 entry instead of allowing
caps to be NULL?
The rest looks good to me, feel free to add
Reviewed-by: Boris Brezillon
on your next version.
; get_device() twice.
> > We also should make sure to drop the reference to the device
> > taken by of_find_device_by_node() on driver unbind.
> >
> > Fixes: ae02ab00aa3c ("mtd: nand: jz4780: driver for NAND devices on
> > JZ4780 SoCs") Signed-off-by: Wen
On Tue, 5 Feb 2019 13:59:46 +0100
Miquel Raynal wrote:
> Hi Martin,
>
> Martin Kepplinger wrote on Tue, 29 Jan 2019
> 16:37:00 +0100:
>
> > From: Martin Kepplinger
> >
> > Disable BCH soft reset according to MX23 erratum #2847 ("BCH soft
> > reset may cause bus master lock up") for MX28
Hi Shivamurthy,
On Mon, 4 Feb 2019 11:17:51 +
"Shivamurthy Shastri (sshivamurthy)" wrote:
> Driver is redesigned using parameter page to support all the Micron
> SPI NAND flashes.
Do all Micron SPI NANDs really expose a valid ONFI param page? If
that's not the case, then relying on ONFi
On Mon, 4 Feb 2019 14:28:27 +
wrote:
> >
> >> + writel_relaxed(cfg->ifr, aq->regs + QSPI_IFR);
> >> +}
> >
> > Hm, so the only difference we have is the RICR vs ICR reg and the
> > APBTFRTYP_READ vs SAMA5D2_WRITE_TRSFR bit. Not sure it deserves
> > creating 2 hooks for that. Can we
On Mon, 4 Feb 2019 10:10:21 +
wrote:
> +
> +static void atmel_qspi_sam9x60_write_regs(const struct atmel_qspi *aq,
> + const struct spi_mem_op *op,
> + const struct atmel_qspi_cfg *cfg)
> +{
> + /* Clear pending
ove useless
> setting of write transfer type when
> op->data.dir == SPI_MEM_DATA_IN && !op->data.nbytes.
>
> QSPI_IFR_TFRTYP_TRSFR_WRITE is specific just to sama5d2 qspi,
> rename it to QSPI_IFR_SAMA5D2_WRITE_TRSFR.
>
> Suggested-by: Boris Brezillon
>
off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
> ---
> v4: s/smm/mr, init controller in serial memory mode by default
> v3: update smm value when different. rename mr/smm
> v2: cache MR value instead of moving the write access at probe
>
> drivers/spi/atmel-quadspi.c |
On Sun, 03 Feb 2019 11:56:32 -0300
Paul Cercueil wrote:
> Le dim. 3 févr. 2019 à 11:16, Boris Brezillon
> a écrit :
> > On Sun, 03 Feb 2019 10:58:13 -0300
> > Paul Cercueil wrote:
> >
> >> Le dim. 3 févr. 2019 à 4:35, Boris Brezillon
> >>
> &
On Sun, 03 Feb 2019 11:10:50 -0300
Paul Cercueil wrote:
> Le dim. 3 févr. 2019 à 11:08, Boris Brezillon
> a écrit :
> > On Sun, 03 Feb 2019 10:56:53 -0300
> > Paul Cercueil wrote:
> >
> >> Le dim. 3 févr. 2019 à 4:31, Boris Brezillon
> >>
> &
On Sun, 03 Feb 2019 10:58:13 -0300
Paul Cercueil wrote:
> Le dim. 3 févr. 2019 à 4:35, Boris Brezillon
> a écrit :
> > On Sat, 2 Feb 2019 20:19:26 -0300
> > Paul Cercueil wrote:
> >
> >> Add the backend code for the jz4780-bch driver to support
On Sun, 03 Feb 2019 10:56:53 -0300
Paul Cercueil wrote:
> Le dim. 3 févr. 2019 à 4:31, Boris Brezillon
> a écrit :
> > On Sat, 2 Feb 2019 20:19:21 -0300
> > Paul Cercueil wrote:
> >
> >> Add support for probing the jz4780-nand driver on the JZ
On Sun, 03 Feb 2019 10:01:36 -0300
Paul Cercueil wrote:
> Hi,
>
> Le dim. 3 févr. 2019 à 4:20, Boris Brezillon
> a écrit :
> > On Sat, 2 Feb 2019 20:19:17 -0300
> > Paul Cercueil wrote:
> >
> >> Hi,
> >>
> >> As request
vice
> taken by of_find_device_by_node() on driver unbind.
>
Missing Fixes tag.
> Signed-off-by: Wen Yang
> Cc: Tudor Ambarus
> Cc: Boris Brezillon
> Cc: Miquel Raynal
> Cc: Richard Weinberger
> Cc: David Woodhouse
> Cc: Brian Norris
> Cc: Marek Vasut
> Cc: Nicolas Ferre
>
vice
> taken by of_find_device_by_node() on driver unbind.
>
> Signed-off-by: Wen Yang
> Cc: Tudor Ambarus
> Cc: Boris Brezillon
> Cc: Miquel Raynal
> Cc: Richard Weinberger
> Cc: David Woodhouse
> Cc: Brian Norris
> Cc: Marek Vasut
> Cc: Nicolas Ferre
> Cc: Alexand
On Sun, 3 Feb 2019 09:26:45 +0100
Boris Brezillon wrote:
> +Przemyslaw
>
> On Fri, 1 Feb 2019 07:30:39 +0800
> Liu Jian wrote:
>
> > In function do_write_buffer(), in the for loop, there is a case
> > chip_ready() returns 1 while chip_good() returns 0, so
+Przemyslaw
On Fri, 1 Feb 2019 07:30:39 +0800
Liu Jian wrote:
> In function do_write_buffer(), in the for loop, there is a case
> chip_ready() returns 1 while chip_good() returns 0, so it never
> break the loop.
> To fix this, chip_good() is enough and it should timeout if it stay
> bad for a
On Sat, 2 Feb 2019 20:19:26 -0300
Paul Cercueil wrote:
> Add the backend code for the jz4780-bch driver to support the JZ4740
> SoC from Ingenic.
>
> Signed-off-by: Paul Cercueil
> ---
>
> Changes:
>
> v2: New patch
>
> drivers/mtd/nand/raw/ingenic/Makefile | 2 +-
>
On Sat, 2 Feb 2019 20:19:21 -0300
Paul Cercueil wrote:
> Add support for probing the jz4780-nand driver on the JZ4740 SoC from
> Ingenic.
>
> Signed-off-by: Paul Cercueil
> ---
>
> Changes:
>
> v2: - Add support for the JZ4740 and not the JZ4725B: they behave the
> same, and JZ4740 is
On Sat, 2 Feb 2019 20:19:23 -0300
Paul Cercueil wrote:
> The Ben Nanonote from Qi Hardware expects a specific OOB layout on its
> NAND. If the "ingenic,oob-layout" device property is set to "qi,lb60",
> this specific OOB layout is used.
I'm really not a big fan of this ingenic,oob-layout
On Sat, 2 Feb 2019 20:19:22 -0300
Paul Cercueil wrote:
> The boot ROM of the JZ4725B SoC expects a specific OOB layout on the
> NAND.
>
> Add an optional "ingenic,oob-layout" device property. When set to
> "ingenic,jz4725b", this specific OOB layout is used.
It's a SoC-specific layout, please
On Sat, 2 Feb 2019 20:19:17 -0300
Paul Cercueil wrote:
> Hi,
>
> As requested by Boris, I added a patch to move all the Ingenic NAND
> drivers to their own directory.
>
> In this V2 I added support for the JZ4740 SoC. The combo of the
> jz4780-nemc, jz4780-nand and jz4740-bch now obsolete the
On Sat, 2 Feb 2019 08:58:25 +
wrote:
> >> @@ -117,6 +120,7 @@
> >> #define QSPI_IFR_CRMBIT(14)
> >> #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
> >> #define QSPI_IFR_NBDUM(n) (((n) << 16) &
> >> QSPI_IFR_NBDUM_MASK)
> >> +#define
On Sat, 2 Feb 2019 08:46:38 +
wrote:
> On 02/02/2019 09:13 AM, Boris Brezillon wrote:
> > On Sat, 2 Feb 2019 04:07:33 +
> > wrote:
> >
> >> From: Tudor Ambarus
> >>
> >> Remove NOP when setting read transfer type. Remove useless
On Sat, 2 Feb 2019 08:44:27 +
wrote:
> On 02/02/2019 09:11 AM, Boris Brezillon wrote:
> > On Sat, 2 Feb 2019 04:07:19 +
> > wrote:
> >
> >> From: Tudor Ambarus
> >>
> >> The wrappers hid that the accesses are relaxed. Drop them.
>
On Sat, 2 Feb 2019 08:38:40 +
wrote:
> On 02/02/2019 09:06 AM, Boris Brezillon wrote:
> > On Sat, 2 Feb 2019 04:07:13 +
> > wrote:
> >
> >> From: Tudor Ambarus
> >>
> >> Cache Serial Memory Mode (SMM) value to avoid write access when
&
On Sat, 2 Feb 2019 04:07:46 +
wrote:
> From: Tudor Ambarus
>
> The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
> access, the other for the qspi core and phy. Both are mandatory. It uses
> different transfer type bits in IFR register. It has dedicated registers
>
On Sat, 2 Feb 2019 04:07:44 +
wrote:
> From: Tudor Ambarus
>
> The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
> access, the other for the qspi core and phy. Both are mandatory.
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
> Suggested-by: Boris Brezillon
> Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
> ---
> v3: new patch
>
> drivers/spi/atmel-quadspi.c | 33 ++---
> 1 file changed, 18 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/s
On Sat, 2 Feb 2019 04:07:39 +
wrote:
> From: Tudor Ambarus
>
> Naming clocks is a good practice. Make "pclk" madatory even if
> we support unnamed clock in the driver, to be backward compatible
> with old DTs.
>
> Suggested-by: Boris Brezillon
> Signed
On Sat, 2 Feb 2019 04:07:33 +
wrote:
> From: Tudor Ambarus
>
> Remove NOP when setting read transfer type. Remove useless
> setting of write transfer type when
> op->data.dir == SPI_MEM_DATA_IN && !op->data.nbytes.
>
> QSPI_IFR_TFRTYP_TRSFR_WRITE is specific just to sama5d2 qspi,
> rename
On Sat, 2 Feb 2019 04:07:22 +
wrote:
> From: Tudor Ambarus
>
> Let general names to core drivers.
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
> ---
> v3: no change
> v2: update after the removing of iomem access wrappers
>
> dr
On Sat, 2 Feb 2019 04:07:19 +
wrote:
> From: Tudor Ambarus
>
> The wrappers hid that the accesses are relaxed. Drop them.
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Tudor Ambarus
> ---
> v3: no change
> v2: new patch
>
>
On Sat, 2 Feb 2019 04:07:13 +
wrote:
> From: Tudor Ambarus
>
> Cache Serial Memory Mode (SMM) value to avoid write access when
> setting the controller in serial memory mode. SMM is set in
> exec_op() and not at probe time, to let room for future regular
> SPI support.
>
> Signed-off-by:
Hi Masahiro,
On Fri, 1 Feb 2019 19:27:46 +0900
Masahiro Yamada wrote:
> Hi.
>
>
> When I was looking into the NAND controller/chips separation,
> this question popped up in my mind.
>
>
> Commit 2d472aba15ff169 provides us a more flexibility
> about the controller/chips connection.
> The
On Fri, 1 Feb 2019 14:49:27 +
wrote:
>
> +#define QSPI_IFR_APBTFRTYP_READ BIT(24)
> >
> > And this one would be
> >
> > define QSPI_IFR_SAM9X60_READ_TRSFR BIT(24)
>
> I prefer letting this bit named as in the datasheet, QSPI_IFR_APBTFRTYP_READ,
> and change it
Hello Linus,
Here is the I3C fixes PR for 5.0-rc5.
Regards,
Boris
The following changes since commit 49a57857aeea06ca831043acbb0fa5e0f50602fd:
Linux 5.0-rc3 (2019-01-21 13:14:44 +1300)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git
On Fri, 1 Feb 2019 07:07:40 +
wrote:
> >
> >> #define QSPI_IFR_TFRTYP_MASKGENMASK(13, 12)
> >> #define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12)
> >> #define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12)
> >
> > Looks like the read/write flag is on bit 13. Can we just add
Hi Dinh,
On Thu, 31 Jan 2019 11:24:16 -0600
Dinh Nguyen wrote:
> On 1/28/19 4:20 AM, Miquel Raynal wrote:
> > Hi Dinh,
> >
> > Masahiro Yamada wrote on Wed, 16 Jan
> > 2019 10:27:11 +0900:
> >
> >> (+CC Dinh Nguyen)
> >>
> >> On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal
> >> wrote:
>
On Thu, 31 Jan 2019 16:15:28 +
wrote:
> From: Tudor Ambarus
>
> Cache MR value to avoid write access when setting the controller
> in Serial Memory Mode (SMM). SMM is set in exec_op() and not at
> probe time, to let room for future regular SPI support.
>
> Signed-off-by: Tudor Ambarus
>
On Thu, 31 Jan 2019 16:15:51 +
wrote:
> From: Tudor Ambarus
>
> The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
> access, the other for the qspi core and phy. Both are mandatory. It uses
> dedicated register for Read Instruction Code Register (RICR) and
> Write
On Thu, 31 Jan 2019 13:13:22 +
Peter Rosin wrote:
> On 2019-01-27 09:27, Boris Brezillon wrote:
> > On Thu, 10 Jan 2019 15:10:28 +
> > Peter Rosin wrote:
> >
> >> Hi!
> >>
> >> I found an unfortunate issue while recoding plane handling
On Thu, 31 Jan 2019 12:40:04 +
wrote:
> On 01/31/2019 01:55 PM, Boris Brezillon wrote:
> > On Wed, 30 Jan 2019 15:08:47 +
> > wrote:
> >
> >> +
> >> +static int atmel_sam9x60_qspi_set_cfg(struct atmel_qspi *aq,
> >> +
On Wed, 30 Jan 2019 15:08:47 +
wrote:
> +/*
> + * atmel_qspi_set_address_mode() - set address mode.
> + * @cfg: contains register values
> + * @op: describes a SPI memory operation
> + *
> + * The controller allows 24 and 32-bit addressing while NAND-flash requires
> + *
On Wed, 30 Jan 2019 15:08:47 +
wrote:
> +
> +static int atmel_sam9x60_qspi_set_cfg(struct atmel_qspi *aq,
> + const struct spi_mem_op *op,
> + struct atmel_qspi_cfg *cfg)
> +{
> + int ret = atmel_qspi_set_mode(cfg, op);
d/nand/raw/nand_bbt.c:173: warning: Function parameter or member
> 'this' not described in 'read_bbt'
> ../drivers/mtd/nand/raw/nand_bbt.c:173: warning: Excess function parameter
> 'chip' description in 'read_bbt'
>
> Signed-off-by: Randy Dunlap
> Cc: Boris Brezillon
> Cc: Miq
On Wed, 30 Jan 2019 15:08:47 +
wrote:
> +static int atmel_sam9x60_qspi_clk_prepare_enable(struct atmel_qspi *aq)
> +{
> + struct device *dev = >pdev->dev;
> + int ret;
> +
> + if (!aq->clk) {
> + /* Get the peripheral clock */
> + aq->clk =
On Wed, 30 Jan 2019 15:08:45 +
wrote:
> From: Tudor Ambarus
>
> The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
> access, the other for the qspi core and phy. Both are mandatory.
>
> Signed-off-by: Tudor Ambarus
> ---
>
On Wed, 30 Jan 2019 15:08:43 +
wrote:
> From: Tudor Ambarus
>
> Introduced in:
> commit b60557876849 ("ARM: dts: at91: sama5d2: switch to new clock binding")
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
> ---
> Documentation/devicet
On Wed, 30 Jan 2019 15:08:40 +
wrote:
> From: Tudor Ambarus
>
> Adopt the SPDX license identifiers to ease license compliance
> management.
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
> ---
> drivers/spi/atmel-quadspi.c | 13 +-
On Wed, 30 Jan 2019 15:08:38 +
wrote:
> From: Tudor Ambarus
>
> Return -ENOTSUPP when atmel_qspi_find_mode() fails. Propagate
> the error in atmel_qspi_exec_op().
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
> ---
> drivers/spi/atmel-quad
On Wed, 30 Jan 2019 15:08:35 +
wrote:
> From: Tudor Ambarus
>
> The cast is done implicitly.
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
> ---
> drivers/spi/atmel-quadspi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
On Wed, 30 Jan 2019 15:08:33 +
wrote:
> From: Tudor Ambarus
>
> Let general names to core drivers.
>
> Signed-off-by: Tudor Ambarus
> ---
> drivers/spi/atmel-quadspi.c | 52
> ++---
> 1 file changed, 26 insertions(+), 26 deletions(-)
>
> diff
On Wed, 30 Jan 2019 15:08:31 +
wrote:
> From: Tudor Ambarus
>
> Cosmetic change, no functional change.
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
> ---
> drivers/spi/atmel-quadspi.c | 9 -
> 1 file changed, 4 insertions(+), 5 dele
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