[PATCH] ASoC: wm8804: Allow control of master clock divider in PLLgeneration

the MCLK divider. Signed-off-by: Daniel Matuschek Acked-by: Charles Keepax Tested-by: Florian Meier --- sound/soc/codecs/wm8804.c | 17 ++--- sound/soc/codecs/wm8804.h | 4 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/wm8804.c b/sound/soc

Re: [alsa-devel] [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

I'm sorry for this. Looks like I still had problems with some whitespaces. I will resend the patch and hope, it will work now. Daniel Am 17.01.2014 um 13:22 schrieb Mark Brown : > On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: > >> WM8804 can run with P

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

The idle_bias_off should not be part of this patch. I will check this again. Am 17.01.2014 um 18:59 schrieb Mark Brown : > On Fri, Jan 17, 2014 at 05:43:14PM +0100, Florian Meier wrote: >> I have tested your patch. >> There is a (non blocking) error message regarding .idle_bias_off, but I >> assu

[PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

the MCLK divider. Signed-off-by: Daniel Matuschek --- sound/soc/codecs/wm8804.c | 17 ++--- sound/soc/codecs/wm8804.h |4 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/wm8804.c b/sound/soc/codecs/wm8804.c index 1704b1e..4619bf8 100644

[PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

Signed-off-by: Daniel Matuschek After some discussions of the patch last week, here is a new version. Simply reducing the post_table did not work, as for some frequencies both settings (MCLKDIV=0 and MCLKDIV=1) are needed (e.g. 96 and 192kHz) WM8804 can run with PLL frequencies of 256xfs

[PATCH] ASoC: wm8804: Cleanup of post_table

Signed-off-by: Daniel Matuschek Existing post_table has duplicate settings for some PLL settings. Only the first setting was used with mclk_div=1 With the updated post_table, the driver uses mclk_div=0 whenever it is possible. This allows the WM8804 to work at 256xfs internal clock and

Re: [alsa-devel] [PATCH] ASoC: wm8804: Allow fine-grained control of the PLL generation

On 09.01.2014, at 15:27, Charles Keepax wrote: > On Wed, Jan 08, 2014 at 10:36:53PM +0100, Daniel Matuschek wrote: >> Signed-off-by: Daniel Matuschek >> > > > >> pll_div->freqmode = post_table[i].freqmode; >> -

[PATCH] ASoC: wm8804: Allow fine-grained control of the PLL generation

Signed-off-by: Daniel Matuschek WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using the "pllid" argument of the "set_pll&q