Add the DDR memory arbitrer dedicated to audio subsystem of the g12a
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts/amlogic/meson
Add the spdif output devices of the g12a SoCs.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 24 +
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index
Add the PDM audio capture device of the g12a SoC.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index
Add the capture and playback audio fifos (DMA) of the g12a SoCs.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 73 +
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts/amlogic
Add the tdm encoders, decoders and interfaces devices of the g12a SoC.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 135
1 file changed, 135 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts
Add the controller dedicated to audio clocks found on the g12a SoC.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 37 +
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts/amlogic
Add the spdif input device of the g12a SoC
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index
merged through ASoC [1].
[0]: https://lkml.kernel.org/r/20190329160649.31603-2-jbru...@baylibre.com
[1]: https://lkml.kernel.org/r/20190404111733.28705-2-jbru...@baylibre.com
Jerome Brunet (7):
arm64: dts: meson: g12a: add audio clock controller
arm64: dts: meson: g12a: add audio memory
On Wed, 2019-04-10 at 14:13 +0800, Chunfeng Yun wrote:
> Use devm_clk_get_optional() to get optional clock
>
> Cc: Martin Blumenstingl
> Signed-off-by: Chunfeng Yun
> Acked-by: Martin Blumenstingl
Reviewed-by: Jerome Brunet
> ---
> v2: add Acked-by Martin Blumenstingl
u prefer, I can try to submit a fixup to keep the patch in stable.
Status is the same for the stable/linux-4.19.y.
>
> -------
> commit 9b0f430450cf230e736bc40f95bf34fbdb99cead
> Author: Jerome Brunet
> Date: Fri Dec 21 17:02:36 2018 +0100
>
>
On Fri, 2019-04-05 at 13:43 -0700, Stephen Boyd wrote:
> Quoting Michael Turquette (2019-04-05 08:43:40)
> > Hi Jerome,
> >
> > On Fri, Mar 29, 2019 at 3:58 PM Jerome Brunet wrote:
> > > On Fri, 2019-03-29 at 15:14 -0700, Stephen Boyd wrote:
> > >
On Fri, 2019-03-29 at 23:58 +0100, Jerome Brunet wrote:
> On Fri, 2019-03-29 at 15:14 -0700, Stephen Boyd wrote:
> > > > We actively discourage using init callbacks. Can you do this some other
> > > > way?
> > >
> > > Yes I'm aware of that but init it
According the publicly available datasheet (and some test) the max98357a
also supports 32, 44.1 and 88.2 kHz sample rate.
Signed-off-by: Jerome Brunet
---
Datasheet is available here:
https://datasheets.maximintegrated.com/en/ds/MAX98357A-MAX98357B.pdf
sound/soc/codecs/max98357a.c | 3
Since the g12a SoC fifo can set the fifo initial start address, we must
make sure to actually reset the write pointer to this address when
starting a capture.
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-toddr.c | 53 +
1 file changed, 53 insertions
Add new compatible strings for the g12a devices.
Audio wise, the g12a is fairly to close to the axg, yet some differences
need to be handled.
Signed-off-by: Jerome Brunet
---
Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt | 4 +++-
Documentation/devicetree/bindings/sound/amlogic
The g12a tdmout requires a different signal skew offset than the axg.
With this change, the skew offset is added as a parameter of the tdm
formatters to prepare the addition of the g12a support.
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-tdm-formatter.c | 6 --
sound/soc/meson
SoC family
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-fifo.c | 34 +++---
sound/soc/meson/axg-fifo.h | 2 ++
2 files changed, 33 insertions(+), 3 deletions(-)
diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c
index 75e5e480fda2
The axg tdmout driver just need a different skew offset to operate
correctly on the g12a SoC family.
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-tdmout.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/sound/soc/meson/axg-tdmout.c b/sound/soc/meson/axg-tdmout.c
index
at the same time.
Like the toddr fifo, the g12a frddr also need to take care of resetting
the read pointer to the initial fifo address when preparing a playback.
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-frddr.c | 143 +++-
1 file changed, 140
pointer shall be reset to this address on startup.
* frddrs may now play on up to 3 output interfaces simultaneously.
* tdmout formatters need a different signal skew offset.
Jerome Brunet (6):
ASoC: meson: add g12a compatibles
ASoC: meson: axg-fifo: add g12a support
ASoC: meson: axg-toddr
in dpcm_be_dai_startup(), just skip those BE.
Fixes: 906c7d690c3b ("ASoC: dpcm: Apply symmetry for DPCM")
Signed-off-by: Jerome Brunet
---
sound/soc/soc-pcm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index 0d5ec68a1e50..99
On Sat, 2019-03-30 at 16:56 +0100, Martin Blumenstingl wrote:
> Hi Jerome,
>
> On Sat, Mar 30, 2019 at 12:07 AM Jerome Brunet wrote:
> > On Fri, 2019-03-29 at 20:39 +0100, Martin Blumenstingl wrote:
> > > Hi Jerome,
> > >
> > > On Fri, Mar 29, 2
On Sat, 2019-03-30 at 16:58 +0100, Martin Blumenstingl wrote:
> On Fri, Mar 29, 2019 at 4:34 PM Jerome Brunet wrote:
> > As reported on this [0] mpll series, We are observing a lot of jitter
> > on the MPLL outputs of the g12a. No such jitter is seen on gx family.
> > On
On Sun, 2019-03-31 at 01:40 -0500, Rob Herring wrote:
> On Thu, Mar 14, 2019 at 05:37:24PM +0100, Jerome Brunet wrote:
> > From: Guillaume La Roque
> >
> > Add optional drive-strength property
> >
> > Signed-off-by: Guillaume La Roque
On Fri, 2019-03-29 at 20:39 +0100, Martin Blumenstingl wrote:
> Hi Jerome,
>
> On Fri, Mar 29, 2019 at 4:34 PM Jerome Brunet wrote:
> > The bit 'SSEN' available on some MPLL DSS outputs is not related to the
> > fractional part of the divider but to the function called
On Fri, 2019-03-29 at 15:14 -0700, Stephen Boyd wrote:
> > > We actively discourage using init callbacks. Can you do this some other
> > > way?
> >
> > Yes I'm aware of that but init it the right place to do this.
> > To be clear, this is not initializing the clock to some particular rate, the
>
clocks in the provider anymore,
so we can completely remove them later on.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 21 ++---
drivers/clk/meson/axg-audio.h | 29 -
2 files changed, 6 insertions(+), 44 deletions(-)
diff --git
clocks
Signed-off-by: Maxime Jourdan
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 240 +-
drivers/clk/meson/axg-audio.h | 7 +-
2 files changed, 239 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg
The audio clock controller is compatible with axg and g12a SoC family.
Having each clock name prefixed with "axg_" looks weird on the g12a.
This change replace the "axg_" by "aud_" in fron the clock names.
Signed-off-by: Jerome Brunet
---
drive
Add a new compatible string and additional clock ids for audio clock
controller of the g12a SoC family.
Signed-off-by: Jerome Brunet
---
.../bindings/clock/amlogic,axg-audio-clkc.txt | 3 ++-
include/dt-bindings/clock/axg-audio-clkc.h | 10 ++
2 files changed, 12
This patchset updates the axg audio controller to support the audio
controller of the g12a SoC family.
Jerome Brunet (3):
dt-bindings: clk: axg-audio: add g12a support
clk: meson: axg_audio: replace prefix axg by aud
clk: meson: axg-audio: don't register inputs in the onecell data
Maxime
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/clk-mpll.c | 9 ++---
drivers/clk/meson/clk-mpll.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
index 64d31c8ba3d0..2d39a8bc367c 100644
--- a/drivers/clk/meson/clk-mp
After testing, it appears that the SSEN bit controls the spread
spectrum function on MPLL2, not MPLL0.
Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 10 +-
1 file changed, 5 insertions(+), 5
The documentation says there is an SSEN bit on mpll0 but, after testing
it, no spread spectrum function appears to be enabled by this bit on any
of the MPLLs.
Let's remove it until we know more
Fixes: 1f737ffa13ef ("clk: meson: mpll: fix mpll0 fractional part ignored")
Signed-off-
and completely break SPDIF.
After exchanging with Amlogic, it seems he have activated (by mistake)
the 'spread spectrum' feature.
This patchset properly set the bit responsible for the spread spectrum
in the mpll driver and add the required correction in the related clock
controllers.
Jerome
d_pll divider driver")
> Signed-off-by: Neil Armstrong
> ---
> drivers/clk/meson/vid-pll-div.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Jerome Brunet
On Wed, 2019-03-27 at 11:33 +0100, Neil Armstrong wrote:
> On Amlogic Meson G12b platform, the fclk_div3 seems to be necessary for
> the system to operate correctly.
>
> Disabling it cause the entire system to freeze, including peripherals.
>
> This patch patch marks this clock as critical,
On Mon, 2019-03-25 at 19:04 +0100, Martin Blumenstingl wrote:
> > Thanks for fixing this Martin.
> you're welcome!
>
> > As for the future enhancement, I'd like to know what you have in mind.
> > As I have told you previously, I think the clock bindings of this driver are
> > not great.
> >
> >
On Mon, 2019-03-25 at 10:10 -0700, Stephen Boyd wrote:
> Quoting Jerome Brunet (2019-03-25 04:11:57)
> > @@ -138,6 +129,27 @@ static int mpll_set_rate(struct clk_hw *hw,
> > return 0;
> > }
> >
> > +static void mpll_init(struct clk_hw *hw)
> >
Add the MPLL common register initial setting
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/g12a.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 6a01f8fd8114..493db74270ac 100644
--- a/drivers/clk/meson
Add the required init of each MPLL of the g12a.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/g12a.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index d3f53a9b97dc..6a01f8fd8114 100644
--- a/drivers/clk
are ongoing to explain and, hopefully, solve this as well.
Jerome Brunet (4):
clk: meson: mpll: add init callback and regs
clk: meson: g12a: add mpll register init sequences
clk: meson: eeclk: add init regs
clk: meson: g12a: add controller register init
drivers/clk/meson/clk-mpll.c| 33
magic settings need to applied on the mpll
register.
This change adds the ability to do that on the mpll driver.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/clk-mpll.c | 33 +++--
drivers/clk/meson/clk-mpll.h | 2 ++
2 files changed, 25 insertions(+), 10
-by: Jerome Brunet
---
drivers/clk/meson/meson-eeclk.c | 3 +++
drivers/clk/meson/meson-eeclk.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eeclk.c
index 37a34c9c3885..6ba2094be257 100644
--- a/drivers/clk/meson/meson-eeclk.c
+++ b
clock controller")
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/g12a.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 0e1ce8c03259..d3f53a9b97dc 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
up patch is always appreciated :) Before or after your changes, I don't
really mind. Up to you.
Acked-by: Jerome Brunet
>
> Testing:
> I have not tested this with Maxime's video decoder driver yet.
> However, I manually enabled and set various frequencies for the HCODEC
> clock and
lk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
> clk: meson: meson8b: add the VPU clock trees
>
> drivers/clk/meson/meson8b.c | 422 ++-
> drivers/clk/meson/meson8b.h | 12 +-
> include/dt-bindings/clock/meson8b-clkc.h | 1 +
> 3 files changed, 433 insertions(+), 2 deletions(-)
>
Looks sane.
Acked-by: Jerome Brunet
is requires
> meson_clk_pll_is_better() to work with the case where "now == rate".
>
> This fixes a hang during boot on Meson8b / Odroid-C1 for me.
>
> Fixes: 8eed1db1adec6a ("clk: meson: pll: update driver for the g12a")
> Signed-off-by: Martin Blumenstingl
Good catch !
Reviewed-by: Jerome Brunet
On Thu, 2019-03-14 at 17:37 +0100, Jerome Brunet wrote:
> The purpose of this patchset is to add drive-strength support in meson pinconf
> driver. This is a new feature that was added on the g12a. It is critical for
> us
> to support this since many functions are failing with default
On Sun, 2019-03-24 at 23:02 +0100, Martin Blumenstingl wrote:
> Back in January a "BUG: scheduling while atomic" error showed up during
> boot on my Meson8b Odroid-C1 (which uses a PWM regulator as CPU supply).
> The call trace comes down to:
> __mutex_lock
> clk_prepare_lock
>
ngs.
>
> Fixes: be3d960b0aeb ("dt-bindings: clk: add G12A AO Clock and Reset Bindings")
> Signed-off-by: Neil Armstrong
> ---
> drivers/clk/meson/g12a-aoclk.h | 1 -
> include/dt-bindings/clock/g12a-aoclkc.h | 1 +
> 2 files changed, 1 insertion(+), 1 deletion(-)
Acked-by: Jerome Brunet
> drivers/clk/meson/g12a.h | 5 +-
> include/dt-bindings/clock/g12a-clkc.h | 1 +
> 5 files changed, 150 insertions(+), 1 deletion(-)
Well this PLL is indeed a nasty one ;)
Acked-by: Jerome Brunet
On Thu, 2019-03-07 at 15:14 +0100, Neil Armstrong wrote:
> Add the PCIe reference clock feeding the USB3 + PCIE combo PHY.
>
> This PLL needs a very precise register sequence to permit to be locked,
> thus using the specific clk-pll pcie ops.
>
> The PLL is then followed by :
> - a fixed /2
meson-g12a: add cpu clock bindings
> clk: meson: g12a: add cpu clocks
>
> drivers/clk/meson/g12a.c | 350 ++
> drivers/clk/meson/g12a.h | 22 +-
> include/dt-bindings/clock/g12a-clkc.h | 1 +
> 3 files changed, 372 insertions(+), 1 deletion(-)
>
With the small naming comment on patch 2
Acked-by: Jerome Brunet
On Mon, 2019-03-04 at 14:11 +0100, Neil Armstrong wrote:
> Add the Amlogic G12A Family CPU Clock tree in read/only for now.
>
> The CPU clock can either use the SYS_PLL for > 1GHz frequencies or
> use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch
> muxes.
>
> Proper DVFS
On Fri, 2019-03-15 at 10:16 -0700, Stephen Boyd wrote:
> Quoting Jerome Brunet (2019-03-15 03:01:53)
> > On Tue, 2019-02-26 at 14:34 -0800, Stephen Boyd wrote:
> > > ---
> > > drivers/clk/clk.c| 260 ++-
> > >
t; 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Jerome Brunet
On Tue, 2019-03-19 at 09:50 +0100, Maxime Jourdan wrote:
A complete sentence would have been nice ;)
Add the video decoder clocks which are ...
> Mostly like meson-gx, except that the VDEC_HEVC clock is now split in two:
> HEVC and HEVCF.
>
> Signed-off-by: Maxime Jourdan
> ---
>
On Sun, 2019-03-17 at 17:14 +0100, Andrew Lunn wrote:
> On Thu, Mar 14, 2019 at 03:01:34PM +0100, Jerome Brunet wrote:
> > Add support for the mdio mux and internal phy glue of the g12a SoC family
> >
> > Signed-off-by: Jerome Brunet
> > ---
> > drivers/ne
... something to look at someday.
Jerome Brunet (2):
arm64: dts: meson: g12a: add secure monitor
arm64: dts: meson: g12a: add efuse
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 13 +
1 file changed, 13 insertions(+)
--
2.20.1
Add the interface to the secure monitor on g12a
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 31ddf9444b3e
Add the g12a SoC efuse device
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 92ee8c895ba6..dcc821cf35bb
e've always done before.
>
> Using either one of these new methods is entirely optional. Existing
> drivers will continue to work, and they can migrate to this new approach
> as they see fit. Eventually, we'll want to get rid of the 'parent_names'
> array in struct clk_init_da
From: Guillaume La Roque
Add optional drive-strength property
Signed-off-by: Guillaume La Roque
Signed-off-by: Jerome Brunet
---
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/meson
Roque
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson-g12a.c | 36 ++---
drivers/pinctrl/meson/pinctrl-meson.c | 166 -
drivers/pinctrl/meson/pinctrl-meson.h | 20 ++-
3 files changed, 162 insertions(+), 60 deletions(-)
diff --git a/drivers
The purpose of this patchset is to add drive-strength support in meson pinconf
driver. This is a new feature that was added on the g12a. It is critical for us
to support this since many functions are failing with default pad
drive-strength.
Now the slightly annoying part :(
The value achievable
Eventually, we'll want to get rid of the 'parent_names'
> array in struct clk_init_data and use one of these new methods instead.
>
Being able to specify parents from DT is great addition !!! Thx !
Overall, it looks good but with such big patch on framework is not easy get a
clear idea. I'll
if there no valid reason to do so)
* the actual clocks are removed. The fact that they exist is just the
result of an ugly hack. This will be resolved in CCF when we can
reference DT directly in parent table.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.h | 20
On Tue, 2019-01-29 at 10:56 -0800, Stephen Boyd wrote:
> > > +/**
> > > + * struct clk_parent_data - clk parent information
> > > + * @hw: parent clk_hw pointer (used for clk providers with internal
> > > clks)
> > > + * @name: parent name local to provider registering clk
> > > + * @fallback:
On Tue, 2019-02-05 at 16:01 -0800, Stephen Boyd wrote:
> Quoting Jerome Brunet (2019-01-31 10:40:07)
> > On Wed, 2019-01-30 at 13:30 -0800, Stephen Boyd wrote:
> > > > With this quirk, CCF is making an assumption that might be wrong.
> > > >
> > > >
lers
> - SARADC source and bus clock
> - Infrared Decoder/Encoder bus clock
> - USB 32K reference clock
>
> This also adds resets lines for :
> - Always-On UARTS & I2C Controllers
> - SARADC, Infrared Decoder/Encoder
>
> This patchset depends on the ("clk: meson
On Tue, 2019-02-12 at 15:23 +0100, Neil Armstrong wrote:
> This adds the G12A and G12B SoC ids and the S90X2 package ID.
^
Small typo here |
>
> Signed-off-by: Neil Armstrong
> ---
>
Add the peripheral clock controller to the g12a SoC DT
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index
Enable the g12a clock controller for ARCH_MESON
Signed-off-by: Jerome Brunet
---
arch/arm64/Kconfig.platforms | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 819e74ae9224..d0e0bd4af05d 100644
--- a/arch
This patchset selects the required configuration flag and adds the
DT node of the main clock controller for g12a SoC family.
FYI, the configuration flag and DT bindings have been introduced by
this series [0].
[0]: https://lkml.kernel.org/r/20190201145345.6795-1-jbru...@baylibre.com
Jerome
lers
> - SARADC source and bus clock
> - Infrared Decoder/Encoder bus clock
> - USB 32K reference clock
>
> This also adds resets lines for :
> - Always-On UARTS & I2C Controllers
> - SARADC, Infrared Decoder/Encoder
>
> This patchset depends on the ("clk: meson
On Mon, 2019-02-04 at 10:13 +0100, Neil Armstrong wrote:
> Add bindings for the Amlogic G12A AO Clock and Reset controllers.
>
> Signed-off-by: Neil Armstrong
> ---
> .../bindings/clock/amlogic,gxbb-aoclkc.txt| 1 +
> include/dt-bindings/clock/g12a-aoclkc.h | 43 +++
>
As pointed out in review, a few clock are not properly defined.
Reported-by: Martin Blumenstingl
Fixes: 2a4c63e080cd ("soc: amlogic: clk-measure: add axg and g12a support")
Signed-off-by: Jerome Brunet
---
drivers/soc/amlogic/meson-clk-measure.c | 8 +---
1 file changed, 5
The clk-msr node should be in cbus.
Fixes: eeca2cf15e05 ("arm64: dts: meson: g12a: add clk measure support")
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/aml
Hi Kevin,
Here are 2 fixup for the clock measure series.
First error was due to the rebase on the v2 of the bus fixup patch
Second address some comments Martin had on the initial submission
Feel free to fold these fixups with the related changes if you wish.
Jerome Brunet (2):
arm64: dts
fix undefined reference to `__aeabi_uldivmod' when dividing
u64 on arm32.
Fixes: 496c0462b46f ("clk: meson: pll: update driver for the g12a")
Signed-off-by: Jerome Brunet
---
Neil,
Feel free to squash this with the offending change. If you prefer,
I can submit a v7.
Chee
From: Jian Hu
Add the peripheral clock controller found in the g12a SoC family
Signed-off-by: Jian Hu
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/Kconfig | 12 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/clk-regmap.h |9
The function used to probe the peripheral clock controller of the arm64
amlogic SoCs is mostly the same. We now have 3 of those controllers so
it is time to factorize things a bit.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/Kconfig | 11 +-
drivers/clk/meson/Makefile | 1
ameter significantly faster since we don't have to try all the possible
settings.
Signed-off-by: Jerome Brunet
---
Side note:
You may notice that the g12a documentation says that the fractional
parameter of the hifi and gp0 pll is actually 19 bits long.
On older plls, frac was a ratio in the
From: Jian Hu
Add new clock controller compatible and dt-bindings header for the
Everything-Else domain of the g12a SoC
Reviewed-by: Rob Herring
Signed-off-by: Jian Hu
Signed-off-by: Jerome Brunet
---
.../bindings/clock/amlogic,gxbb-clkc.txt | 1 +
include/dt-bindings/clock/g12a
rg/r/1533890858-113020-1-git-send-email-jian...@amlogic.com
[5]:
https://lkml.kernel.org/r/1541511349-121152-1-git-send-email-jian...@amlogic.com
[6]:
https://lkml.kernel.org/r/1543498917-98605-1-git-send-email-jian...@amlogic.com
[7]: https://lkml.kernel.org/r/20190201125841.26785-1-jbru...@bayli
Fix apb, cbus, hiu and periph regions which are not aligned
with the documentation and the information provided by Amlogic
Fixes: 9c8c52f7cb4f ("arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT
support")
Cc: Jianxin Pan
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/aml
...@baylibre.com
Jerome Brunet (4):
clk: export some clk_hw function symbols for module drivers
clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory
clk: meson: axg-audio does not require syscon
clk: meson: rework and clean drivers dependencies
drivers/clk/Makefile
clk-provider.h provides clk_hw_is_prepared(), clk_hw_is_enabled() and
clk_hw_is_prepared() but these symbols are not exported for the
modules which prevents a clock driver using them to be compiled as
a module. Export them to fix the problem.
Acked-by: Stephen Boyd
Signed-off-by: Jerome Brunet
The axg audio clock controller uses regmap mmio, not syscon.
Fixes: 1cd50181750f ("clk: meson: axg: add the audio clock controller driver")
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/meson
.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/Kconfig | 82 +++---
drivers/clk/meson/Makefile| 27 ++--
drivers/clk/meson/axg-aoclk.c | 4 +-
drivers/clk/meson/axg-audio.c | 5 +-
drivers/clk/meson/axg.c
Use CONFIG_ARCH_MESON to let make enter the meson clock directory.
As part of a rework, CONFIG_COMMON_CLK_AMLOGIC is about to be removed.
Acked-by: Stephen Boyd
Signed-off-by: Jerome Brunet
---
drivers/clk/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk
Add device tree bindings for the reset controller of g12a SoC family.
Acked-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
Changes since v2 [0]:
* Dropped useless g12a compatible
[0]: https://lkml.kernel.org/r/20190128181316.30814-1-jbru...@baylibre.com
.../reset/amlogic,meson-g12a
On Wed, 2019-01-30 at 13:30 -0800, Stephen Boyd wrote:
> > With this quirk, CCF is making an assumption that might be wrong.
> >
> > The quirk is very easy put in the get_parent() callback of the said
> > driver, or
> > even better, don't provide the callback if it should not be called.
> >
> >
On Tue, 2019-01-29 at 13:15 -0800, Stephen Boyd wrote:
> > I suppose this is the answer the discussion we had last year. I'm not sure
> > it
> > answer the problem. In the case I presented, we have no idea wether the
> > setting is valid or not.
> >
> > We can't assume it is `at least something
On Tue, 2019-01-29 at 10:56 -0800, Stephen Boyd wrote:
> Quoting Jerome Brunet (2019-01-29 02:12:00)
> > On Mon, 2019-01-28 at 22:10 -0800, Stephen Boyd wrote:
> > > Using either one of these new methods is entirely optional. Existing
> > > drivers will continue to
On Tue, 2019-01-29 at 10:04 -0800, Stephen Boyd wrote:
> Quoting Jerome Brunet (2019-01-28 10:04:20)
> > Signed-off-by: Jerome Brunet
> > ---
>
> And also make clk-regmap.c a module? Having any commit text would be
> good.
Stephen,
As stated in the cover-letter, this p
ow will it work with debugfs: clock names are used to create the
directories in there, plus clk_summary will quickly get messy.
* How will it behave if 2 clock registers with "foo" and one clock register
with the fallback parent "foo" ?
>
>
> findable, an error pointer like EPROBE_DEFER if their parent provider
> hasn't probed yet but is valid, a NULL pointer if they can't find the
> clk but index is valid, and an error pointer with an appropriate error
> code otherwise.
>
> Cc: Miquel Raynal
> Cc: Jerome Brunet
Selecting COMMON_CLK_AMLOGIC is not required as it is already selected
by the SoC clock controller driver
Signed-off-by: Jerome Brunet
---
arch/arm64/Kconfig.platforms | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index
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