Hi Balakrishna,
On Wed, Dec 26, 2018 at 11:15:30AM +0530, Balakrishna Godavarthi wrote:
> Hi Matthias,
>
> On 2018-12-22 06:01, Matthias Kaehlcke wrote:
> > On Thu, Dec 20, 2018 at 08:16:36PM +0530, Balakrishna Godavarthi wrote:
> > > This patch will help to stop frame
Hi Taniya,
On Mon, Dec 24, 2018 at 12:29:18AM +0530, Taniya Das wrote:
> Hello Matthias,
>
> Thanks for your review comments.
>
> On 12/22/2018 2:27 AM, Matthias Kaehlcke wrote:
> > Hi Taniya,
> >
> > On Fri, Dec 21, 2018 at 11:36:48PM +0530, Taniya Das
On Thu, Dec 20, 2018 at 08:16:35PM +0530, Balakrishna Godavarthi wrote:
> wcn3990 requires a power pulse to turn ON/OFF along with
> regulators. Sometimes we are observing the power pulses are sent
> out with some time delay, due to queuing these commands. This is
> causing synchronization issues
st until host change its baudrate.
>
> Signed-off-by: Balakrishna Godavarthi
> Tested-by: Matthias Kaehlcke
> Reviewed-by: Matthias Kaehlcke
> ---
> drivers/bluetooth/hci_qca.c | 24 +---
> 1 file changed, 13 insertions(+), 11 deletions(-)
>
>
Hi Taniya,
On Fri, Dec 21, 2018 at 11:36:48PM +0530, Taniya Das wrote:
> Add support to read the voltage look up table and populate OPP for all
> corresponding CPUS.
>
> Signed-off-by: Taniya Das
> ---
> drivers/cpufreq/qcom-cpufreq-hw.c | 32 ++--
> 1 file changed,
On Fri, Dec 21, 2018 at 11:44:23PM +0530, Taniya Das wrote:
> This change adds the cpufreq node as per the bindings example for SDM845.
>
> Signed-off-by: Taniya Das
> Tested-by: Matthias Kaehlcke
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 19 +++
>
pufreq@17d43000 {
> + compatible = "qcom,cpufreq-hw";
> + reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
> + reg-names = "freq-domain0", "freq-domain1";
> +
> + clocks = < RPMH_CXO_CLK>, < GPLL0>;
> + clock-names = "xo", "alternate";
> +
> + #freq-domain-cells = <1>;
> + };
> +
> qfprom@784000 {
> compatible = "qcom,qfprom";
> reg = <0x784000 0x8ff>;
My understanding is that the entries in the SDM845 DT are sorted by
address. The address of the cpufreq node is 0x17d43000, hence it
should be the last entry of the 'soc' node, after 'timer@17c9'.
Tested-by: Matthias Kaehlcke
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd tag
---
Changes in v5:
- added missing return keyword in msm_dsi_pll_28nm_init()
- added "Reviewed-by: Stephen Boyd " tag
Cha
Add 'xo_board' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
---
Changes in v5:
- none
Changes in v4:
- added 'Reviewed-by: Stephen Boyd ' tag
Changes
Add 'xo_board' as ref clock for the DSI PHY, it was previously
hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
---
Changes in v5:
- none
Changes in v4:
- added 'Reviewed-by: Stephen Boyd ' tag
Changes in v3:
- patch added
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 10nm PHY
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v5:
- pass the ref clock name to _register
Allow the PHY drivers to get the ref clock from the DT.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
Reviewed-by: Rob Herring
---
Changes in v5:
- added "Reviewed-by: Rob Herring " tag
Changes in v4:
- added "Reviewed-by" tags f
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 14nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v5:
- pass the ref clock name to _register
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
---
Changes in v5:
- added "Reviewed-by: Stephen Boyd " tag
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate()
-
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
---
based on "[v6] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file"
:
- always use parent rate for 28nm and 28nm 8960 PHYs
Major changes in v3:
- keep supporting DTs without ref clock for the 28nm and the 28nm
8960 PHYs
- added patch to add ref clock to qcom-apq8064.dtsi
Major changes in v2:
- apply to all MSM DSI PHY drivers, not only 10nm
Matthias Kaehlcke (8
On Mon, Dec 10, 2018 at 07:51:19AM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-12-04 14:42:30)
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > index 71fe60e5f01f1..032bf3e8614bd 100644
> >
Hi Niklas,
On Wed, Dec 12, 2018 at 11:07:17PM +0100, Niklas Cassel wrote:
> On Tue, Dec 04, 2018 at 02:42:29PM -0800, Matthias Kaehlcke wrote:
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate.
> >
> > Signe
t and the property does not exist
> > or is invalid the controller is marked as unconfigured.
> >
> > Signed-off-by: Matthias Kaehlcke
> > Reviewed-by: Balakrishna Godavarthi
> > Tested-by: Balakrishna Godavarthi
> > ---
> > Changes in v2:
> > - adde
On Wed, Dec 19, 2018 at 10:49:26AM -0800, Evan Green wrote:
> On Wed, Dec 19, 2018 at 10:17 AM Matthias Kaehlcke wrote:
> >
> > Before commit a1fee899e5bed ("tty: serial: qcom_geni_serial: Fix
> > softlock") the size of TX transfers was limited to the TX
s are sent as if they were
actual data.
Handle wrap arounds of the TX buffer properly and ensure that words
written to the TX FIFO always contain valid data (unless the transfer
is completed).
Fixes: a1fee899e5bed ("tty: serial: qcom_geni_serial: Fix softlock")
Signed-off-by: Matthias Kaehlc
/ CLK_HW_DIV;
> + clk_put(clk);
> +
> + global_pdev = pdev;
> +
> + ret = cpufreq_register_driver(_qcom_hw_driver);
> + if (ret)
> + dev_err(>dev, "CPUFreq HW driver failed to register\n");
> + else
> + dev_dbg(>dev, "QCOM CPUFreq HW driver initialized\n");
> +
> + return ret;
> +}
> +
> +static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
> +{
> + return cpufreq_unregister_driver(_qcom_hw_driver);
> +}
> +
> +static const struct of_device_id qcom_cpufreq_hw_match[] = {
> + { .compatible = "qcom,cpufreq-hw" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
> +
> +static struct platform_driver qcom_cpufreq_hw_driver = {
> + .probe = qcom_cpufreq_hw_driver_probe,
> + .remove = qcom_cpufreq_hw_driver_remove,
> + .driver = {
> + .name = "qcom-cpufreq-hw",
> + .of_match_table = qcom_cpufreq_hw_match,
> + },
> +};
> +
> +static int __init qcom_cpufreq_hw_init(void)
> +{
> + return platform_driver_register(_cpufreq_hw_driver);
> +}
> +subsys_initcall(qcom_cpufreq_hw_init);
> +
> +static void __exit qcom_cpufreq_hw_exit(void)
> +{
> + platform_driver_unregister(_cpufreq_hw_driver);
> +}
> +module_exit(qcom_cpufreq_hw_exit);
> +
> +MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
> +MODULE_LICENSE("GPL v2");
Reviewed-by: Matthias Kaehlcke
+ dev_err(>dev, "CPUFreq HW driver failed to register\n");
> + else
> + dev_dbg(>dev, "QCOM CPUFreq HW driver initialized\n");
> +
> + return ret;
> +}
> +
> +static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
> +{
> + return cpufreq_unregister_driver(_qcom_hw_driver);
> +}
> +
> +static const struct of_device_id qcom_cpufreq_hw_match[] = {
> + { .compatible = "qcom,cpufreq-hw" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
> +
> +static struct platform_driver qcom_cpufreq_hw_driver = {
> + .probe = qcom_cpufreq_hw_driver_probe,
> + .remove = qcom_cpufreq_hw_driver_remove,
> + .driver = {
> + .name = "qcom-cpufreq-hw",
> + .of_match_table = qcom_cpufreq_hw_match,
> + },
> +};
> +
> +static int __init qcom_cpufreq_hw_init(void)
> +{
> + return platform_driver_register(_cpufreq_hw_driver);
> +}
> +subsys_initcall(qcom_cpufreq_hw_init);
> +
> +static void __exit qcom_cpufreq_hw_exit(void)
> +{
> + platform_driver_unregister(_cpufreq_hw_driver);
> +}
> +module_exit(qcom_cpufreq_hw_exit);
> +
> +MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
> +MODULE_LICENSE("GPL v2");
FWIW:
Reviewed-by: Matthias Kaehlcke
Hi Georgi,
not a full review, only one thing I just stumbled across:
On Fri, Dec 07, 2018 at 05:29:14PM +0200, Georgi Djakov wrote:
> From: David Dai
>
> Introduce Qualcomm SDM845 specific provider driver using the
> interconnect framework.
>
> Signed-off-by: David Dai
> Signed-off-by:
Hi Georgi,
not a full review, only one thing I just stumbled across:
On Fri, Dec 07, 2018 at 05:29:14PM +0200, Georgi Djakov wrote:
> From: David Dai
>
> Introduce Qualcomm SDM845 specific provider driver using the
> interconnect framework.
>
> Signed-off-by: David Dai
> Signed-off-by:
Hi Andy,
can this be landed or are any more changes needed?
Thanks
Matthias
On Wed, Oct 03, 2018 at 05:24:09PM -0700, Matthias Kaehlcke wrote:
> This adds nodes for all possible UARTs to sdm845.dtsi. By default
> only configure the RX/TX lines with pinctrl. Boards that use UARTs
>
Hi Andy,
can this be landed or are any more changes needed?
Thanks
Matthias
On Wed, Oct 03, 2018 at 05:24:09PM -0700, Matthias Kaehlcke wrote:
> This adds nodes for all possible UARTs to sdm845.dtsi. By default
> only configure the RX/TX lines with pinctrl. Boards that use UARTs
>
", 0,
> SCALE_HW_CALIB_THERM_100K_PULLUP)
> - [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 1,
> + [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 0,
>
", 0,
> SCALE_HW_CALIB_THERM_100K_PULLUP)
> - [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 1,
> + [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 0,
>
ot;, i,
> + freq, core_count);
> + }
nit: IMO it would be better to put the normal case ("core_count !=
max_cores") first and the exception in the else branch.
> +MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
nit: my suggestion was 'QCOM CPUFreq HW driver', which is what's used
elsewhere in the driver.
Anyway, no need to respin just for the nits, we can address them (or
not) with follow-up patches.
Reviewed-by: Matthias Kaehlcke
ot;, i,
> + freq, core_count);
> + }
nit: IMO it would be better to put the normal case ("core_count !=
max_cores") first and the exception in the else branch.
> +MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
nit: my suggestion was 'QCOM CPUFreq HW driver', which is what's used
elsewhere in the driver.
Anyway, no need to respin just for the nits, we can address them (or
not) with follow-up patches.
Reviewed-by: Matthias Kaehlcke
PHYs
- added patch to add ref clock to qcom-apq8064.dtsi
Major changes in v2:
- apply to all MSM DSI PHY drivers, not only 10nm
Matthias Kaehlcke (8):
dt-bindings: msm/dsi: Add ref clock for PHYs
drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT
drm/msm/dsi: 28nm PHY: Get ref clock from
PHYs
- added patch to add ref clock to qcom-apq8064.dtsi
Major changes in v2:
- apply to all MSM DSI PHY drivers, not only 10nm
Matthias Kaehlcke (8):
dt-bindings: msm/dsi: Add ref clock for PHYs
drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT
drm/msm/dsi: 28nm PHY: Get ref clock from
On Tue, Nov 27, 2018 at 09:56:46PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke wrote:
> >
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate.
>
> In the case of the 14nm P
On Tue, Nov 27, 2018 at 09:56:46PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke wrote:
> >
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate.
>
> In the case of the 14nm P
On Mon, Nov 26, 2018 at 04:09:50PM -0800, Matthias Kaehlcke wrote:
> On Thu, Nov 22, 2018 at 05:45:12PM +0530, Balakrishna Godavarthi wrote:
> > During initalization of wcn3990, we observed UART is reading some
> > stray bytes on the Rx line. This is logging Frame re
On Mon, Nov 26, 2018 at 04:09:50PM -0800, Matthias Kaehlcke wrote:
> On Thu, Nov 22, 2018 at 05:45:12PM +0530, Balakrishna Godavarthi wrote:
> > During initalization of wcn3990, we observed UART is reading some
> > stray bytes on the Rx line. This is logging Frame re
r it back once the initialization is done.
>
> Signed-off-by: Balakrishna Godavarthi
> Tested-by: Matthias Kaehlcke
> ---
> v2:
> * Updated commit text & comments.
> v1:
> * initial patch
> ---
> drivers/bluetooth/hci_qca.c | 18 ++
>
r it back once the initialization is done.
>
> Signed-off-by: Balakrishna Godavarthi
> Tested-by: Matthias Kaehlcke
> ---
> v2:
> * Updated commit text & comments.
> v1:
> * initial patch
> ---
> drivers/bluetooth/hci_qca.c | 18 ++
>
On Thu, Nov 22, 2018 at 10:37:08AM +0530, Viresh Kumar wrote:
> On 21-11-18, 14:06, Matthias Kaehlcke wrote:
> > On Wed, Nov 21, 2018 at 04:12:47PM +0530, Taniya Das wrote:
> > > + .boost_enabled = true,
> >
> > I have no real expertise with cpufreq boost, but a
On Thu, Nov 22, 2018 at 10:37:08AM +0530, Viresh Kumar wrote:
> On 21-11-18, 14:06, Matthias Kaehlcke wrote:
> > On Wed, Nov 21, 2018 at 04:12:47PM +0530, Taniya Das wrote:
> > > + .boost_enabled = true,
> >
> > I have no real expertise with cpufreq boost, but a
st until host change its baudrate.
Thanks for updating the commit message and provide more details!
> Signed-off-by: Balakrishna Godavarthi
> Tested-by: Matthias Kaehlcke
> ---
> v2:
> * updated commit text and comments.
> v1:
> * initial patch
> ---
> drivers/bluetoo
st until host change its baudrate.
Thanks for updating the commit message and provide more details!
> Signed-off-by: Balakrishna Godavarthi
> Tested-by: Matthias Kaehlcke
> ---
> v2:
> * updated commit text and comments.
> v1:
> * initial patch
> ---
> drivers/bluetoo
On Thu, Nov 22, 2018 at 05:45:10PM +0530, Balakrishna Godavarthi wrote:
> wcn3990 requires a power pulse to turn ON/OFF along with
> regulators. Sometimes we are observing the power pulses are sent
> out with some time delay, due to queuing these commands. This is
> causing synchronization issues
On Thu, Nov 22, 2018 at 05:45:10PM +0530, Balakrishna Godavarthi wrote:
> wcn3990 requires a power pulse to turn ON/OFF along with
> regulators. Sometimes we are observing the power pulses are sent
> out with some time delay, due to queuing these commands. This is
> causing synchronization issues
On Wed, Nov 21, 2018 at 04:12:47PM +0530, Taniya Das wrote:
> The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
> for changing the frequency of CPUs. The driver implements the cpufreq
> driver interface for this hardware engine.
>
> Signed-off-by: Saravana Kannan
>
On Wed, Nov 21, 2018 at 04:12:47PM +0530, Taniya Das wrote:
> The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
> for changing the frequency of CPUs. The driver implements the cpufreq
> driver interface for this hardware engine.
>
> Signed-off-by: Saravana Kannan
>
Hi Taniya,
thanks for respinning, a few nits inline.
On Wed, Nov 21, 2018 at 04:12:47PM +0530, Taniya Das wrote:
> The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
> for changing the frequency of CPUs. The driver implements the cpufreq
> driver interface for this
Hi Taniya,
thanks for respinning, a few nits inline.
On Wed, Nov 21, 2018 at 04:12:47PM +0530, Taniya Das wrote:
> The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
> for changing the frequency of CPUs. The driver implements the cpufreq
> driver interface for this
On Wed, Nov 21, 2018 at 04:12:46PM +0530, Taniya Das wrote:
> Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
> SoCs. This is required for managing the cpu frequency transitions which are
> controlled by the hardware engine.
>
> Signed-off-by: Taniya Das
> ---
>
On Wed, Nov 21, 2018 at 04:12:46PM +0530, Taniya Das wrote:
> Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
> SoCs. This is required for managing the cpu frequency transitions which are
> controlled by the hardware engine.
>
> Signed-off-by: Taniya Das
> ---
>
On Thu, Sep 27, 2018 at 02:22:53PM -0700, Matthias Kaehlcke wrote:
> The temperature information from the temp-alarm block itself is very
> coarse ("temperature is above/below trip points"). Provide the driver
> with the die temperature channel of the ADC on the PMIC for more
On Thu, Sep 27, 2018 at 02:22:53PM -0700, Matthias Kaehlcke wrote:
> The temperature information from the temp-alarm block itself is very
> coarse ("temperature is above/below trip points"). Provide the driver
> with the die temperature channel of the ADC on the PMIC for more
On Sun, Nov 11, 2018 at 06:12:29PM +0530, Taniya Das wrote:
> Hello Stephen,
>
> Thanks for your comments.
>
> On 11/4/2018 9:50 AM, Stephen Boyd wrote:
> > Quoting Taniya Das (2018-11-02 20:06:00)
> > > Hello Stephen,
> > >
> > > On 10/18/2018 5:02 AM, Stephen Boyd wrote:
> > > > Quoting
On Sun, Nov 11, 2018 at 06:12:29PM +0530, Taniya Das wrote:
> Hello Stephen,
>
> Thanks for your comments.
>
> On 11/4/2018 9:50 AM, Stephen Boyd wrote:
> > Quoting Taniya Das (2018-11-02 20:06:00)
> > > Hello Stephen,
> > >
> > > On 10/18/2018 5:02 AM, Stephen Boyd wrote:
> > > > Quoting
On Thu, Sep 20, 2018 at 10:12:53AM -0700, Matthias Kaehlcke wrote:
> sysrq_handle_crash() currently forces a crash by dereferencing a
> NULL pointer, which is undefined behavior in C. Just call panic()
> instead, which is simpler and doesn't depend on compiler specific
> handling of t
On Thu, Sep 20, 2018 at 10:12:53AM -0700, Matthias Kaehlcke wrote:
> sysrq_handle_crash() currently forces a crash by dereferencing a
> NULL pointer, which is undefined behavior in C. Just call panic()
> instead, which is simpler and doesn't depend on compiler specific
> handling of t
On Tue, Nov 06, 2018 at 03:09:40PM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-11-02 14:45:33)
> > Allow the 10nm PHY driver to get the ref clock from the DT.
> >
> > Signed-off-by: Matthias Kaehlcke
> > ---
> > Documentation/devicetree
On Tue, Nov 06, 2018 at 03:09:40PM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-11-02 14:45:33)
> > Allow the 10nm PHY driver to get the ref clock from the DT.
> >
> > Signed-off-by: Matthias Kaehlcke
> > ---
> > Documentation/devicetree
ow_control(hu, true);
> + host_set_baudrate(hu, 2400);
> serdev_device_write(serdev, , sizeof(cmd), 0);
> serdev_device_wait_until_sent(serdev, 0);
> hci_uart_set_flow_control(hu, false);
This change won't win a beauty price, but it seems it is needed to
suppress the 'frame reassembly' spam, unless the controller can be
convinced to stop sending garbage in the first place.
Tested-by: Matthias Kaehlcke
ow_control(hu, true);
> + host_set_baudrate(hu, 2400);
> serdev_device_write(serdev, , sizeof(cmd), 0);
> serdev_device_wait_until_sent(serdev, 0);
> hci_uart_set_flow_control(hu, false);
This change won't win a beauty price, but it seems it is needed to
suppress the 'frame reassembly' spam, unless the controller can be
convinced to stop sending garbage in the first place.
Tested-by: Matthias Kaehlcke
On Tue, Nov 06, 2018 at 06:44:07PM +0530, Balakrishna Godavarthi wrote:
> Hi Marcel,
>
> On 2018-11-06 18:32, Marcel Holtmann wrote:
> > Hi Balakrishna,
> >
> > > > > During hci down we are sending reset command to chip, which
> > > > > is not required for wcn3990, as hdev->shutdown() will turn
On Tue, Nov 06, 2018 at 06:44:07PM +0530, Balakrishna Godavarthi wrote:
> Hi Marcel,
>
> On 2018-11-06 18:32, Marcel Holtmann wrote:
> > Hi Balakrishna,
> >
> > > > > During hci down we are sending reset command to chip, which
> > > > > is not required for wcn3990, as hdev->shutdown() will turn
gt;hdev, "Set UART speed to %d", speed);
> ret = qca_set_baudrate(hu->hdev, qca_baudrate);
> @@ -1104,6 +1102,9 @@ static int qca_set_speed(struct hci_uart *hu, enum
> qca_speed_type speed_type)
> return ret;
>
> host_set_baudrate(hu, speed);
> +
> + if (qcadev->btsoc_type == QCA_WCN3990)
> + serdev_device_set_rts(hu->serdev, true);
> }
>
> return 0;
Tested-by: Matthias Kaehlcke
gt;hdev, "Set UART speed to %d", speed);
> ret = qca_set_baudrate(hu->hdev, qca_baudrate);
> @@ -1104,6 +1102,9 @@ static int qca_set_speed(struct hci_uart *hu, enum
> qca_speed_type speed_type)
> return ret;
>
> host_set_baudrate(hu, speed);
> +
> + if (qcadev->btsoc_type == QCA_WCN3990)
> + serdev_device_set_rts(hu->serdev, true);
> }
>
> return 0;
Tested-by: Matthias Kaehlcke
On Tue, Nov 06, 2018 at 05:35:25PM +0530, Balakrishna Godavarthi wrote:
> wcn3990 requires a power pulse to turn ON/OFF along with
> regulators. Sometimes we are observing the power pulses are sent
> out with some time delay, due to queuing these commands. This is
> causing synchronization issues
On Tue, Nov 06, 2018 at 05:35:25PM +0530, Balakrishna Godavarthi wrote:
> wcn3990 requires a power pulse to turn ON/OFF along with
> regulators. Sometimes we are observing the power pulses are sent
> out with some time delay, due to queuing these commands. This is
> causing synchronization issues
On Thu, Oct 25, 2018 at 03:43:39PM -0700, Matthias Kaehlcke wrote:
> Hi,
>
> On Tue, Oct 23, 2018 at 05:23:34PM +0530, Amit Kucheria wrote:
> > Hi Taniya,
> >
> > Both the patches are missing v9 in their subject line - this threw off
> > patchwork wh
On Thu, Oct 25, 2018 at 03:43:39PM -0700, Matthias Kaehlcke wrote:
> Hi,
>
> On Tue, Oct 23, 2018 at 05:23:34PM +0530, Amit Kucheria wrote:
> > Hi Taniya,
> >
> > Both the patches are missing v9 in their subject line - this threw off
> > patchwork wh
Add a channel node for the die temperature to the ADC.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v6:
- changed node name to 'adc-chan@'
Changes in v5:
- added unit address to 'die-temp' node
Changes in v4:
- none
Changes in v3:
- fixed separator in commit
Add a channel node for the die temperature to the ADC.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v6:
- changed node name to 'adc-chan@'
Changes in v5:
- added unit address to 'die-temp' node
Changes in v4:
- none
Changes in v3:
- fixed separator in commit
This series adds a channel for the die temperature to the QCOM SPMI
PMIC5 ADC. It also fixes an example in the DT documentation.
Matthias Kaehlcke (2):
dt-bindings: iio: vadc: Add unit address to ADC channel node in
example
arm64: dts: qcom: pm8998: Add die temperature channel node
This series adds a channel for the die temperature to the QCOM SPMI
PMIC5 ADC. It also fixes an example in the DT documentation.
Matthias Kaehlcke (2):
dt-bindings: iio: vadc: Add unit address to ADC channel node in
example
arm64: dts: qcom: pm8998: Add die temperature channel node
The node has a reg property, therefore its name should include a unit
address. Also change the name from 'usb_id_nopull' to 'adc-chan', which
is the preferred name for ADC channel nodes.
Include headers for constants used in the example.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas
The node has a reg property, therefore its name should include a unit
address. Also change the name from 'usb_id_nopull' to 'adc-chan', which
is the preferred name for ADC channel nodes.
Include headers for constants used in the example.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas
> +++ b/drivers/bluetooth/hci_qca.c
> @@ -1241,7 +1241,10 @@ static int qca_setup(struct hci_uart *hu)
> }
>
> /* Setup bdaddr */
> - hu->hdev->set_bdaddr = qca_set_bdaddr_rome;
> + if (qcadev->btsoc_type == QCA_WCN3990)
> + hu->hdev->set_bdaddr = qca_set_device_bdaddr;
> + else
> + hu->hdev->set_bdaddr = qca_set_bdaddr_rome;
>
> return ret;
> }
Reviewed-by: Matthias Kaehlcke
Tested-by: Matthias Kaehlcke
> +++ b/drivers/bluetooth/hci_qca.c
> @@ -1241,7 +1241,10 @@ static int qca_setup(struct hci_uart *hu)
> }
>
> /* Setup bdaddr */
> - hu->hdev->set_bdaddr = qca_set_bdaddr_rome;
> + if (qcadev->btsoc_type == QCA_WCN3990)
> + hu->hdev->set_bdaddr = qca_set_device_bdaddr;
> + else
> + hu->hdev->set_bdaddr = qca_set_bdaddr_rome;
>
> return ret;
> }
Reviewed-by: Matthias Kaehlcke
Tested-by: Matthias Kaehlcke
Hi,
On Tue, Oct 23, 2018 at 05:23:34PM +0530, Amit Kucheria wrote:
> Hi Taniya,
>
> Both the patches are missing v9 in their subject line - this threw off
> patchwork when trying to download the patches.
>
> On Thu, Oct 11, 2018 at 5:06 PM Taniya Das wrote:
> >
> > Add QCOM cpufreq firmware
Hi,
On Tue, Oct 23, 2018 at 05:23:34PM +0530, Amit Kucheria wrote:
> Hi Taniya,
>
> Both the patches are missing v9 in their subject line - this threw off
> patchwork when trying to download the patches.
>
> On Thu, Oct 11, 2018 at 5:06 PM Taniya Das wrote:
> >
> > Add QCOM cpufreq firmware
On Fri, Oct 26, 2018 at 01:33:40AM +0530, Amit Kucheria wrote:
> On Fri, Oct 26, 2018 at 12:55 AM Matthias Kaehlcke wrote:
> >
> > Hi Amit,
> >
> > vaguely related question, since you are working on SDM845 thermal
> > stuff: Do you have plans to add CPU coolin
On Fri, Oct 26, 2018 at 01:33:40AM +0530, Amit Kucheria wrote:
> On Fri, Oct 26, 2018 at 12:55 AM Matthias Kaehlcke wrote:
> >
> > Hi Amit,
> >
> > vaguely related question, since you are working on SDM845 thermal
> > stuff: Do you have plans to add CPU coolin
under development/review, but I wonder what the
path forward is.
Cheers
Matthias
On Wed, Sep 12, 2018 at 03:23:01PM +0530, Amit Kucheria wrote:
> One thermal zone per cpu is defined
>
> Signed-off-by: Amit Kucheria
> Reviewed-by: Matthias Kaehlcke
> Tested-by: Matthias Kaehlcke
under development/review, but I wonder what the
path forward is.
Cheers
Matthias
On Wed, Sep 12, 2018 at 03:23:01PM +0530, Amit Kucheria wrote:
> One thermal zone per cpu is defined
>
> Signed-off-by: Amit Kucheria
> Reviewed-by: Matthias Kaehlcke
> Tested-by: Matthias Kaehlcke
stra
Signed-off-by: Matthias Kaehlcke
---
kernel/sched/sched.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h
index 4a2e8cae63c4..b9387d35e261 100644
--- a/kernel/sched/sched.h
+++ b/kernel/sched/sched.h
@@ -1393,7 +1393,7 @@ st
stra
Signed-off-by: Matthias Kaehlcke
---
kernel/sched/sched.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h
index 4a2e8cae63c4..b9387d35e261 100644
--- a/kernel/sched/sched.h
+++ b/kernel/sched/sched.h
@@ -1393,7 +1393,7 @@ st
On Thu, Oct 11, 2018 at 05:06:00PM +0530, Taniya Das wrote:
> Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
> SoCs. This is required for managing the cpu frequency transitions which are
> controlled by the hardware engine.
>
> Signed-off-by: Taniya Das
> ---
>
On Thu, Oct 11, 2018 at 05:06:00PM +0530, Taniya Das wrote:
> Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
> SoCs. This is required for managing the cpu frequency transitions which are
> controlled by the hardware engine.
>
> Signed-off-by: Taniya Das
> ---
>
On Fri, Oct 12, 2018 at 10:15:23AM -0700, Matthias Kaehlcke wrote:
> On Fri, Oct 05, 2018 at 03:47:43PM -0500, Rob Herring wrote:
> > On Wed, Oct 03, 2018 at 05:14:31PM -0700, Matthias Kaehlcke wrote:
> > > The node has a reg property, therefore its name should include a
On Fri, Oct 12, 2018 at 10:15:23AM -0700, Matthias Kaehlcke wrote:
> On Fri, Oct 05, 2018 at 03:47:43PM -0500, Rob Herring wrote:
> > On Wed, Oct 03, 2018 at 05:14:31PM -0700, Matthias Kaehlcke wrote:
> > > The node has a reg property, therefore its name should include a
Hi Marcel,
On Tue, Oct 16, 2018 at 08:52:07AM +0200, Marcel Holtmann wrote:
> Hi Matthias,
>
> >> void bt_sock_reclassify_lock(struct sock *sk, int proto);
> >>
> >> +int device_get_bd_address(struct device *dev, bdaddr_t *bd_addr);
> >
> > Maybe change the API name to
Hi Marcel,
On Tue, Oct 16, 2018 at 08:52:07AM +0200, Marcel Holtmann wrote:
> Hi Matthias,
>
> >> void bt_sock_reclassify_lock(struct sock *sk, int proto);
> >>
> >> +int device_get_bd_address(struct device *dev, bdaddr_t *bd_addr);
> >
> > Maybe change the API name to
On Mon, Oct 15, 2018 at 08:06:02PM +0200, Marcel Holtmann wrote:
> Hi Matthias,
>
> void bt_sock_reclassify_lock(struct sock *sk, int proto);
>
> +int device_get_bd_address(struct device *dev, bdaddr_t *bd_addr);
> >>>
> >>> Maybe change the API name to start with bt_ and get
On Mon, Oct 15, 2018 at 08:06:02PM +0200, Marcel Holtmann wrote:
> Hi Matthias,
>
> void bt_sock_reclassify_lock(struct sock *sk, int proto);
>
> +int device_get_bd_address(struct device *dev, bdaddr_t *bd_addr);
> >>>
> >>> Maybe change the API name to start with bt_ and get
Hi Marcel,
please let me know if any changes are needed to get this patch applied
to bluetooth-next.
Thanks
Matthias
On Thu, Oct 04, 2018 at 10:33:38AM -0700, Matthias Kaehlcke wrote:
> On Thu, Sep 27, 2018 at 10:13:05AM -0700, Matthias Kaehlcke wrote:
> > On Thu, Sep 27, 2018 at 1
Hi Marcel,
please let me know if any changes are needed to get this patch applied
to bluetooth-next.
Thanks
Matthias
On Thu, Oct 04, 2018 at 10:33:38AM -0700, Matthias Kaehlcke wrote:
> On Thu, Sep 27, 2018 at 10:13:05AM -0700, Matthias Kaehlcke wrote:
> > On Thu, Sep 27, 2018 at 1
On Fri, Oct 05, 2018 at 03:47:43PM -0500, Rob Herring wrote:
> On Wed, Oct 03, 2018 at 05:14:31PM -0700, Matthias Kaehlcke wrote:
> > The node has a reg property, therefore its name should include a unit
> > address.
> >
> > Also change the name from 'usb_id_nopull' t
On Fri, Oct 05, 2018 at 03:47:43PM -0500, Rob Herring wrote:
> On Wed, Oct 03, 2018 at 05:14:31PM -0700, Matthias Kaehlcke wrote:
> > The node has a reg property, therefore its name should include a unit
> > address.
> >
> > Also change the name from 'usb_id_nopull' t
On Mon, Oct 08, 2018 at 10:57:24PM -0700, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-09-25 14:02:55)
> > Add a global binding for the 'aliases' node. This includes an initial list
> > of standardized alias names for some hardware components that are commonly
> &
On Mon, Oct 08, 2018 at 10:57:24PM -0700, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-09-25 14:02:55)
> > Add a global binding for the 'aliases' node. This includes an initial list
> > of standardized alias names for some hardware components that are commonly
> &
On Thu, Oct 11, 2018 at 12:11:34PM -0700, Matthias Kaehlcke wrote:
> Hi Rob,
>
> On Fri, Oct 05, 2018 at 03:47:43PM -0500, Rob Herring wrote:
> > On Wed, Oct 03, 2018 at 05:14:31PM -0700, Matthias Kaehlcke wrote:
> > > The node has a reg property, therefore its na
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