Osipenko
> Signed-off-by: Viresh Kumar
> ---
Any Fixes tag?
Reviewed-by: Stephen Boyd
Quoting Will Deacon (2020-10-26 06:25:33)
> On Fri, Oct 23, 2020 at 08:47:50AM -0700, Stephen Boyd wrote:
> > diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
> > index 15c706fb0a37..0e50ba3e88d7 100644
> > --- a/include/linux/arm-smccc.h
> > +++
rpenter
Signed-off-by: Stephen Boyd
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 5d33ad4d06f2..0cda16846962 100644
--- a/drivers/phy/qualcomm/phy-q
ning.
>
> Fixes: af776a3e1c30 ("drm/msm/dpu: add SM8250 to hw catalog")
> Signed-off-by: Arnd Bergmann
> ---
Reviewed-by: Stephen Boyd
("arm64: KVM: Propagate full Spectre v2 workaround state to
KVM guests")
Signed-off-by: Stephen Boyd
---
I see that before commit c118bbb52743 ("arm64: KVM: Propagate full
Spectre v2 workaround state to KVM guests") we had this mapping:
0 is SPECTRE_MITIGATED
SMCCC_RET_NOT
Rikard Falkeborn (1):
clk: pxa: Constify static struct clk_ops
Serge Semin (1):
clk: baikal-t1: Mark Ethernet PLL as critical
Stefan Agner (1):
clk: meson: g12a: mark fclk_div2 as critical
Stephen Boyd (14):
Merge tag 'clk-renesas-for-v5.10-tag2' of
git://git.kerne
Steven Price
Cc: Marc Zyngier
Cc: sta...@vger.kernel.org
Link: https://developer.arm.com/documentation/den0028/latest [1]
Fixes: c118bbb52743 ("arm64: KVM: Propagate full Spectre v2 workaround state to
KVM guests")
Signed-off-by: Stephen Boyd
---
I see that before commit c118bbb52743 (&qu
Quoting Will Deacon (2020-10-21 14:13:26)
> On Wed, Oct 21, 2020 at 09:12:02AM -0700, Stephen Boyd wrote:
>
> > My read of the spec was that the intent is to remove the call at some
> > point and have the removal of the call mean that it isn't vulnerable.
>
> No, t
Quoting Will Deacon (2020-10-21 08:49:09)
> On Wed, Oct 21, 2020 at 08:23:54AM -0700, Stephen Boyd wrote:
> >
> > If I'm reading the TF-A code correctly it looks like this will return
> > SMC_UNK if the platform decides that "This flag can be set to 0 by the
> &g
Quoting Will Deacon (2020-10-21 00:57:23)
> On Tue, Oct 20, 2020 at 02:45:43PM -0700, Stephen Boyd wrote:
> > According to the SMCCC spec (7.5.2 Discovery) the
> > ARM_SMCCC_ARCH_WORKAROUND_1 function id only returns 0, 1, and
> > SMCCC_RET_NOT_SUPPORTED corresponding to
Quoting Kuogee Hsieh (2020-10-20 09:59:59)
> No need to check LINK_STATuS_UPDATED bit before
LINK_STATUS_UPDATED?
> return 6 bytes of link status during link training.
Why?
> This patch also fix phy compliance test link rate
> conversion error.
How?
>
> Signed-off-by: Kuogee Hsieh
> ---
An
The function detect_harden_bp_fw() is gone after commit d4647f0a2ad7
("arm64: Rewrite Spectre-v2 mitigation code"). Update this comment to
reflect the new state of affairs.
Cc: Marc Zyngier
Fixes: d4647f0a2ad7 ("arm64: Rewrite Spectre-v2 mitigation code")
Signed-off-by: Ste
m64: KVM: Propagate full Spectre v2 workaround state to
KVM guests")
Fixes: 73f381660959 ("arm64: Advertise mitigation of Spectre-v2, or lack
thereof")
Signed-off-by: Stephen Boyd
---
This will require a slightly different backport to stable kernels, but
at least it looks like
The first patch fixes a problem with spectre-v2 detection in guest
kernels found on v5.4 and the second patch fixes an outdated comment.
Cc: Andre Przywara
Cc: Steven Price
Cc: Marc Zyngier
Cc: sta...@vger.kernel.org
Stephen Boyd (2):
arm64: ARM_SMCCC_ARCH_WORKAROUND_1 doesn't r
Quoting Abel Vesa (2020-10-15 02:25:44)
> According to the latest RM (see Table 5-1. Clock Root Table),
> both usdhc root clocks have the parent order as follows:
>
> 000 - 25M_REF_CLK
> 001 - SYSTEM_PLL1_DIV2
> 010 - SYSTEM_PLL1_CLK
> 011 - SYSTEM_PLL2_DIV2
> 100 - SYSTEM_PLL3_CLK
> 101 - SYSTEM_
Quoting Stephen Boyd (2020-10-16 19:01:37)
> If the GDSC is enabled out of boot but doesn't have the retain ff bit
> set we will get confusing results where the registers that are powered
> by the GDSC lose their contents on the first power off of the GDSC but
> thereafter
Quoting Srinivas Kandagatla (2020-10-16 07:12:37)
> This patchset adds support for GFM Muxes found in LPASS
> (Low Power Audio SubSystem) IP in Audio Clock Controller
> and Always ON clock controller.
>
> Clocks derived from these muxes are consumed by LPASS Digital Codec.
> Currently the driver f
Quoting Doug Anderson (2020-10-16 20:17:56)
>
> I'm happy to repost a v5 of just patches #1 and #2 with the newlines
> fixed next week, or I'm happy if you want to fix them when applying as
> you alluded to on the Chrome OS gerrit.
Please resend. Thanks!
Quoting Stephen Boyd (2020-10-15 20:16:27)
> Quoting Douglas Anderson (2020-10-14 17:13:29)
> > From: Taniya Das
> >
> > In the case where the PLL configuration is lost, then the pm runtime
> > resume will reconfigure before usage.
>
> Taniya, this commit nee
e a
noise) but critically doesn't set the RETAIN_FF bit.
Cc: Douglas Anderson
Cc: Taniya Das
Cc: Rajendra Nayak
Fixes: 173722995cdb ("clk: qcom: gdsc: Add support to enable retention of
GSDCR")
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gdsc.c | 8
1 file changed, 8
gt;
> Fixes: 50e99641413e7 ("soc: qcom: smp2p: Qualcomm Shared Memory Point to
> Point")
> Signed-off-by: Evan Green
> ---
Reviewed-by: Stephen Boyd
Quoting Douglas Anderson (2020-10-14 17:13:29)
> From: Taniya Das
>
> In the case where the PLL configuration is lost, then the pm runtime
> resume will reconfigure before usage.
Taniya, this commit needs a lot more describing than one sentence. I see
that the PLL's L value is reset at boot, but
> makes the functions a little easier to understand. Decreasing the
> amount of times we read/write memory mapped registers is also nice,
> even if we are using "relaxed" variants.
>
> Signed-off-by: Douglas Anderson
> ---
Reviewed-by: Stephen Boyd
Quoting Douglas Anderson (2020-10-14 14:05:23)
> diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c
> b/drivers/clk/qcom/lpasscorecc-sc7180.c
> index 48d370e2108e..e12d4c2b1b70 100644
> --- a/drivers/clk/qcom/lpasscorecc-sc7180.c
> +++ b/drivers/clk/qcom/lpasscorecc-sc7180.c
> @@ -388,6 +388,25 @@
Quoting Doug Anderson (2020-10-14 16:07:52)
> Hi,
>
> On Wed, Oct 14, 2020 at 4:00 PM Stephen Boyd wrote:
> >
> > Quoting Doug Anderson (2020-10-14 15:28:58)
> > > Hi,
> > >
> > > On Wed, Oct 14, 2020 at 3:10 PM Stephen Boyd wrote:
> > >
Quoting Doug Anderson (2020-10-14 15:28:58)
> Hi,
>
> On Wed, Oct 14, 2020 at 3:10 PM Stephen Boyd wrote:
> >
> > Quoting Douglas Anderson (2020-10-14 14:05:22)
> > > diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c
> > > b/drivers/clk/qcom/lpassc
Quoting Douglas Anderson (2020-10-14 14:05:22)
> diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c
> b/drivers/clk/qcom/lpasscorecc-sc7180.c
> index abcf36006926..48d370e2108e 100644
> --- a/drivers/clk/qcom/lpasscorecc-sc7180.c
> +++ b/drivers/clk/qcom/lpasscorecc-sc7180.c
> @@ -356,12 +356,48 @
Quoting Greg Kroah-Hartman (2020-10-03 03:56:53)
> On Fri, Oct 02, 2020 at 02:22:17PM -0700, Stephen Boyd wrote:
> > Quoting Mauro Carvalho Chehab (2020-09-28 23:22:11)
> > > Hi Stephen,
> > >
> > > While double-checking against yesterday's linux-nex
Quoting Jing Xiangfeng (2020-07-27 23:18:46)
> _ti_omap4_clkctrl_setup() misses to call kfree() in an error path. Jump
> to cleanup to fix it.
>
> Fixes: 6c3090520554 ("clk: ti: clkctrl: Fix hidden dependency to node name")
> Signed-off-by: Jing Xiangfeng
> ---
> drivers/clk/ti/clkctrl.c | 2 +-
Quoting Joel Stanley (2020-10-13 22:28:00)
> On Wed, 14 Oct 2020 at 02:50, Stephen Boyd wrote:
> >
> > Quoting Ryan Chen (2020-09-28 00:01:08)
> > > In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
> > > default for Host SuperIO UART d
Quoting Claudiu Beznea (2020-10-14 07:34:32)
> According to datasheet (Chapter 29.16.13, PMC Programmable Clock Register)
> there are only two programmable clocks on SAM9X60.
>
> Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
> Signed-off-by: Claudiu Beznea
> ---
Applied to clk-next
Quoting Douglas Anderson (2020-10-14 08:58:24)
> diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c
> b/drivers/clk/qcom/lpasscorecc-sc7180.c
> index 228d08f5d26f..ee23eb5b9bf2 100644
> --- a/drivers/clk/qcom/lpasscorecc-sc7180.c
> +++ b/drivers/clk/qcom/lpasscorecc-sc7180.c
> @@ -356,6 +356,25 @@
ses link training failed
>
> Signed-off-by: Kuogee Hsieh
> ---
Can we add some sort of Fixes tag? Maybe the beginning of this DP driver
support?
Tested-by: Stephen Boyd
also replace ST_SUSPEND_PENDING with ST_DISPLAY_OFF.
>
> Changes in V2:
> -- Add more information to commit message.
>
> Changes in V3:
> -- change base
>
> Signed-off-by: Kuogee Hsieh
> ---
Any Fixes tag?
Tested-by: Stephen Boyd
Quoting Paul Cercueil (2020-09-02 18:50:44)
> The to_clk_info() previously had a BUG_ON() to check that it was only
> called for PLL clocks. Yet, all the other clocks were doing the exact
> same thing the macro does, in-line.
>
> Move the to_clk_info() macro to the top of the file, remove the
> ha
Quoting Paul Cercueil (2020-09-02 18:50:45)
> Use the readl_poll_timeout() function instead of rolling our own
> busy-wait loops. This makes the code simpler.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
Quoting Paul Cercueil (2020-09-02 18:50:47)
> The custom clocks have custom functions to round, get or set their rate.
> Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
Quoting Paul Cercueil (2020-09-02 18:50:46)
> CLK_SET_RATE_GATE means that the clock must be gated when being
> reclocked. This is not the case for the PLLs in Ingenic SoCs.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
Quoting Paul Cercueil (2020-09-02 18:50:48)
> Clocks that don't have a divider are in our case all marked with the
> CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation
> should modify the value pointed to by parent_rate, in order to propagate
> the rate change to the parent, as
Quoting Navid Emamdoost (2020-08-09 16:11:58)
> In the implementation of bcm2835_register_pll(), the allocated pll is
> leaked if devm_clk_hw_register() fails to register hw. Release pll if
> devm_clk_hw_register() fails.
>
> Signed-off-by: Navid Emamdoost
> ---
Applied to clk-next
Quoting Claudiu Beznea (2020-08-24 23:59:11)
> Fix variable set but not used compilation warning.
>
> Fixes: 43b1bb4a9b3e ("clk: at91: clk-sam9x60-pll: re-factor to support plls
> with multiple outputs")
> Reported-by: kernel test robot
> Signed-off-by: Claudiu Beznea
> ---
Applied to clk-next
Quoting Claudiu Beznea (2020-08-24 23:59:09)
> There is no need to check parent_name variable while assigning it to
> init.parent_names. parent_name variable is already checked at
> the beginning of at91_clk_register_peripheral() function.
>
> Fixes: 6114067e437eb ("clk: at91: add PMC peripheral c
Quoting Claudiu Beznea (2020-08-24 23:59:10)
> SAMA5D2 datasheet specifies on chapter 33.22.8 (PMC Clock Generator
> Main Oscillator Register) that writing any value other than
> 0x37 on KEY field aborts the write operation. Use the key when
> selecting main clock parent.
>
> Fixes: 27cb1c2083373
Quoting Xu Wang (2020-09-20 20:45:22)
> In case of error, the function clk_register() returns ERR_PTR()
> and never returns NULL. The NULL test in the return value check
> should be replaced with IS_ERR().
>
> Signed-off-by: Xu Wang
> ---
Applied to clk-next
Quoting Lubomir Rintel (2020-09-25 16:39:14)
> The LCD clock dividers are apparently based on one. No datasheet,
> determined empirically, but seems to be confirmed by line 19 of lcd.fth in
> OLPC laptop's Open Firmware [1]:
>
>h# 0700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz
>
>
Quoting Ryan Chen (2020-09-28 00:01:08)
> In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
> default for Host SuperIO UART device, eSPI clk for Host eSPI bus access
> eSPI slave channel, those clks can't be disable should keep default,
> otherwise will affect Host side access
Quoting Qiang Zhao (2020-09-15 20:03:10)
> From: Zhao Qiang
>
> On LS2088A, Watchdog need clk divided by 32,
> so modify MAX_PLL_DIV to 32
>
> Signed-off-by: Zhao Qiang
> ---
Applied to clk-next
Quoting Serge Semin (2020-09-20 04:03:35)
> We've discovered that disabling the so called Ethernet PLL causes reset of
> the devices consuming its outgoing clock. The resets happen automatically
> even if each underlying clock gate is turned off. Due to that we can't
> disable the Ethernet PLL unti
Quoting Alexandru Ardelean (2020-10-01 01:59:47)
> From: Lars-Peter Clausen
>
> The axi-clkgen has (optional) fractional dividers on the output clock
> divider and feedback clock divider path. Utilizing the fractional dividers
> allows for a better resolution of the output clock, being able to
>
Quoting Alexandru Ardelean (2020-10-01 01:59:48)
> From: Lars-Peter Clausen
>
> Using the fractional dividers requires some additional power bits to be
> set.
>
> The fractional power bits are not documented and the current heuristic
> for setting them seems be insufficient for some cases. Just
tof Kozlowski
> ---
Reviewed-by: Stephen Boyd
Quoting Krzysztof Kozlowski (2020-10-01 09:56:46)
> diff --git a/drivers/clk/samsung/clk-exynos-clkout.c
> b/drivers/clk/samsung/clk-exynos-clkout.c
> index 34ccb1d23bc3..68af082d4716 100644
> --- a/drivers/clk/samsung/clk-exynos-clkout.c
> +++ b/drivers/clk/samsung/clk-exynos-clkout.c
> @@ -28,41
Can you check your get_maintainers script invocation? Not sure why arm64
maintainers are Cced on a clk patch.
Quoting Varadarajan Narayanan (2020-09-27 22:15:34)
> Add programming sequence support for managing the Stromer
> PLLs.
>
> Signed-off-by: Varadarajan Narayanan
> ---
> drivers/clk/qcom
Quoting Varadarajan Narayanan (2020-09-27 22:15:36)
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 0583273..d1a2504 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -155,6 +155,14 @@ config IPQ_GCC_8074
> i2c, USB, SD/eMMC, etc. Sel
Quoting Taniya Das (2020-10-13 10:11:49)
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml
> b/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml
> new file mode 100644
> index 000..07bd38e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/
Quoting Taniya Das (2020-10-13 10:11:48)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c
> b/drivers/clk/qcom/clk-alpha-pll.c
> index 26139ef..17e1fc0 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -1561,3 +1571,73 @@ const struct clk_ops clk_alpha_pl
Quoting Taniya Das (2020-10-13 10:11:50)
> diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
> new file mode 100644
> index 000..e954d21
> --- /dev/null
> +++ b/drivers/clk/qcom/camcc-sc7180.c
> @@ -0,0 +1,1737 @@
[...]
> +
> +enum {
> + P_BI_TCXO,
> + P
Quoting Srinivas Kandagatla (2020-09-25 03:31:14)
> GFM Muxes in AUDIO_CC control clocks to LPASS WSA and RX Codec Macros.
> This patch adds support to these muxes.
>
> Signed-off-by: Srinivas Kandagatla
> ---
> drivers/clk/qcom/Kconfig| 6 +
> drivers/clk/qcom/Makefile |
Quoting Srinivas Kandagatla (2020-09-25 03:31:11)
> This patchset adds support for GFM Muxes found in LPASS
> (Low Power Audio SubSystem) IP in Audio Clock Controller
> and Always ON clock controller.
>
> Clocks derived from these muxes are consumed by LPASS Digital Codec.
> Currently the driver f
Quoting Jonathan Marek (2020-09-27 12:06:51)
> Add support for the display clock controller found on SM8150 and SM8250.
>
> Signed-off-by: Jonathan Marek
> Tested-by: Dmitry Baryshkov (SM8250)
> ---
Applied to clk-next
Quoting Jonathan Marek (2020-09-27 12:06:50)
> Add device tree bindings for display clock controller for
> Qualcomm Technology Inc's SM8150 and SM8250 SoCs.
>
> Signed-off-by: Jonathan Marek
> Tested-by: Dmitry Baryshkov (SM8250)
> ---
Applied to clk-next
Quoting Jonathan Marek (2020-09-23 09:06:30)
> Add support for the video clock controller found on SM8150 based devices.
>
> Derived from the downstream driver.
>
> Signed-off-by: Jonathan Marek
> ---
Applied to clk-next
Quoting Jonathan Marek (2020-09-23 09:06:29)
> Add device tree bindings for video clock controller for SM8250 SoCs.
>
> Signed-off-by: Jonathan Marek
> Reviewed-by: Rob Herring
> ---
Applied to clk-next
Quoting Jonathan Marek (2020-09-23 09:06:31)
> Add support for the video clock controller found on SM8250 based devices.
>
> Derived from the downstream driver.
>
> Signed-off-by: Jonathan Marek
> ---
Applied to clk-next
Quoting Jonathan Marek (2020-09-23 09:06:27)
> These two bindings are almost identical, so combine them into one. This
> will make it easier to add the sm8150 and sm8250 videocc bindings.
>
> Signed-off-by: Jonathan Marek
> Reviewed-by: Rob Herring
> ---
Applied to clk-next
Quoting Jonathan Marek (2020-09-23 09:06:28)
> Add device tree bindings for video clock controller for SM8150 SoCs.
>
> Signed-off-by: Jonathan Marek
> Reviewed-by: Rob Herring
> ---
Applied to clk-next
Quoting Konrad Dybcio (2020-10-05 07:58:55)
> This change adds GDSCs, resets and most of the missing
> clocks to the msm8994 GCC driver. The remaining ones
> are of local_vote_clk and gate_clk type, which are not
> yet supported upstream. Also reorder them to match the
> original downstream driver.
Quoting Julia Lawall (2020-09-27 12:12:19)
> Replace commas with semicolons. What is done is essentially described by
> the following Coccinelle semantic patch (http://coccinelle.lip6.fr/):
>
> //
> @@ expression e1,e2; @@
> e1
> -,
> +;
> e2
> ... when any
> //
>
> Signed-off-by: Julia Lawall
Quoting Julia Lawall (2020-09-27 12:12:20)
> Replace commas with semicolons. What is done is essentially described by
> the following Coccinelle semantic patch (http://coccinelle.lip6.fr/):
>
> //
> @@ expression e1,e2; @@
> e1
> -,
> +;
> e2
> ... when any
> //
>
> Signed-off-by: Julia Lawall
Quoting Julia Lawall (2020-09-27 12:12:11)
> Replace commas with semicolons. What is done is essentially described by
> the following Coccinelle semantic patch (http://coccinelle.lip6.fr/):
>
> //
> @@ expression e1,e2; @@
> e1
> -,
> +;
> e2
> ... when any
> //
>
> Signed-off-by: Julia Lawall
Quoting Wang Qing (2020-09-23 23:55:04)
> Modify the comment typo: "compliment" -> "complement".
>
> Signed-off-by: Wang Qing
> ---
Applied to clk-next
Quoting Paul Cercueil (2020-09-25 05:29:12)
> >> +static int ingenic_drm_update_pixclk(struct notifier_block *nb,
> >> +unsigned long action,
> >> +void *data)
> >> +{
> >> + struct ingenic_drm *priv = drm_nb_get_priv(nb);
> >>
Quoting Fabien Parent (2020-09-18 06:23:03)
> Add the following clock support for MT8167 SoC: topckgen, apmixedsys,
> infracfg, audsys, imgsys, mfgcfg, vdecsys.
>
> Signed-off-by: Fabien Parent
> ---
Applied to clk-next
Quoting Fabien Parent (2020-09-18 06:23:02)
> Add binding documentation for topckgen, apmixedsys, infracfg, audsys,
> imgsys, mfgcfg, vdecsys on MT8167 SoC.
>
> Signed-off-by: Fabien Parent
> Reviewed-by: Rob Herring
> ---
Applied to clk-next
Quoting Mauro Carvalho Chehab (2020-10-09 05:15:30)
> Several *.txt files got converted to yaml. Update their
> references at MAINTAINERS file accordingly.
>
> Signed-off-by: Mauro Carvalho Chehab
> ---
Acked-by: Stephen Boyd
in mainline is i2c.
>
> Fixes: 37692de5d523 ("i2c: i2c-qcom-geni: Add bus driver for the Qualcomm
> GENI I2C controller")
> Fixes: 02b9aec59243 ("i2c: i2c-qcom-geni: Fix DMA transfer race")
> Signed-off-by: Douglas Anderson
> ---
Reviewed-by: Stephen B
lems!
>
> To be explicit, the patch ("soc: qcom: geni: More properly switch
> to DMA mode") is a prerequisite for this one.
>
> Fixes: 02b9aec59243 ("i2c: i2c-qcom-geni: Fix DMA transfer race")
> Signed-off-by: Douglas Anderson
> ---
Reviewed-by: Stephen Boyd
Quoting Douglas Anderson (2020-10-08 15:52:35)
> diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
> index 751a49f6534f..746854745b15 100644
> --- a/drivers/soc/qcom/qcom-geni-se.c
> +++ b/drivers/soc/qcom/qcom-geni-se.c
> @@ -266,49 +266,53 @@ EXPORT_SYMBOL(geni_se_ini
+Roja
Quoting Douglas Anderson (2020-10-08 15:52:32)
> Previously I landed commit 02b9aec59243 ("i2c: i2c-qcom-geni: Fix DMA
> transfer race") to fix a race we were seeing. While that most
> definitely fixed the race we were seeing, it looks like it causes
> problems in the TX path, which we didn
Quoting Hanks Chen (2020-07-30 06:30:16)
> Add MT6779 UART0 clock support.
>
> Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
> Signed-off-by: Wendell Lin
> Signed-off-by: Hanks Chen
> Reviewed-by: Matthias Brugger
> ---
Applied to clk-next
Quoting Hanks Chen (2020-10-07 19:39:13)
> On Wed, 2020-10-07 at 19:00 -0700, Stephen Boyd wrote:
> > Quoting Hanks Chen (2020-10-03 03:06:47)
> > > Hi Michael & Stephen,
> > >
> > > Please kindly let me know your comments about this patch.
> > >
Quoting Hanks Chen (2020-10-03 03:06:47)
> Hi Michael & Stephen,
>
> Please kindly let me know your comments about this patch.
> Thanks
>
What's the base for this patch? I tried applying to v5.9-rc1 and it
didn't work.
Quoting Jerome Brunet (2020-09-28 02:47:24)
>
> On Sun 27 Sep 2020 at 21:12, Julia Lawall wrote:
>
> Hi Stephen,
>
> Do you want to take all the clock related patches directly ?
>
>
Sure that's fine.
Green
Signed-off-by: Stephen Boyd
---
drivers/iio/proximity/sx9310.c | 125 -
1 file changed, 124 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/proximity/sx9310.c b/drivers/iio/proximity/sx9310.c
index 3f909177eca9..23aa235ac2b6 100644
--- a/drivers/iio
more patches for userspace settings
- Removed body thresholds as they're probably not used
- Removed compensate common as it probably doesn't matter
- Moved thresholds, gain factor, hysteresis, debounce to userspace
Stephen Boyd (6):
iio: sx9310: Support hardware gain factor
iio:
al Grignou
Cc: Evan Green
Signed-off-by: Stephen Boyd
---
drivers/iio/proximity/sx9310.c | 100 +
1 file changed, 100 insertions(+)
diff --git a/drivers/iio/proximity/sx9310.c b/drivers/iio/proximity/sx9310.c
index 9eb10e8263e7..3f909177eca9 100644
--- a/drivers/ii
Add support to set the proximity thresholds for each channel.
Cc: Daniel Campello
Cc: Lars-Peter Clausen
Cc: Peter Meerwald-Stadler
Cc: Douglas Anderson
Cc: Gwendal Grignou
Cc: Evan Green
Signed-off-by: Stephen Boyd
---
drivers/iio/proximity/sx9310.c | 114
Add support to set the hardware gain of the channels as a multiplier of
2x, 4x, or 8x.
Cc: Daniel Campello
Cc: Lars-Peter Clausen
Cc: Peter Meerwald-Stadler
Cc: Douglas Anderson
Cc: Gwendal Grignou
Cc: Evan Green
Signed-off-by: Stephen Boyd
---
drivers/iio/proximity/sx9310.c | 109
n the channel's proximity threshold. This is sort of odd but
seems to work in practice as most of the time only one channel is used.
Cc: Daniel Campello
Cc: Lars-Peter Clausen
Cc: Peter Meerwald-Stadler
Cc: Douglas Anderson
Cc: Gwendal Grignou
Cc: Evan Green
Signed-off-by: Stephen Boyd
--
Anderson
Cc: Gwendal Grignou
Cc: Evan Green
Signed-off-by: Stephen Boyd
---
.../iio/proximity/semtech,sx9310.yaml | 63 +++
1 file changed, 63 insertions(+)
diff --git
a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9310.yaml
b/Documentation/devicetree
Quoting Rajendra Nayak (2020-10-06 00:31:41)
>
> On 10/4/2020 3:56 AM, Kuogee Hsieh wrote:
> > Set link rate by using OPP set rate api so that CX level will be set
> > accordingly based on the link rate.
> >
> > Changes in v2:
> > -- remove dev from dp_ctrl_put() parameters
> > -- address review
Quoting khs...@codeaurora.org (2020-10-05 11:02:10)
> >> + dp_del_event(dp_display, EV_DISCONNECT_PENDING_TIMEOUT);
> >> +
> >> dp_display_disable(dp_display, 0);
> >>
> >> rc = dp_display_unprepare(dp);
> >> if (rc)
> >> DRM_ERROR("DP display unprepar
Quoting Kuogee Hsieh (2020-10-02 15:09:19)
> Connection state is set incorrectly happen at either failure of link train
> or cable plugged in while suspended. This patch fixes these problems.
> This patch also replace ST_SUSPEND_PENDING with ST_DISPLAY_OFF.
>
> Signed-off-by: Kuogee Hsieh
Any Fi
Quoting Roja Rani Yarubandi (2020-10-01 01:44:25)
> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c
> b/drivers/i2c/busses/i2c-qcom-geni.c
> index aee2a1dd2c62..56d3fbfe7eb6 100644
> --- a/drivers/i2c/busses/i2c-qcom-geni.c
> +++ b/drivers/i2c/busses/i2c-qcom-geni.c
> @@ -380,6 +380,36 @@ static v
y: Roja Rani Yarubandi
> ---
Reviewed-by: Stephen Boyd
Quoting kgu...@codeaurora.org (2020-02-06 21:57:49)
> On 2020-02-07 00:36, Stephen Boyd wrote:
> > Quoting Kiran Gunda (2020-02-06 05:55:26)
> >> Convert the bindings from .txt to .yaml format.
> >>
> >> Signed-off-by: Kiran Gunda
> >> ---
> >
Quoting Mark Brown (2020-10-02 11:04:30)
> On Fri, Oct 02, 2020 at 10:48:32AM -0700, Stephen Boyd wrote:
> > Quoting Mark Brown (2020-10-02 09:03:24)
>
> > > ...and doing this in the dev_name() should help other diagnostic users
> > > (like dev_printk() for exam
Quoting Guru Das Srinagesh (2020-09-28 15:49:08)
> From: Anirudh Ghayal
>
> VBUS can be detected via a dedicated PMIC pin. Enable compatible string
> that adds support for reporting the VBUS status.
>
> Signed-off-by: Anirudh Ghayal
> Signed-off-by: Guru Das Srinagesh
> ---
> Documentation/de
Quoting Mauro Carvalho Chehab (2020-09-28 23:22:11)
> Hi Stephen,
>
> While double-checking against yesterday's linux-next, I noticed
> that those two patches weren't merge yet.
>
> As you replied to both with your Reviewed-by:, are you expecting
> them to be merged via someone's tree, or are yo
Quoting Mark Brown (2020-10-02 09:03:24)
> On Thu, Oct 01, 2020 at 05:45:00PM -0700, David Collins wrote:
>
> > The SPMI regmap debugfs files are used extensively for testing and debug
> > purposes internally at Qualcomm and by our customers. It would be helpful
> > if the more verbose naming sch
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