K Poulose wrote:
On 08/27/2020 09:44 PM, Mathieu Poirier wrote:
Hi Liu,
On Wed, Aug 19, 2020 at 04:06:37PM +0800, Qi Liu wrote:
When too much trace information is generated on-chip, the ETM will
overflow, and cause data loss. This is a common phenomenon on ETM
devices.
But sometimes we do not
On 11/12/20 10:37 AM, Linu Cherian wrote:
Hi Suzuki,
On Thu, Nov 12, 2020 at 2:51 PM Suzuki K Poulose wrote:
Hi Linu,
Please could you test this slightly modified version and give us
a Tested-by tag if you are happy with the results ?
Suzuki
On 11/10/20 12:45 PM, Anshuman Khandual wrote
On 11/10/20 12:45 PM, Anshuman Khandual wrote:
Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
accessible via the system registers. The TRBE supports different addressing
modes including CPU virtual address and buffer modes including the circular
buffer mode. The TRBE buf
Hi Anshuman,
On 11/10/20 12:45 PM, Anshuman Khandual wrote:
Unlike traditional sink devices, individual TRBE instances are not detected
via DT or ACPI nodes. Instead TRBE instances are detected during CPU online
process. Hence a path connecting ETE and TRBE on a given CPU would not have
been esta
On 11/10/20 12:45 PM, Anshuman Khandual wrote:
perf handle structure needs to be shared with the TRBE IRQ handler for
capturing trace data and restarting the handle. There is a probability
of an undefined reference based crash when etm event is being stopped
while a TRBE IRQ also getting processe
Hi Linu,
Please could you test this slightly modified version and give us
a Tested-by tag if you are happy with the results ?
Suzuki
On 11/10/20 12:45 PM, Anshuman Khandual wrote:
From: Suzuki K Poulose
When there are multiple sinks on the system, in the absence
of a specified sink, it is
On 11/6/20 6:52 PM, Mathieu Poirier wrote:
Good morning,
On Wed, Oct 28, 2020 at 10:09:37PM +, Suzuki K Poulose wrote:
etm4_get_access_type() calculates the exception level bits
for use in address comparator registers. This is also used
by the TRCVICTLR register by shifting to the required
On 11/9/20 8:50 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:45PM +, Suzuki K Poulose wrote:
Document the bindings for ETMs with system register accesses.
Cc: devicet...@vger.kernel.org
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Rob Herring
Signed-off-by: Suzuki K Poulose
On 11/9/20 8:46 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:44PM +, Suzuki K Poulose wrote:
Add support for devices with system instruction access only.
They don't have a memory mapped interface and thus are not
AMBA devices.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-o
On 11/6/20 8:46 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:38PM +, Suzuki K Poulose wrote:
In preparation to detect the support for system instruction
support, move the detection of the device access to the target
CPU.
Signed-off-by: Suzuki K Poulose
---
.../coresight
On 11/9/20 6:32 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:41PM +, Suzuki K Poulose wrote:
As per the specification any update to the TRCPRGCTLR must be synchronized
by a context synchronization event (in our case an explicist ISB) before
the TRCSTATR is checked.
Cc: Mike
On 11/9/20 8:22 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:42PM +, Suzuki K Poulose wrote:
ETM v4.4 onwards adds support for system instruction access
to the ETM. Detect the support on an ETM and switch to using the
mode when available.
Signed-off-by: Suzuki K Poulose
On 11/9/20 9:00 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:26PM +, Suzuki K Poulose wrote:
We are about to introduce support for sysreg access to ETMv4.4+
component. Since there are generic routines that access the
registers (e.g, CS_LOCK/UNLOCK , claim/disclaim operations
On 11/6/20 9:11 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:39PM +, Suzuki K Poulose wrote:
We are about to rely on TRCDEVARCH for detecting the ETM
and its architecture version, falling back to TRCIDR1 if
the former is not implemented (in older broken implementations).
Also
On 11/6/20 8:34 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:38PM +, Suzuki K Poulose wrote:
In preparation to detect the support for system instruction
support, move the detection of the device access to the target
CPU.
Signed-off-by: Suzuki K Poulose
---
.../coresight
On 11/6/20 6:52 PM, Mathieu Poirier wrote:
Good morning,
Good morning.
On Wed, Oct 28, 2020 at 10:09:37PM +, Suzuki K Poulose wrote:
etm4_get_access_type() calculates the exception level bits
for use in address comparator registers. This is also used
by the TRCVICTLR register by
On 11/5/20 9:55 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:36PM +, Suzuki K Poulose wrote:
We rely on the ETM architecture version to decide whether
Secure EL2 is available on the CPU for excluding the level
for address comparators and viewinst main control register.
We must
Hi Mathieu,
On 11/5/20 8:52 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:33PM +, Suzuki K Poulose wrote:
ETMv4.4 architecture defines the system instructions for accessing
ETM via register accesses. Add basic support for accessing a given
register via system instructions.
Cc
On 11/3/20 6:36 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:29PM +, Suzuki K Poulose wrote:
Convert the generic CLAIM tag management APIs to use the
device access layer abstraction.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing
On 11/3/20 6:03 PM, Mathieu Poirier wrote:
On Wed, Oct 28, 2020 at 10:09:28PM +, Suzuki K Poulose wrote:
Convert the generic routines to use the new access abstraction layer
gradually, starting with coresigth_timeout.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K
On 11/3/20 5:25 PM, Mathieu Poirier wrote:
On Tue, Nov 03, 2020 at 10:14:17AM -0700, Mathieu Poirier wrote:
Hi Suzuki,
On Wed, Oct 28, 2020 at 10:09:26PM +, Suzuki K Poulose wrote:
We are about to introduce support for sysreg access to ETMv4.4+
component. Since there are generic routines
On 11/2/20 9:46 PM, Mathieu Poirier wrote:
Hi Suzuki,
On Wed, Oct 28, 2020 at 10:09:25PM +, Suzuki K Poulose wrote:
TRCSSPCICR is present only if all of the following are true:
TRCIDR4.NUMSSCC > n.
TRCIDR4.NUMPC > 0b .
TRCSSCSR.PC == 0b1
Signed-off-by: Su
s-bus-coresight-devices-etb10 | 5 +-
For the above,
Acked-by: Suzuki K Poulose
On 10/29/20 7:53 AM, Mike Leach wrote:
Hi Suzuki,
On Wed, 28 Oct 2020 at 22:10, Suzuki K Poulose wrote:
CoreSight ETMv4.4 obsoletes memory mapped access to ETM and
mandates the system instructions for registers.
This also implies that they may not be on the amba bus.
Right now all the
Joe, Andy
Need your input on the checkpatch failures on this patch. Please
see below.
On 10/28/20 10:09 PM, Suzuki K Poulose wrote:
ETMv4.4 architecture defines the system instructions for accessing
ETM via register accesses. Add basic support for accessing a given
register via system
TRCVIPCSSCTLR is not present if the TRCIDR4.NUMPC > 0. Thus we
should only access the register if it is present, preventing
any undesired behavior.
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 +++
1 file changed, 7 insertions(+)
TRCPROCSELR is not implemented if the TRCIDR3.NUMPROC == 0. Skip
accessing the register in such cases.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions
r claim/disclaim and CS_LOCK/UNLOCK conversions.
- Move device access initialisation for etm4x to the target CPU
- Cleanup secure exception level mask handling.
- Switch to use TRCDEVARCH for ETM component discovery. This
is for making
- Check the availability of OS/Software Locks before
TRCVMIDCTRL1 is only implemented only if the TRCIDR4.NUMVMIDC > 4.
We must not touch the register otherwise.
Cc: sta...@vger.kernel.org
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++---
1 file changed
The TRCCIDCTLR1 is only implemented if TRCIDR4.NUMCIDC > 4.
Don't touch the register if it is not implemented.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++---
1 file changed, 6 insertions(+), 3 d
Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 326 +-
.../coresight/coresight-etm4x-sysfs.c | 9 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 24 ++
3 files changed, 187 insertions(+), 172 deletions(-)
d
As per the specification any update to the TRCPRGCTLR must be synchronized
by a context synchronization event (in our case an explicist ISB) before
the TRCSTATR is checked.
Cc: Mike Leach
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x
handling by adding helpers.
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 60 ++-
2 files changed, 58 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x
Convert the generic routines to use the new access abstraction layer
gradually, starting with coresigth_timeout.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-catu.c | 5 ++--
drivers/hwtracing/coresight/coresight
the access directly
to avoid having to deal with the un-initialised csdev.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tpiu.c | 30 +---
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers
TRCSSPCICR is present only if all of the following are true:
TRCIDR4.NUMSSCC > n.
TRCIDR4.NUMPC > 0b .
TRCSSCSR.PC == 0b1
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 -
1 file changed, 8 insertions
As we are about to add support for sysreg access to ETM4.4+ components,
make sure that we read the registers only on the host CPU.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-sysfs.c | 23 ---
1 file
users by
shifting to their field.
No functional changes, only code cleanups.
Signed-off-by: Suzuki K Poulose
---
Changes since previous version:
- Fix the duplicate shift. More commentary
---
.../coresight/coresight-etm4x-core.c | 47 +--
.../coresight/coresight-etm4x
CoreSight ETM with system register access may not have a
memory mapped i/o access. Refactor the ETM specific probing
into a common routine to allow reusing the code for such ETMs.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c
ETM v4.4 onwards adds support for system instruction access
to the ETM. Detect the support on an ETM and switch to using the
mode when available.
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 39 +++
1 file changed, 39 insertions(+)
diff
The Software lock is not implemented for system instructions
based accesses. So, skip the lock register access in such
cases.
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 40 ---
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git
We have been using TRCIDR1 for detecting the ETM version. This
is in preparation for the future IP support.
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 46 +--
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers
Document the bindings for ETMs with system register accesses.
Cc: devicet...@vger.kernel.org
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Rob Herring
Signed-off-by: Suzuki K Poulose
---
Documentation/devicetree/bindings/arm/coresight.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion
Add support for devices with system instruction access only.
They don't have a memory mapped interface and thus are not
AMBA devices.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 50 +--
1 file ch
Convert the generic CLAIM tag management APIs to use the
device access layer abstraction.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-catu.c | 6 +-
drivers/hwtracing/coresight/coresight-core.c | 66
In preparation to detect the support for system instruction
support, move the detection of the device access to the target
CPU.
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 45 ---
1 file changed, 40 insertions(+), 5 deletions(-)
diff
As we are about define a switch..case table for individual register
access by offset for implementing the system instruction support,
document the possible set of registers for each group to make
it easier to co-relate.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
Since ETMv4.2, TRCIDR3.NUMPROCS has been extended to a 5bit field
by encoding the top 2 bits[4:3] in TRCIDR3.[13:12], which were RES0.
Fix the driver to compute the field correctly for ETMv4.2+
Cc: Mike Leach
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight
r claim/disclaim and CS_LOCK/UNLOCK conversions.
- Move device access initialisation for etm4x to the target CPU
- Cleanup secure exception level mask handling.
- Switch to use TRCDEVARCH for ETM component discovery. This
is for making
- Check the availability of OS/Software Locks before
We rely on the ETM architecture version to decide whether
Secure EL2 is available on the CPU for excluding the level
for address comparators and viewinst main control register.
We must instead use the TRCDIDR3.EXLEVEL_S field to detect
the supported levels.
Signed-off-by: Suzuki K Poulose
layer for the accesses
to a given device.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-catu.c | 1 +
drivers/hwtracing/coresight/coresight-core.c | 49 +
.../hwtracing/coresight/coresight-cti-core.c | 1 +
drivers/hwtracing
ETMv4.4 architecture defines the system instructions for accessing
ETM via register accesses. Add basic support for accessing a given
register via system instructions.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 39
Define the fields of the DEVARCH register for identifying
a component as an ETMv4.x unit. Going forward, we use the
DEVARCH register for the component identification, rather
than the TRCIDR3.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x
On 10/27/20 8:51 AM, ba...@kernel.org wrote:
From: Felipe Balbi
Fix the following build warning:
WARNING: modpost: missing MODULE_LICENSE() in
drivers/hwtracing/coresight/coresight.o
Signed-off-by: Felipe Balbi
Acked-by: Suzuki K Poulose
Hi Sai,
On 10/15/2020 01:45 PM, Sai Prakash Ranjan wrote:
On production systems with ETMs enabled, it is preferred to
exclude kernel mode(NS EL1) tracing for security concerns and
support only userspace(NS EL0) tracing. So provide an option
via kconfig to exclude kernel mode tracing if it is req
On 10/14/2020 10:36 AM, Sai Prakash Ranjan wrote:
On 2020-10-13 22:05, Suzuki K Poulose wrote:
On 10/07/2020 02:00 PM, Sai Prakash Ranjan wrote:
There was a report of NULL pointer dereference in ETF enable
path for perf CS mode with PID monitoring. It is almost 100%
reproducible when the
On 10/07/2020 02:00 PM, Sai Prakash Ranjan wrote:
There was a report of NULL pointer dereference in ETF enable
path for perf CS mode with PID monitoring. It is almost 100%
reproducible when the process to monitor is something very
active such as chrome and with ETF as the sink and not ETR.
Curren
TRCCIDCCTLR1);
writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0);
- writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR1);
+ writel_relaxed(state->trcvmidcctlr1, drvdata->base + TRCVMIDCCTLR1);
Reviewed-by: Suzuki K Poulose
| 63 +-
1 file changed, 57 insertions(+), 6 deletions(-)
diff --git a/drivers/perf/arm_dsu_pmu.c b/drivers/perf/arm_dsu_pmu.c
index 96ed93c..98e68ed 100644
--- a/drivers/perf/arm_dsu_pmu.c
+++ b/drivers/perf/arm_dsu_pmu.c
Reviewed-by: Suzuki K Poulose
functions, for module unload
- add a MODULE_DEVICE_TABLE for autoloading on boot
Cc: Mathieu Poirier
Cc: Leo Yan
Cc: Alexander Shishkin
Cc: Randy Dunlap
Cc: Suzuki K Poulose
Cc: Greg Kroah-Hartman
Cc: Russell King
Co-developed-by: Mian Yousaf Kaukab
Signed-off-by: Mian Yousaf Kaukab
Signed-off-by
active session.
Signed-off-by: Tingwei Zhang
Tested-by: Mike Leach
Suggested-by: Suzuki K Poulose
Reviewed-by: Suzuki K Poulose
Hi Tuan
On 09/14/2020 05:21 PM, Tuan Phan wrote:
Reported-by: kernel test robot mailto:l...@intel.com>>
All warnings (new ones prefixed by >>):
drivers/perf/arm_dsu_pmu.c:799:36: warning: unused variable
'dsu_pmu_acpi_match' [-Wunused-const-variable]
static const struct acpi_device_id dsu
autoloading on boot
Cc: Mathieu Poirier
Cc: Leo Yan
Cc: Alexander Shishkin
Cc: Randy Dunlap
Cc: Suzuki K Poulose
Cc: Greg Kroah-Hartman
Cc: Russell King
Co-developed-by: Mian Yousaf Kaukab
Signed-off-by: Mian Yousaf Kaukab
Signed-off-by: Kim Phillips
Signed-off-by: Tingwei Zhang
Reported
autoloading on boot
Cc: Mathieu Poirier
Cc: Leo Yan
Cc: Alexander Shishkin
Cc: Randy Dunlap
Cc: Suzuki K Poulose
Cc: Greg Kroah-Hartman
Cc: Russell King
Co-developed-by: Mian Yousaf Kaukab
Signed-off-by: Mian Yousaf Kaukab
Signed-off-by: Kim Phillips
Signed-off-by: Tingwei Zhang
Reported
etm4_remove function, for module unload
- add a MODULE_DEVICE_TABLE for autoloading on boot
- delay advertising the per-cpu etmdrvdata
- protect etmdrvdata[] by modifying it on relevant CPU
Cc: Mathieu Poirier
Cc: Leo Yan
Cc: Alexander Shishkin
Cc: Randy Dunlap
Cc: Suzuki K Poulose
Cc: Greg Kroah
function, for module unload
- add a MODULE_DEVICE_TABLE for autoloading on boot
Cc: Mathieu Poirier
Cc: Leo Yan
Cc: Alexander Shishkin
Cc: Randy Dunlap
Cc: Suzuki K Poulose
Cc: Greg Kroah-Hartman
Cc: Russell King
Signed-off-by: Kim Phillips
Signed-off-by: Tingwei Zhang
Reviewed-by: Mike
On 09/10/2020 08:07 PM, Tuan Phan wrote:
Hi Will,
On Sep 10, 2020, at 6:40 AM, kernel test robot wrote:
Hi Tuan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.9-rc4 next-20200910]
[If your patch is applied to
On 09/07/2020 12:02 PM, Will Deacon wrote:
[+ Suzuki as I'd like his Ack on this]
Thanks Will !
On Fri, Aug 14, 2020 at 05:39:40PM -0700, Tuan Phan wrote:
Add support for probing device from ACPI node.
Each DSU ACPI node and its associated cpus are inside a cluster node.
Signed-off-by: Tua
be to get syscall args filenames
75: Use vfs_getname probe to get syscall args filenames
# perf test 71
71: Check Arm CoreSight trace data recording and branch samples: Ok
Signed-off-by: Leo Yan
Leo,
Thank you so much for testcase !
Reviewed-by: Suzuki K Poulose
On 09/07/2020 08:29 AM, Leo Yan wrote:
We need a simple method to test Perf with Arm CoreSight drivers, this
could be used for smoke testing when new patch is coming for perf or
CoreSight drivers, and we also can use the test to confirm if the
CoreSight has been enabled successfully on new platfo
oirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
Change since v1:
- Updated the description, added Tested-by.
- No code changes
- Rebased on coresight/next
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/hwtrac
On 08/27/2020 09:44 PM, Mathieu Poirier wrote:
Hi Liu,
On Wed, Aug 19, 2020 at 04:06:37PM +0800, Qi Liu wrote:
When too much trace information is generated on-chip, the ETM will
overflow, and cause data loss. This is a common phenomenon on ETM
devices.
But sometimes we do not want to lose perf
On 08/19/2020 08:22 PM, Mathieu Poirier wrote:
Hi Suzuki,
On Tue, Aug 18, 2020 at 08:29:31PM +0100, Suzuki K Poulose wrote:
If the specified/hinted sink is not reachable from a subset of the CPUs,
we could end up unable to trace the event on those CPUs. This
is the best effort we could do
] el0_sync+0x140/0x180
Fixes: f9d81a657bb8 ("coresight: perf: Allow tracing on hotplugged CPUs")
Reported-by: Jeremy Linton
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 10 ++
1 file changed, 10
-Hip08 */
+ CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
Acked-by: Suzuki K Poulose
gt;child_port;
+ if (ptr->child_port >= pdata->nr_inport)
+ pdata->nr_inport = ptr->child_port + 1;
}
}
I was about to post a similar fix following a report from
Jeremy. This looks fine to me.
Reviewed-by: Suzuki K Poulose
Hi Leo,
On 08/06/2020 08:02 AM, Leo Yan wrote:
We need a simple method to test Perf with Arm CoreSight drivers, this
could be used for smoke testing when new patch is coming for perf or
CoreSight drivers, and we also can use the test to confirm if the
CoreSight has been enabled successfully on n
_pgd")
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
---
Reviewed-by: Suzuki K Poulose
Hi Qi
On 08/03/2020 02:35 PM, Qi Liu wrote:
Add ETMv4 periperhal ID for HiSilicon Hip08 and Hip09 platform. Hip08
contains ETMv4.2 device and Hip09 contains ETMv4.5 device.
Does the ETMv4.5 on your system implement system instructions to access
the ETMs ? If so, please could you give the follo
quot;hwtracing/coresight-etm4x: Convert to hotplug state
machine")
Suggested-by: Suzuki K Poulose
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Suzuki K Poulose
On 07/31/2020 01:18 PM, liwei (GF) wrote:
On 2020/7/30 16:14, Leo Yan wrote:
Hi Suzuki,
On Wed, Jul 29, 2020 at 10:12:50AM +0100, Suzuki Kuruppassery Poulose wrote:
On 07/24/2020 10:16 AM, Wei Li wrote:
Armv8.3 extends the SPE by adding:
- Alignment field in the Events packet, and filtering
On 07/29/2020 10:01 PM, Mathieu Poirier wrote:
On Wed, Jul 22, 2020 at 06:20:29PM +0100, Suzuki K Poulose wrote:
TPIU driver access the device before the coresight device
is registered. In other words, before the drvdata->csdev
is valid. Thus, we need to make sure that the csdev_access
is va
On 07/30/2020 10:41 PM, Mathieu Poirier wrote:
On Wed, Jul 22, 2020 at 06:20:35PM +0100, Suzuki K Poulose wrote:
ETMv4.4 architecture defines the system instructions for accessing
ETM via register accesses. Add basic support for accessing a given
register via system instructions.
Cc: Mathieu
On 07/30/2020 09:20 PM, Mathieu Poirier wrote:
On Wed, Jul 22, 2020 at 06:20:34PM +0100, Suzuki K Poulose wrote:
Convert all register accesses from etm4x driver to use a wrapper
to allow switching the access at runtime with little overhead.
co-developed by sed tool ;-), mostly equivalent to
On 07/30/2020 08:54 PM, Mathieu Poirier wrote:
On Wed, Jul 22, 2020 at 06:20:32PM +0100, Suzuki K Poulose wrote:
Convert the CoreSight CLAIM set/clear, LOCK/UNLOCK operations to
use the coresight device access abstraction.
Mostly a mechanical change.
Cc: Mathieu Poirier
Cc: Mike Leach
On 07/30/2020 06:31 PM, Mathieu Poirier wrote:
On Wed, Jul 22, 2020 at 06:20:30PM +0100, Suzuki K Poulose wrote:
etm4_init_arch_data is called early during the device probe,
even before the coresight_device is registered. Since we are
about to replace the direct access via abstraction layer, we
On 07/29/2020 06:20 PM, Mathieu Poirier wrote:
On Wed, Jul 22, 2020 at 06:20:40PM +0100, Suzuki K Poulose wrote:
Document the bindings for ETMv4.4 and later with only system register
access.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by
On 07/29/2020 08:56 PM, Mathieu Poirier wrote:
On Wed, Jul 22, 2020 at 06:20:28PM +0100, Suzuki K Poulose wrote:
We are about to introduce support for sysreg access to ETMv4.4+
component. Since there are generic routines that access the
registers (e.g, CS_LOCK/UNLOCK , claim/disclaim operations
On 07/29/2020 07:01 PM, Mathieu Poirier wrote:
Hi Suzuki,
I have starte to review this - comments will be scattered over a few days.
On Wed, Jul 22, 2020 at 06:20:27PM +0100, Suzuki K Poulose wrote:
Skip cpu save/restore before the coresight device is registered.
Cc: Mathieu Poirier
Cc
On 07/24/2020 10:16 AM, Wei Li wrote:
Armv8.3 extends the SPE by adding:
- Alignment field in the Events packet, and filtering on this event
using PMSEVFR_EL1.
- Support for the Scalable Vector Extension (SVE).
The main additions for SVE are:
- Recording the vector length for SVE operations i
On 07/27/2020 07:07 AM, Sai Prakash Ranjan wrote:
etm4_count keeps track of number of ETMv4 registered and on some
systems, a race is observed on etm4_count variable which can
lead to multiple calls to cpuhp_setup_state_nocalls_cpuslocked().
This function internally calls cpuhp_store_callbacks()
available
via etmdrvdata[smp_processor_id()].
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b
ata->base + \(.*\))/etm4x_\1_write32(csdev,
\2, \3)
We don't want to replace them with the csdev_access_* to
avoid a function call for every register access for system
register access.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-et
CoreSight ETM with system register access may not have a
memory mapped i/o access. Refactor the ETM specific probing
into a common routine to allow reusing the code for such ETMs.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight
Convert the generic routines to use the new access abstraction layer
gradually, starting with coresigth_timeout.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-catu.c | 2 +-
drivers/hwtracing/coresight/coresight-etb10.c | 5
: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x.c | 76 +++
drivers/hwtracing/coresight/coresight-etm4x.h | 16
2 files changed, 78 insertions(+), 14 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b/drivers/hwtracing/coresight/coresight
As we are about to add support for sysreg access to ETM4.4+ components,
make sure that we read the registers only on the host CPU.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-sysfs.c | 23 ---
1 file changed, 10
Convert the CoreSight CLAIM set/clear, LOCK/UNLOCK operations to
use the coresight device access abstraction.
Mostly a mechanical change.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-catu.c | 14 ++--
.../hwtracing/coresight
Document the bindings for ETMv4.4 and later with only system register
access.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
Documentation/devicetree/bindings/arm/coresight.txt | 6 +-
1 file changed, 5 insertions
Define the fields of the DEVARCH register for identifying
a component as an ETMv4.x unit.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++--
drivers/hwtracing/coresight/coresight-etm4x.h | 16
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